|  | CMSIS-CORE
    Version 3.20
    CMSIS-CORE support for Cortex-M processor-based devices | 
Structure type to access the Trace Port Interface Register (TPI).
| Data Fields | |
| __IO uint32_t | SSPSR | 
| Offset: 0x000 (R/ ) Supported Parallel Port Size Register.  More... | |
| __IO uint32_t | CSPSR | 
| Offset: 0x004 (R/W) Current Parallel Port Size Register.  More... | |
| uint32_t | RESERVED0 [2] | 
| Reserved.  More... | |
| __IO uint32_t | ACPR | 
| Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register.  More... | |
| uint32_t | RESERVED1 [55] | 
| Reserved.  More... | |
| __IO uint32_t | SPPR | 
| Offset: 0x0F0 (R/W) Selected Pin Protocol Register.  More... | |
| uint32_t | RESERVED2 [131] | 
| Reserved.  More... | |
| __I uint32_t | FFSR | 
| Offset: 0x300 (R/ ) Formatter and Flush Status Register.  More... | |
| __IO uint32_t | FFCR | 
| Offset: 0x304 (R/W) Formatter and Flush Control Register.  More... | |
| __I uint32_t | FSCR | 
| Offset: 0x308 (R/ ) Formatter Synchronization Counter Register.  More... | |
| uint32_t | RESERVED3 [759] | 
| Reserved.  More... | |
| __I uint32_t | TRIGGER | 
| Offset: 0xEE8 (R/ ) TRIGGER.  More... | |
| __I uint32_t | FIFO0 | 
| Offset: 0xEEC (R/ ) Integration ETM Data.  More... | |
| __I uint32_t | ITATBCTR2 | 
| Offset: 0xEF0 (R/ ) ITATBCTR2.  More... | |
| uint32_t | RESERVED4 [1] | 
| Reserved.  More... | |
| __I uint32_t | ITATBCTR0 | 
| Offset: 0xEF8 (R/ ) ITATBCTR0.  More... | |
| __I uint32_t | FIFO1 | 
| Offset: 0xEFC (R/ ) Integration ITM Data.  More... | |
| __IO uint32_t | ITCTRL | 
| Offset: 0xF00 (R/W) Integration Mode Control.  More... | |
| uint32_t | RESERVED5 [39] | 
| Reserved.  More... | |
| __IO uint32_t | CLAIMSET | 
| Offset: 0xFA0 (R/W) Claim tag set.  More... | |
| __IO uint32_t | CLAIMCLR | 
| Offset: 0xFA4 (R/W) Claim tag clear.  More... | |
| uint32_t | RESERVED7 [8] | 
| Reserved.  More... | |
| __I uint32_t | DEVID | 
| Offset: 0xFC8 (R/ ) TPIU_DEVID.  More... | |
| __I uint32_t | DEVTYPE | 
| Offset: 0xFCC (R/ ) TPIU_DEVTYPE.  More... | |
| __IO uint32_t TPI_Type::ACPR | 
| __IO uint32_t TPI_Type::CLAIMCLR | 
| __IO uint32_t TPI_Type::CLAIMSET | 
| __IO uint32_t TPI_Type::CSPSR | 
| __I uint32_t TPI_Type::DEVID | 
| __I uint32_t TPI_Type::DEVTYPE | 
| __IO uint32_t TPI_Type::FFCR | 
| __I uint32_t TPI_Type::FFSR | 
| __I uint32_t TPI_Type::FIFO0 | 
| __I uint32_t TPI_Type::FIFO1 | 
| __I uint32_t TPI_Type::FSCR | 
| __I uint32_t TPI_Type::ITATBCTR0 | 
| __I uint32_t TPI_Type::ITATBCTR2 | 
| __IO uint32_t TPI_Type::ITCTRL | 
| uint32_t TPI_Type::RESERVED0[2] | 
| uint32_t TPI_Type::RESERVED1[55] | 
| uint32_t TPI_Type::RESERVED2[131] | 
| uint32_t TPI_Type::RESERVED3[759] | 
| uint32_t TPI_Type::RESERVED4[1] | 
| uint32_t TPI_Type::RESERVED5[39] | 
| uint32_t TPI_Type::RESERVED7[8] | 
| __IO uint32_t TPI_Type::SPPR | 
| __IO uint32_t TPI_Type::SSPSR | 
| __I uint32_t TPI_Type::TRIGGER |