diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
index 12d926fa0c691c7e6ea0f28a04e6b639e71988c9..98f322cce9ab50c0a6395752b9583a3c27144875 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
@@ -168,7 +168,7 @@ void configureSdram() {
                          | FMC_SDCR2_NB        // 4 internal banks
                          | FMC_SDCR2_MWID_0    // 16 bit data bus
                          | FMC_SDCR2_NR_1      // 13 bit row address
-                         | FMC_SDCR2_NC_1;     // 9 bit column address
+                         | FMC_SDCR2_NC_0;     // 9 bit column address
 
     // 2. Memory device timings
     #ifdef SYSCLK_FREQ_216MHz