From 1ed8d4360ca7718afc19c676638814175fd13442 Mon Sep 17 00:00:00 2001
From: Emilio Corigliano <emilio.corigliano@skywarder.eu>
Date: Mon, 12 Feb 2024 18:06:45 +0100
Subject: [PATCH] [compute_unit_v2] Fixed ram 9 bit column address setting
---
.../stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
index 12d926fa..98f322cc 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
@@ -168,7 +168,7 @@ void configureSdram() {
| FMC_SDCR2_NB // 4 internal banks
| FMC_SDCR2_MWID_0 // 16 bit data bus
| FMC_SDCR2_NR_1 // 13 bit row address
- | FMC_SDCR2_NC_1; // 9 bit column address
+ | FMC_SDCR2_NC_0; // 9 bit column address
// 2. Memory device timings
#ifdef SYSCLK_FREQ_216MHz
--
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