diff --git a/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h
index 2d739f367d2085296a3aba05e0fe2b757fcfd7c6..22cd07b67aa3f3c6667742b6982291a10ba01fa9 100644
--- a/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h
+++ b/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h
@@ -30,7 +30,7 @@
 namespace miosix {
 
 /**
- * \addtogroup Settings
+ * \addtogroup Interfaces
  * \{
  */
 
@@ -47,6 +47,9 @@ const unsigned int CTXSAVE_ON_STACK=0;
 /// \internal Stack alignment required by the CPU
 const unsigned int CTXSAVE_STACK_ALIGNMENT=4;
 
+/// \internal Offset in words to retrieve the thread stack pointer in ctxsave
+const unsigned int STACK_OFFSET_IN_CTXSAVE=13;
+
 /**
  * \}
  */
diff --git a/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h
index d1c1d4e77954e783de5d07e3904b1efaff48319b..ebdcfbe41b491ce2dfca555990f7e4e795078e89 100644
--- a/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h
+++ b/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h
@@ -32,6 +32,27 @@
  * \{
  */
 
+/*
+ * In this architecture, registers are saved in the following order:
+ * *ctxsave+64 --> cpsr
+ * *ctxsave+60 --> pc (return address)
+ * *ctxsave+56 --> lr
+ * *ctxsave+52 --> sp
+ * *ctxsave+48 --> r12
+ * *ctxsave+44 --> r11
+ * *ctxsave+40 --> r10
+ * *ctxsave+36 --> r9
+ * *ctxsave+32 --> r8
+ * *ctxsave+28 --> r7
+ * *ctxsave+24 --> r6
+ * *ctxsave+20 --> r5
+ * *ctxsave+16 --> r4
+ * *ctxsave+12 --> r3
+ * *ctxsave+8  --> r2
+ * *ctxsave+4  --> r1
+ * *ctxsave+0  --> r0
+ */
+
 /**
  * \internal
  * \def saveContextFromSwi()
@@ -137,32 +158,6 @@ inline void doYield()
                  :::"r3");
 }
 
-/**
- * \internal
- * Allows to retrieve the saved stack pointer in a portable way as
- * ctxsave[stackPtrOffsetInCtxsave]
- *
- * In this architecture, registers are saved in the following order:
- * *ctxsave+64 --> cpsr
- * *ctxsave+60 --> pc (return address)
- * *ctxsave+56 --> lr
- * *ctxsave+52 --> sp
- * *ctxsave+48 --> r12
- * *ctxsave+44 --> r11
- * *ctxsave+40 --> r10
- * *ctxsave+36 --> r9
- * *ctxsave+32 --> r8
- * *ctxsave+28 --> r7
- * *ctxsave+24 --> r6
- * *ctxsave+20 --> r5
- * *ctxsave+16 --> r4
- * *ctxsave+12 --> r3
- * *ctxsave+8  --> r2
- * *ctxsave+4  --> r1
- * *ctxsave+0  --> r0
- */
-const int stackPtrOffsetInCtxsave=13;
-
 } //namespace miosix
 
 /**
diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h
index e5867ea3d6ccfe5623194618b2537ace31a44cf8..6a11c08b6c20a487160ade4eee0caa1bb5cb536e 100644
--- a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h
+++ b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h
@@ -30,7 +30,7 @@
 namespace miosix {
 
 /**
- * \addtogroup Settings
+ * \addtogroup Interfaces
  * \{
  */
 
@@ -48,6 +48,9 @@ const unsigned int CTXSAVE_ON_STACK=32;
 /// \internal Stack alignment required by the CPU
 const unsigned int CTXSAVE_STACK_ALIGNMENT=8;
 
+/// \internal Offset in words to retrieve the thread stack pointer in ctxsave
+const unsigned int STACK_OFFSET_IN_CTXSAVE=0;
+
 /**
  * \}
  */
diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h
index d3175e8c5b29cacd297a9299a3906e671065f32f..30cdb19267b119d5b9796cb0de9f843e6e528dbb 100644
--- a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h
+++ b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h
@@ -34,6 +34,19 @@
  * \{
  */
 
+/*
+ * In this architecture, registers are saved in the following order:
+ * *ctxsave+32 --> r11
+ * *ctxsave+28 --> r10
+ * *ctxsave+24 --> r9
+ * *ctxsave+20 --> r8
+ * *ctxsave+16 --> r7
+ * *ctxsave+12 --> r6
+ * *ctxsave+8  --> r5
+ * *ctxsave+4  --> r4
+ * *ctxsave+0  --> psp
+ */
+
 /**
  * \internal
  * \def saveContext()
@@ -96,24 +109,6 @@ inline void doYield()
     asm volatile("dmb":::"memory");
 }
 
-/**
- * \internal
- * Allows to retrieve the saved stack pointer in a portable way as
- * ctxsave[stackPtrOffsetInCtxsave]
- *
- * In this architecture, registers are saved in the following order:
- * *ctxsave+32 --> r11
- * *ctxsave+28 --> r10
- * *ctxsave+24 --> r9
- * *ctxsave+20 --> r8
- * *ctxsave+16 --> r7
- * *ctxsave+12 --> r6
- * *ctxsave+8  --> r5
- * *ctxsave+4  --> r4
- * *ctxsave+0  --> psp
- */
-const int stackPtrOffsetInCtxsave=0;
-
 } //namespace miosix
 
 /**
diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h
index 7c4de9fdce4de2e3e5f6414bd4530241cac604e3..deb7eded65660006b7aab2ff6e69373f2688c2b0 100644
--- a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h
+++ b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h
@@ -32,11 +32,14 @@
 #ifndef __FPU_PRESENT
 #define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU
 #endif
+#if (__FPU_PRESENT!=0) && (__FPU_USED!=1)
+#error "__FPU_USED should be 1"
+#endif
 
 namespace miosix {
 
 /**
- * \addtogroup Settings
+ * \addtogroup Interfaces
  * \{
  */
 
@@ -77,6 +80,9 @@ const unsigned int CTXSAVE_ON_STACK=32;
 /// \internal Stack alignment required by the CPU
 const unsigned int CTXSAVE_STACK_ALIGNMENT=8;
 
+/// \internal Offset in words to retrieve the thread stack pointer in ctxsave
+const unsigned int STACK_OFFSET_IN_CTXSAVE=0;
+
 /**
  * \}
  */
diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h
index b0c7abae1d2039061a586eb4d079ac11c081da12..61920a9b75ea2e4d50c8c114a23579bef536182e 100644
--- a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h
+++ b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h
@@ -32,9 +32,6 @@
 #ifndef __FPU_PRESENT
 #define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU
 #endif
-#if (__FPU_PRESENT!=0) && (__FPU_USED!=1)
-#error "__FPU_USED should be 1"
-#endif
 
 /**
  * \addtogroup Interfaces
@@ -43,6 +40,23 @@
 
 #if __FPU_PRESENT==1
 
+/*
+ * In this architecture, registers are saved in the following order:
+ * *ctxsave+100 --> s31
+ * ...
+ * *ctxsave+40  --> s16
+ * *ctxsave+36  --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used)
+ * *ctxsave+32  --> r11
+ * *ctxsave+28  --> r10
+ * *ctxsave+24  --> r9
+ * *ctxsave+20  --> r8
+ * *ctxsave+16  --> r7
+ * *ctxsave+12  --> r6
+ * *ctxsave+8   --> r5
+ * *ctxsave+4   --> r4
+ * *ctxsave+0   --> psp
+ */
+
 /**
  * \internal
  * \def saveContext()
@@ -89,6 +103,19 @@
 
 #else //__FPU_PRESENT==1
 
+/*
+ * In this architecture, registers are saved in the following order:
+ * *ctxsave+32 --> r11
+ * *ctxsave+28 --> r10
+ * *ctxsave+24 --> r9
+ * *ctxsave+20 --> r8
+ * *ctxsave+16 --> r7
+ * *ctxsave+12 --> r6
+ * *ctxsave+8  --> r5
+ * *ctxsave+4  --> r4
+ * *ctxsave+0  --> psp
+ */
+
 /**
  * \internal
  * \def saveContext()
@@ -143,52 +170,6 @@ inline void doYield()
     asm volatile("dmb":::"memory");
 }
 
-#if __FPU_PRESENT==1
-
-/**
- * \internal
- * Allows to retrieve the saved stack pointer in a portable way as
- * ctxsave[stackPtrOffsetInCtxsave]
- *
- * In this architecture, registers are saved in the following order:
- * *ctxsave+100 --> s31
- * ...
- * *ctxsave+40  --> s16
- * *ctxsave+36  --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used)
- * *ctxsave+32  --> r11
- * *ctxsave+28  --> r10
- * *ctxsave+24  --> r9
- * *ctxsave+20  --> r8
- * *ctxsave+16  --> r7
- * *ctxsave+12  --> r6
- * *ctxsave+8   --> r5
- * *ctxsave+4   --> r4
- * *ctxsave+0   --> psp
- */
-const int stackPtrOffsetInCtxsave=0;
-
-#else //__FPU_PRESENT==1
-
-/**
- * \internal
- * Allows to retrieve the saved stack pointer in a portable way as
- * ctxsave[stackPtrOffsetInCtxsave]
- *
- * In this architecture, registers are saved in the following order:
- * *ctxsave+32 --> r11
- * *ctxsave+28 --> r10
- * *ctxsave+24 --> r9
- * *ctxsave+20 --> r8
- * *ctxsave+16 --> r7
- * *ctxsave+12 --> r6
- * *ctxsave+8  --> r5
- * *ctxsave+4  --> r4
- * *ctxsave+0  --> psp
- */
-const int stackPtrOffsetInCtxsave=0;
-
-#endif //__FPU_PRESENT==1
-
 } //namespace miosix
 
 /**
diff --git a/miosix/interfaces/cpu_const.h b/miosix/interfaces/cpu_const.h
index dad32b9b295769ccba85f7f1ab6a6d8790628f23..2b6eb2d1e8561adf013c8caaf165b35e570c2e5a 100644
--- a/miosix/interfaces/cpu_const.h
+++ b/miosix/interfaces/cpu_const.h
@@ -47,6 +47,9 @@
  *
  * Stack alignment required by the CPU
  * const unsigned int CTXSAVE_STACK_ALIGNMENT=...;
+ *
+ * Offset in words to retrieve the thread stack pointer in ctxsave
+ * const unsigned int STACK_OFFSET_IN_CTXSAVE=...;
  */
 
 /**
diff --git a/miosix/interfaces_private/cpu.h b/miosix/interfaces_private/cpu.h
index b8bce4a2f14117be7a90a79eaea0bbff4ad199b7..b702cf03c1c3f7aa8665638feefcb362ab4f3fd6 100644
--- a/miosix/interfaces_private/cpu.h
+++ b/miosix/interfaces_private/cpu.h
@@ -52,11 +52,6 @@
  * //Restore context in an IRQ where saveContext() is used
  * #define restoreContext()
  *
- * namespace miosix {
- * ///Allows to retrieve the saved stack pointer in a portable way as
- * ///ctxsave[stackPtrOffsetInCtxsave]
- * const int stackPtrOffsetInCtxsave=...;
- * }
  * \endcode
  */
 
diff --git a/miosix/kernel/kernel.cpp b/miosix/kernel/kernel.cpp
index 0b80bd189183597d2256afa7e66c1dab9452d2ed..4fbd36a7d1eb8fb8b56210be9d66580cad9b5fd0 100755
--- a/miosix/kernel/kernel.cpp
+++ b/miosix/kernel/kernel.cpp
@@ -624,7 +624,7 @@ bool Thread::IRQstackOverflowCheck()
     if(const_cast<Thread*>(runningThread)->flags.isInUserspace())
     {
         bool overflow=false;
-        if(runningThread->userCtxsave[stackPtrOffsetInCtxsave] <
+        if(runningThread->userCtxsave[STACK_OFFSET_IN_CTXSAVE] <
             reinterpret_cast<unsigned int>(runningThread->userWatermark+watermarkSize))
             overflow=true;
         if(overflow==false)
@@ -634,7 +634,7 @@ bool Thread::IRQstackOverflowCheck()
         return overflow;
     }
     #endif //WITH_PROCESSES
-    if(runningThread->ctxsave[stackPtrOffsetInCtxsave] <
+    if(runningThread->ctxsave[STACK_OFFSET_IN_CTXSAVE] <
         reinterpret_cast<unsigned int>(runningThread->watermark+watermarkSize))
         errorHandler(STACK_OVERFLOW);
     for(unsigned int i=0;i<watermarkSize;i++)