diff --git a/miosix/arch/common/drivers/serial_stm32.cpp b/miosix/arch/common/drivers/serial_stm32.cpp
index 798d66b7164a85172f5c5a82fba251089127e59a..4c5448e8fb83e58cfa126bcebbdca011a10bfe6b 100644
--- a/miosix/arch/common/drivers/serial_stm32.cpp
+++ b/miosix/arch/common/drivers/serial_stm32.cpp
@@ -449,7 +449,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
             #endif //!defined(_ARCH_CORTEXM0_STM32F0)            
             break;
     }
-    #endif //_ARCH_CORTEXM3_STM32
+    #endif //_ARCH_CORTEXM3_STM32F1
     
     switch(id)
     {
@@ -703,11 +703,11 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
     }
     //Quirk: stm32f1 rx pin has to be in input mode, while stm32f2 and up want
     //it in ALTERNATE mode. Go figure...
-    #ifdef _ARCH_CORTEXM3_STM32
+    #ifdef _ARCH_CORTEXM3_STM32F1
     Mode::Mode_ rxPinMode=Mode::INPUT;
-    #else //_ARCH_CORTEXM3_STM32
+    #else //_ARCH_CORTEXM3_STM32F1
     Mode::Mode_ rxPinMode=Mode::ALTERNATE;
-    #endif //_ARCH_CORTEXM3_STM32
+    #endif //_ARCH_CORTEXM3_STM32F1
     tx.mode(Mode::ALTERNATE);
     rx.mode(rxPinMode);
     if(flowControl)
@@ -844,10 +844,10 @@ void STM32Serial::IRQwrite(const char *str)
         constexpr unsigned int DMA_CCR4_EN = DMA_CCR_EN;
         #endif
         while((dmaTx->CCR & DMA_CCR4_EN) && !(DMA1->ISR & irqMask[getId()-1])) ;
-        #else //_ARCH_CORTEXM3_STM32
+        #else //_ARCH_CORTEXM3_STM32F1
         //Wait until DMA xfer ends. EN bit is cleared by hardware on transfer end
         while(dmaTx->CR & DMA_SxCR_EN) ;
-        #endif //_ARCH_CORTEXM3_STM32
+        #endif //_ARCH_CORTEXM3_STM32F1
     }
     #endif //SERIAL_DMA
     while(*str)
@@ -1158,7 +1158,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
                    | DMA_SxCR_DMEIE   //Interrupt on direct mode error
                    | DMA_SxCR_EN;     //Start the DMA
     #endif //_ARCH_CORTEXM4_STM32F3
-    #endif //_ARCH_CORTEXM3_STM32
+    #endif //_ARCH_CORTEXM3_STM32F1
 }
 
 void STM32Serial::IRQreadDma()
@@ -1208,7 +1208,7 @@ void STM32Serial::IRQdmaReadStart()
                    | DMA_SxCR_DMEIE   //Interrupt on direct mode error
                    | DMA_SxCR_EN;     //Start the DMA
     #endif //_ARCH_CORTEXM4_STM32F3
-    #endif //_ARCH_CORTEXM3_STM32
+    #endif //_ARCH_CORTEXM3_STM32F1
 }
 
 int STM32Serial::IRQdmaReadStop()
@@ -1224,7 +1224,7 @@ int STM32Serial::IRQdmaReadStop()
     };
     DMA1->IFCR=irqMask[getId()-1];
     return rxQueueMin-dmaRx->CNDTR;
-    #else //_ARCH_CORTEXM3_STM32
+    #else //_ARCH_CORTEXM3_STM32F1
     //Stop DMA and wait for it to actually stop
     dmaRx->CR &= ~DMA_SxCR_EN;
     while(dmaRx->CR & DMA_SxCR_EN) ;
@@ -1242,7 +1242,7 @@ int STM32Serial::IRQdmaReadStop()
     };
     *irqRegs[getId()-1]=irqMask[getId()-1];
     return rxQueueMin-dmaRx->NDTR;
-    #endif //_ARCH_CORTEXM3_STM32
+    #endif //_ARCH_CORTEXM3_STM32F1
 }
 #endif //SERIAL_DMA
 
diff --git a/miosix/arch/common/drivers/servo_stm32.cpp b/miosix/arch/common/drivers/servo_stm32.cpp
index c4023f6ffc6e2a81aee25c8dedde41c23c9d9d0f..07dcf7768c5e101f6111f0befe5634e202c7bf2f 100644
--- a/miosix/arch/common/drivers/servo_stm32.cpp
+++ b/miosix/arch/common/drivers/servo_stm32.cpp
@@ -98,7 +98,7 @@ void SynchronizedServo::enable(int channel)
                 TIM4->CCER |= TIM_CCER_CC1E;
                 #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo1out::alternateFunction(2);
-                #endif //_ARCH_CORTEXM3_STM32
+                #endif //_ARCH_CORTEXM3_STM32F1
                 servo1out::mode(Mode::ALTERNATE);
                 break;
             case 1:
@@ -106,7 +106,7 @@ void SynchronizedServo::enable(int channel)
                 TIM4->CCER |= TIM_CCER_CC2E;
                 #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo2out::alternateFunction(2);
-                #endif //_ARCH_CORTEXM3_STM32
+                #endif //_ARCH_CORTEXM3_STM32F1
                 servo2out::mode(Mode::ALTERNATE);
                 break;
             case 2:
@@ -114,7 +114,7 @@ void SynchronizedServo::enable(int channel)
                 TIM4->CCER |= TIM_CCER_CC3E;
                 #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo3out::alternateFunction(2);
-                #endif //_ARCH_CORTEXM3_STM32
+                #endif //_ARCH_CORTEXM3_STM32F1
                 servo3out::mode(Mode::ALTERNATE);
                 break;
             case 3:
@@ -122,7 +122,7 @@ void SynchronizedServo::enable(int channel)
                 TIM4->CCER |= TIM_CCER_CC4E;
                 #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo4out::alternateFunction(2);
-                #endif //_ARCH_CORTEXM3_STM32
+                #endif //_ARCH_CORTEXM3_STM32F1
                 servo4out::mode(Mode::ALTERNATE);
                 break;
         }
@@ -321,7 +321,7 @@ unsigned int SynchronizedServo::getPrescalerInputFrequency()
     unsigned int freq=SystemCoreClock;
     
     //The position of the PPRE1 bit in RCC->CFGR is different in some stm32
-    #ifdef _ARCH_CORTEXM3_STM32
+    #ifdef _ARCH_CORTEXM3_STM32F1
     const unsigned int ppre1=8;
     #else //stm32f2 and f4
     const unsigned int ppre1=10;