From 48e8ab0db551341ce08892ef4c6096711d05f556 Mon Sep 17 00:00:00 2001
From: Terraneo Federico <fede.tft@hotmail.it>
Date: Sun, 29 Apr 2012 14:32:45 +0200
Subject: [PATCH] Added new board als_mainboard
---
Makefile | 2 +-
.../board_settings.h | 0
.../core/stage_1_boot.cpp | 0
.../interfaces-impl/bsp.cpp | 0
.../interfaces-impl/bsp_impl.h | 0
.../interfaces-impl/console-impl.h | 0
.../interfaces-impl/console.cpp | 0
.../interfaces-impl/delays.cpp | 0
.../interfaces-impl/hwmapping.h | 0
.../stm32_1m+128k_rom.ld | 0
.../Documentation/CMSIS-SVD_Schema_1_0.xsd | 274 +
.../CMSIS/Documentation/CMSIS_CM4_SIMD.htm | 3809 ++++++++++
.../common/CMSIS/Documentation/CMSIS_Core.htm | 1470 ++++
.../Documentation/CMSIS_DebugSupport.htm | 240 +
.../CMSIS/Documentation/CMSIS_History.htm | 472 ++
.../CMSIS/Documentation/CMSIS_Logo_Final.jpg | Bin 0 -> 123676 bytes
.../CMSIS_System_View_Description.htm | 1157 +++
.../cortexM3_stm32l1/common/CMSIS/core_cm3.h | 1236 ++++
.../common/CMSIS/core_cmFunc.h | 609 ++
.../common/CMSIS/core_cmInstr.h | 585 ++
.../cortexM3_stm32l1/common/CMSIS/stm32l1xx.h | 6348 +++++++++++++++++
.../common/CMSIS/system_stm32l1xx.c | 549 ++
.../common/CMSIS/system_stm32l1xx.h | 101 +
.../cortexM3_stm32l1/common/arch_settings.h | 56 +
.../common/core/interrupts.cpp | 190 +
.../cortexM3_stm32l1/common/core/interrupts.h | 37 +
.../interfaces-impl/arch_registers_impl.h | 9 +
.../common/interfaces-impl/delays.cpp | 77 +
.../common/interfaces-impl/endianness_impl.h | 92 +
.../common/interfaces-impl/gpio_impl.cpp | 61 +
.../common/interfaces-impl/gpio_impl.h | 265 +
.../common/interfaces-impl/portability.cpp | 253 +
.../common/interfaces-impl/portability_impl.h | 141 +
.../board_settings.h | 69 +
.../core/stage_1_boot.cpp | 315 +
.../interfaces-impl/bsp.cpp | 134 +
.../interfaces-impl/bsp_impl.h | 46 +
.../interfaces-impl/console-impl.h | 37 +
.../interfaces-impl/console.cpp | 229 +
.../interfaces-impl/hwmapping.h | 66 +
.../stm32_64k+10k_rom.ld | 166 +
miosix/config/Makefile.inc | 99 +-
.../Package-stm32f207ze_als_camboard.bash | 75 +
.../Package-stm32l151c8_als_mainboard.bash | 75 +
miosix_np_2/nbproject/configurations.xml | 133 +-
.../nbproject/private/configurations.xml | 66 +
miosix_np_2/nbproject/private/private.xml | 2 +-
miosix_np_2/nbproject/project.xml | 8 +
48 files changed, 19541 insertions(+), 12 deletions(-)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/board_settings.h (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/core/stage_1_boot.cpp (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/bsp.cpp (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/bsp_impl.h (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/console-impl.h (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/console.cpp (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/delays.cpp (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/interfaces-impl/hwmapping.h (100%)
rename miosix/arch/cortexM3_stm32f2/{stm32f207ze_camboard => stm32f207ze_als_camboard}/stm32_1m+128k_rom.ld (100%)
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_Core.htm
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_DebugSupport.htm
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_History.htm
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_Logo_Final.jpg
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_System_View_Description.htm
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cm3.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmFunc.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmInstr.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/stm32l1xx.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.c
create mode 100644 miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/arch_settings.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/core/interrupts.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/common/core/interrupts.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/endianness_impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console-impl.h
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console.cpp
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h
create mode 100644 miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld
create mode 100644 miosix_np_2/nbproject/Package-stm32f207ze_als_camboard.bash
create mode 100644 miosix_np_2/nbproject/Package-stm32l151c8_als_mainboard.bash
diff --git a/Makefile b/Makefile
index 277dd02a..6c8092c3 100644
--- a/Makefile
+++ b/Makefile
@@ -14,7 +14,7 @@ SUBDIRS := miosix
## List here your source files (both .s, .c and .cpp)
##
SRC := \
-miosix/testsuite/testsuite.cpp
+main.cpp
##
## List here additional static libraries with relative path
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/board_settings.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/board_settings.h
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/board_settings.h
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/board_settings.h
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/core/stage_1_boot.cpp
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/core/stage_1_boot.cpp
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/core/stage_1_boot.cpp
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/bsp.cpp
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/bsp_impl.h
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/console-impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/console-impl.h
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/console-impl.h
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/console-impl.h
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/console.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/console.cpp
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/console.cpp
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/console.cpp
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/delays.cpp
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/delays.cpp
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/delays.cpp
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/interfaces-impl/hwmapping.h
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/stm32_1m+128k_rom.ld
similarity index 100%
rename from miosix/arch/cortexM3_stm32f2/stm32f207ze_camboard/stm32_1m+128k_rom.ld
rename to miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/stm32_1m+128k_rom.ld
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd b/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
new file mode 100644
index 00000000..17ace6a5
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS-SVD_Schema_1_0.xsd
@@ -0,0 +1,274 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!--
+ @date: 29.07.2011
+ @note Copyright (C) 2011 ARM Limited. All rights reserved.
+ @par
+ ARM Limited (ARM) is supplying this software for use with Cortex-M
+ processor based microcontroller, but can be equally used for other
+ suitable processor architectures. This file can be freely distributed.
+ Modifications to this file shall be clearly marked.
+
+ @par
+ THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ -->
+
+<xs:schema xmlns:xs="http://www.w3.org/2001/XMLSchema" elementFormDefault="qualified" attributeFormDefault="qualified" version="1.0">
+
+ <xs:simpleType name="registerNameType">
+ <xs:restriction base="xs:string">
+ <xs:pattern value="([_A-Za-z]{1}[_A-Za-z0-9]*(\[%s\])?)|([_A-Za-z]{1}[_A-Za-z0-9]*(%s)?[_A-Za-z0-9]*)"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="dimIndexType">
+ <xs:restriction base="xs:string">
+ <xs:pattern value="[0-9]+\-[0-9]+|[A-Z]-[A-Z]|[_0-9a-zA-Z]+(,\s*[_0-9a-zA-Z]+)+"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="scaledNonNegativeInteger">
+ <xs:restriction base="xs:string">
+ <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fA-F]+[kmgtKMGT]?"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="enumeratedValueDataType">
+ <xs:restriction base="xs:string">
+ <xs:pattern value="[+]?(0x|0X|#)?[0-9a-fxA-FX]+"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="accessType">
+ <xs:restriction base="xs:token">
+ <xs:enumeration value="read-only"/>
+ <xs:enumeration value="write-only"/>
+ <xs:enumeration value="read-write"/>
+ <xs:enumeration value="writeOnce"/>
+ <xs:enumeration value="read-writeOnce"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="modifiedWriteValuesType">
+ <xs:restriction base="xs:token">
+ <xs:enumeration value="oneToClear"/>
+ <xs:enumeration value="oneToSet"/>
+ <xs:enumeration value="oneToToggle"/>
+ <xs:enumeration value="zeroToClear"/>
+ <xs:enumeration value="zeroToSet"/>
+ <xs:enumeration value="zeroToToggle"/>
+ <xs:enumeration value="clear"/>
+ <xs:enumeration value="set"/>
+ <xs:enumeration value="modify"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="readActionType">
+ <xs:restriction base="xs:token">
+ <xs:enumeration value="clear"/>
+ <xs:enumeration value="set"/>
+ <xs:enumeration value="modify"/>
+ <xs:enumeration value="modifyExternal"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="enumUsageType">
+ <xs:restriction base="xs:token">
+ <xs:enumeration value="read"/>
+ <xs:enumeration value="write"/>
+ <xs:enumeration value="read-write"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:simpleType name="bitRangeType">
+ <xs:restriction base="xs:token">
+ <xs:pattern value="\[([0-3])?[0-9]:([0-3])?[0-9]\]"/>
+ </xs:restriction>
+ </xs:simpleType>
+
+ <xs:complexType name="writeConstraintType">
+ <xs:choice>
+ <xs:element name="writeAsRead" type="xs:boolean"/>
+ <xs:element name="useEnumeratedValues" type="xs:boolean"/>
+ <xs:element name="range">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="minimum" type="scaledNonNegativeInteger"/>
+ <xs:element name="maximum" type="scaledNonNegativeInteger"/>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:choice>
+ </xs:complexType>
+
+ <xs:complexType name="addressBlockType">
+ <xs:sequence>
+ <xs:element name="offset" type="scaledNonNegativeInteger"/>
+ <xs:element name="size" type="scaledNonNegativeInteger"/>
+ <xs:element name="usage">
+ <xs:simpleType>
+ <xs:restriction base="xs:token">
+ <xs:enumeration value="registers"/>
+ <xs:enumeration value="buffer"/>
+ <xs:enumeration value="reserved"/>
+ </xs:restriction>
+ </xs:simpleType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:complexType name="interruptType">
+ <xs:sequence>
+ <xs:element name="name" type="xs:string"/>
+ <xs:element name="value" type="xs:integer"/>
+ </xs:sequence>
+ </xs:complexType>
+
+ <xs:group name="registerPropertiesGroup">
+ <xs:sequence>
+ <xs:element name="size" type="scaledNonNegativeInteger" minOccurs="0"/>
+ <xs:element name="access" type="accessType" minOccurs="0"/>
+ <xs:element name="resetValue" type="scaledNonNegativeInteger" minOccurs="0"/>
+ <xs:element name="resetMask" type="scaledNonNegativeInteger" minOccurs="0"/>
+ </xs:sequence>
+ </xs:group>
+
+ <xs:group name="bitRangeLsbMsbStyle">
+ <xs:sequence>
+ <xs:element name="lsb" type="scaledNonNegativeInteger"/>
+ <xs:element name="msb" type="scaledNonNegativeInteger"/>
+ </xs:sequence>
+ </xs:group>
+
+ <xs:group name="bitRangeOffsetWidthStyle">
+ <xs:sequence>
+ <xs:element name="bitOffset" type="scaledNonNegativeInteger"/>
+ <xs:element name="bitWidth" type="scaledNonNegativeInteger" minOccurs="0"/>
+ </xs:sequence>
+ </xs:group>
+
+ <xs:group name="dimElementGroup">
+ <xs:sequence>
+ <xs:element name="dim" type="scaledNonNegativeInteger"/>
+ <xs:element name="dimIncrement" type="scaledNonNegativeInteger"/>
+ <xs:element name="dimIndex" type="dimIndexType" minOccurs="0"/>
+ </xs:sequence>
+ </xs:group>
+
+ <xs:element name="device" nillable="true">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="name" type="xs:string"/>
+ <xs:element name="version" type="xs:string"/>
+ <xs:element name="description" type="xs:string"/>
+ <xs:element name="addressUnitBits" type="scaledNonNegativeInteger"/>
+ <xs:element name="width" type="scaledNonNegativeInteger"/>
+ <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+ <xs:element name="peripherals">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="peripheral" minOccurs="1" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="name" type="xs:Name"/>
+ <xs:element name="version" type="xs:string" minOccurs="0"/>
+ <xs:element name="description" type="xs:string" minOccurs="0"/>
+ <xs:element name="groupName" type="xs:string" minOccurs="0"/>
+ <xs:element name="prependToName" type="xs:string" minOccurs="0"/>
+ <xs:element name="appendToName" type="xs:string" minOccurs="0"/>
+ <xs:element name="disableCondition" type="xs:string" minOccurs="0"/>
+ <xs:element name="baseAddress" type="scaledNonNegativeInteger"/>
+ <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+ <xs:element name="addressBlock" type="addressBlockType" minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="interrupt" type="interruptType" minOccurs="0" maxOccurs="unbounded"/>
+ <xs:element name="registers" minOccurs="0" maxOccurs="1">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="register" minOccurs="1" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:group ref="dimElementGroup" minOccurs="0"/>
+ <xs:element name="name" type="registerNameType"/> <!-- was xs:Name -->
+ <xs:element name="displayName" type="xs:string" minOccurs="0"/>
+ <xs:element name="description" type="xs:string" minOccurs="0"/>
+ <xs:element name="alternateGroup" type="xs:Name" minOccurs="0"/>
+ <xs:element name="addressOffset" type="scaledNonNegativeInteger"/>
+ <xs:group ref="registerPropertiesGroup" minOccurs="0"/>
+ <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+ <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+ <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+ <xs:element name="fields" minOccurs="0" maxOccurs="1">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="field" minOccurs="1" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="name" type="xs:string"/>
+ <xs:element name="description" type="xs:string" minOccurs="0"/>
+ <xs:choice>
+ <xs:group ref="bitRangeLsbMsbStyle" minOccurs="0"/>
+ <xs:group ref="bitRangeOffsetWidthStyle" minOccurs="0"/>
+ <xs:element name="bitRange" type="bitRangeType" minOccurs="0"/>
+ </xs:choice>
+ <xs:element name="access" type="accessType" minOccurs="0"/>
+ <xs:element name="modifiedWriteValues" type="modifiedWriteValuesType" minOccurs="0"/>
+ <xs:element name="writeConstraint" type="writeConstraintType" minOccurs="0"/>
+ <xs:element name="readAction" type="readActionType" minOccurs="0"/>
+ <xs:element name="enumeratedValues" minOccurs="0" maxOccurs="2">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="name" type="xs:Name" minOccurs="0"/>
+ <xs:element name="usage" type="enumUsageType" minOccurs="0"/>
+ <xs:element name="enumeratedValue" minOccurs="1" maxOccurs="unbounded">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:element name="name" type="xs:string"/>
+ <xs:element name="description" type="xs:string" minOccurs="0"/>
+ <xs:choice>
+ <xs:element name="value" type="enumeratedValueDataType"/>
+ <xs:element name="isDefault" type="xs:boolean"/>
+ </xs:choice>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ <xs:attribute name="derivedFrom" type="xs:Name" use="optional"/>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ <xs:element name="vendorExtensions" minOccurs="0" maxOccurs="1">
+ <xs:complexType>
+ <xs:sequence>
+ <xs:any namespace="##any" processContents="lax" minOccurs="0" maxOccurs="unbounded">
+ </xs:any>
+ </xs:sequence>
+ </xs:complexType>
+ </xs:element>
+ </xs:sequence>
+ <xs:attribute name="schemaVersion" type="xs:decimal" use="required" fixed="1.0"/>
+ </xs:complexType>
+ </xs:element>
+</xs:schema>
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_CM4_SIMD.htm b/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_CM4_SIMD.htm
new file mode 100644
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@@ -0,0 +1,3809 @@
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+ <title>CMSIS: Cortex-M4 SIMD Instructions</title><meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
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+<body>
+
+<h1>CMSIS Support for Cortex-M4 SIMD Instructions</h1>
+
+<p align="center">This file describes the Cortex-M4 SIMD instructions supported by CMSIS.</p>
+<p align="center">Version: 1.00 - 25. November 2010</p>
+
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
+ Copyright � ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+<h2>Revision History</h2>
+<ul>
+ <li>Revision 0.01 - January 2010: Initial version</li>
+ <li>Revision 0.02 - June 2010: added __QADD, __QSUB</li>
+ <li>Revision 1.00 - November 2010: </li>
+</ul>
+
+<hr>
+
+<h2>Contents</h2>
+
+<ol>
+ <li class="LI2"><a href="#About">About</a></li>
+ <li class="LI2"><a href="#CM4-SIMD-Instructions">Cortex-M4 SIMD instruction support</a></li>
+ <li class="LI2"><a href="#Examples">Examples</a></li>
+</ol>
+
+
+
+<p> </p>
+<h2><a name="About"></a>About</h2>
+<p>
+ CMSIS provides for the Cortex-M4 a set of functions supporting Cortex-M4 SIMD instructions.
+</p>
+
+<p> </p>
+<h2><a name="CM4-SIMD-Instructions"></a>Cortex-M4 SIMD instruction support</h2>
+<p>CMSIS supports the following functions for Cortex-M4 instructions:
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Name</th>
+ <th class="kt">Mnemonic</th>
+ <th class="kt">Description</th>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SADD8">__SADD8</a></b></td>
+ <td class="kt">SADD8</td>
+ <td class="kt">GE setting quad 8-bit signed addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QADD8">__QADD8</a></b></td>
+ <td class="kt">QADD8</td>
+ <td class="kt">Q setting quad 8-bit saturating addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHADD8">__SHADD8</a></b></td>
+ <td class="kt">SHADD8</td>
+ <td class="kt">Quad 8-bit signed addition with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UADD8">__UADD8</a></b></td>
+ <td class="kt">UADD8</td>
+ <td class="kt">GE setting quad 8-bit unsigned addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQADD8">__UQADD8</a></b></td>
+ <td class="kt">UQADD8</td>
+ <td class="kt">Quad 8-bit unsigned saturating addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHADD8">__UHADD8</a></b></td>
+ <td class="kt">UHADD8</td>
+ <td class="kt">Quad 8-bit unsigned addition with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SSUB8">__SSUB8</a></b></td>
+ <td class="kt">SSUB8</td>
+ <td class="kt">GE setting quad 8-bit signed subtraction</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QSUB8">__QSUB8</a></b></td>
+ <td class="kt">QSUB8</td>
+ <td class="kt">Q setting quad 8-bit saturating subtract</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHSUB8">__SHSUB8</a></b></td>
+ <td class="kt">SHSUB8</td>
+ <td class="kt">Quad 8-bit signed subtraction with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USUB8">__USUB8</a></b></td>
+ <td class="kt">USUB8</td>
+ <td class="kt">GE setting quad 8-bit unsigned subtract</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQSUB8">__UQSUB8</a></b></td>
+ <td class="kt">UQSUB8</td>
+ <td class="kt">Quad 8-bit unsigned saturating subtraction</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHSUB8">__UHSUB8</a></b></td>
+ <td class="kt">UHSUB8</td>
+ <td class="kt">Quad 8-bit unsigned subtraction with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SADD16">__SADD16</a></b></td>
+ <td class="kt">SADD16</td>
+ <td class="kt">GE setting dual 16-bit signed addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QADD16">__QADD16</a></b></td>
+ <td class="kt">QADD16</td>
+ <td class="kt">Q setting dual 16-bit saturating addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHADD16">__SHADD16</a></b></td>
+ <td class="kt">SHADD16</td>
+ <td class="kt">Dual 16-bit signed addition with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UADD16">__UADD16</a></b></td>
+ <td class="kt">UADD16</td>
+ <td class="kt">GE setting dual 16-bit unsigned addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQADD16">__UQADD16</a></b></td>
+ <td class="kt">UQADD16</td>
+ <td class="kt">Dual 16-bit unsigned saturating addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHADD16">__UHADD16</a></b></td>
+ <td class="kt">UHADD16</td>
+ <td class="kt">Dual 16-bit unsigned addition with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SSUB16">__SSUB16</a></b></td>
+ <td class="kt">SSUB16</td>
+ <td class="kt">GE setting dual 16-bit signed subtraction</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QSUB16">__QSUB16</a></b></td>
+ <td class="kt">QSUB16</td>
+ <td class="kt">Q setting dual 16-bit saturating subtract</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHSUB16">__SHSUB16</a></b></td>
+ <td class="kt">SHSUB16</td>
+ <td class="kt">Dual 16-bit signed subtraction with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USUB16">__USUB16</a></b></td>
+ <td class="kt">USUB16</td>
+ <td class="kt">GE setting dual 16-bit unsigned subtract</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQSUB16">__UQSUB16</a></b></td>
+ <td class="kt">UQSUB16</td>
+ <td class="kt">Dual 16-bit unsigned saturating subtraction</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHSUB16">__UHSUB16</a></b></td>
+ <td class="kt">UHSUB16</td>
+ <td class="kt">Dual 16-bit unsigned subtraction with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SASX">__SASX</a></b></td>
+ <td class="kt">SASX</td>
+ <td class="kt">GE setting dual 16-bit addition and subtraction with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QASX">__QASX</a></b></td>
+ <td class="kt">QASX</td>
+ <td class="kt">Q setting dual 16-bit add and subtract with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHASX">__SHASX</a></b></td>
+ <td class="kt">SHASX</td>
+ <td class="kt">Dual 16-bit signed addition and subtraction with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UASX">__UASX</a></b></td>
+ <td class="kt">UASX</td>
+ <td class="kt">GE setting dual 16-bit unsigned addition and subtraction with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQASX">__UQASX</a></b></td>
+ <td class="kt">UQASX</td>
+ <td class="kt">Dual 16-bit unsigned saturating addition and subtraction with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHASX">__UHASX</a></b></td>
+ <td class="kt">UHASX</td>
+ <td class="kt">Dual 16-bit unsigned addition and subtraction with halved results and exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SSAX">__SSAX</a></b></td>
+ <td class="kt">SSAX</td>
+ <td class="kt">GE setting dual 16-bit signed subtraction and addition with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QSAX">__QSAX</a></b></td>
+ <td class="kt">QSAX</td>
+ <td class="kt">Q setting dual 16-bit subtract and add with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SHSAX">__SHSAX</a></b></td>
+ <td class="kt">SHSAX</td>
+ <td class="kt">Dual 16-bit signed subtraction and addition with halved results</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USAX">__USAX</a></b></td>
+ <td class="kt">USAX</td>
+ <td class="kt">GE setting dual 16-bit unsigned subtract and add with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UQSAX">__UQSAX</a></b></td>
+ <td class="kt">UQSAX</td>
+ <td class="kt">Dual 16-bit unsigned saturating subtraction and addition with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UHSAX">__UHSAX</a></b></td>
+ <td class="kt">UHSAX</td>
+ <td class="kt">Dual 16-bit unsigned subtraction and addition with halved results and exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USAD8">__USAD8</a></b></td>
+ <td class="kt">USAD8</td>
+ <td class="kt">Unsigned sum of quad 8-bit unsigned absolute difference</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USADA8">__USADA8</a></b></td>
+ <td class="kt">USADA8</td>
+ <td class="kt">Unsigned sum of quad 8-bit unsigned absolute difference with 32-bit accumulate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SSAT16">__SSAT16</a></b></td>
+ <td class="kt">SSAT16</td>
+ <td class="kt">Q setting dual 16-bit saturate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__USAT16">__USAT16</a></b></td>
+ <td class="kt">USAT16</td>
+ <td class="kt">Q setting dual 16-bit unsigned saturate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UXTB16">__UXTB16</a></b></td>
+ <td class="kt">UXTB16</td>
+ <td class="kt">Dual extract 8-bits and zero-extend to 16-bits</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__UXTAB16">__UXTAB16</a></b></td>
+ <td class="kt">UXTAB16</td>
+ <td class="kt">Extracted 16-bit to 32-bit unsigned addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SXTB16">__SXTB16</a></b></td>
+ <td class="kt">SXTB16</td>
+ <td class="kt">Dual extract 8-bits and sign extend each to 16-bits</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SXTAB16">__SXTAB16</a></b></td>
+ <td class="kt">SXTAB16</td>
+ <td class="kt">Dual extracted 8-bit to 16-bit signed addition</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMUAD">__SMUAD</a></b></td>
+ <td class="kt">SMUAD</td>
+ <td class="kt">Q setting sum of dual 16-bit signed multiply</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMUADX">__SMUADX</a></b></td>
+ <td class="kt">SMUADX</td>
+ <td class="kt">Q setting sum of dual 16-bit signed multiply with exchange</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLAD">__SMLAD</a></b></td>
+ <td class="kt">SMLAD</td>
+ <td class="kt">Q setting dual 16-bit signed multiply with single 32-bit accumulator</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLADX">__SMLADX</a></b></td>
+ <td class="kt">SMLADX</td>
+ <td class="kt">Q setting pre-exchanged dual 16-bit signed multiply with single 32-bit accumulator</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLALD">__SMLALD</a></b></td>
+ <td class="kt">SMLALD</td>
+ <td class="kt">Dual 16-bit signed multiply with single 64-bit accumulator</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLALDX">__SMLALDX</a></b></td>
+ <td class="kt">SMLALDX</td>
+ <td class="kt">Dual 16-bit signed multiply with exchange with single 64-bit accumulator</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMUSD">__SMUSD</a></b></td>
+ <td class="kt">SMUSD</td>
+ <td class="kt">Dual 16-bit signed multiply returning difference</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMUSDX">__SMUSDX</a></b></td>
+ <td class="kt">SMUSDX</td>
+ <td class="kt">Dual 16-bit signed multiply with exchange returning difference</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLSD">__SMLSD</a></b></td>
+ <td class="kt">SMLSD</td>
+ <td class="kt">Q setting dual 16-bit signed multiply subtract with 32-bit accumulate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLSDX">__SMLSDX</a></b></td>
+ <td class="kt">SMLSDX</td>
+ <td class="kt">Q setting dual 16-bit signed multiply with exchange subtract with 32-bit accumulate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLSLD">__SMLSLD</a></b></td>
+ <td class="kt">SMLSLD</td>
+ <td class="kt">Q setting dual 16-bit signed multiply subtract with 64-bit accumulate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SMLSLDX">__SMLSLDX</a></b></td>
+ <td class="kt">SMLSLDX</td>
+ <td class="kt">Q setting dual 16-bit signed multiply with exchange subtract with 64-bit accumulate</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__SEL">__SEL</a></b></td>
+ <td class="kt">SEL</td>
+ <td class="kt">Select bytes based on GE bits</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QADD">__QADD</a></b></td>
+ <td class="kt">QADD</td>
+ <td class="kt">Q setting saturating add</td>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#__QSUB">__QSUB</a></b></td>
+ <td class="kt">QSUB/td>
+ <td class="kt">Q setting saturating subtract</td>
+ </tr>
+
+ </tbody>
+</table>
+
+<!-- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -->
+<!-- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -->
+
+<h3><a name="__SADD8"></a>Function __SADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four 8-bit signed integer additions.<br>
+ The GE bits in the APSR are set according to the results of the additions.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands.</li>
+ <li><b>val2</b>: second four 8-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the first bytes from each operand, in the first byte of the return value.</li>
+ <li>the addition of the second bytes of each operand, in the second byte of the return value.</li>
+ <li>the addition of the third bytes of each operand, in the third byte of the return value.</li>
+ <li>the addition of the fourth bytes of each operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0</li>
+ <li>if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0</li>
+ <li>if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0</li>
+ <li>if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] + val2[7:0]
+res[15:8] = val1[15:8] + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QADD8"></a>Function __QADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four 8-bit integer additions, saturating the results to
+ the 8-bit signed integer range -2<sup>7</sup> ≤ x ≤ 2<sup>7</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands.</li>
+ <li><b>val2</b>: second four 8-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the saturated addition of the first byte of each operand in the first byte of the return value.</li>
+ <li>the saturated addition of the second byte of each operand in the second byte of the return value.</li>
+ <li>the saturated addition of the third byte of each operand in the third byte of the return value.</li>
+ <li>the saturated addition of the fourth byte of each operand in the fourth byte of the return value.</li>
+ </ul>
+ <p>The returned results are saturated to the 16-bit signed integer range -2<sup>7</sup> ≤ x ≤ 2<sup>7</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] + val2[7:0]
+res[15:8] = val1[15:8] + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHADD8"></a>Function __SHADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four signed 8-bit integer additions, halving the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands.</li>
+ <li><b>val2</b>: second four 8-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the first bytes from each operand, in the first byte of the return value.</li>
+ <li>the halved addition of the second bytes from each operand, in the second byte of the return value.</li>
+ <li>the halved addition fo the third bytes from each operand, in the third byte of the return value.</li>
+ <li>the halved addition of the fourth bytes from each operand, in the fourth byte of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = (val1[7:0] + val2[7:0]) >> 1
+res[15:8] = (val1[15:8] + val2[15:8]) >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UADD8"></a>Function __UADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit integer additions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands for each addition.</li>
+ <li><b>val2</b>: second four 8-bit summands for each addition.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the first bytes in each operand, in the first byte of the return value.</li>
+ <li>the addition of the second bytes in each operand, in the second byte of the return value.</li>
+ <li>the addition of the third bytes in each operand, in the third byte of the return value.</li>
+ <li>the addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[7:0] ≥ 0x100 then APSR.GE[0] = 1 else 0</li>
+ <li>if res[15:8] ≥ 0x100 then APSR.GE[1] = 1 else 0</li>
+ <li>if res[23:16] ≥ 0x100 then APSR.GE[2] = 1 else 0</li>
+ <li>if res[31:24] ≥ 0x100 then APSR.GE[3] = 1 else 0</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] + val2[7:0]
+res[15:8] = val1[15:8] + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQADD8"></a>Function __UQADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit integer additions, saturating the
+ results to the 8-bit unsigned integer range 0 ≤ x ≤ 2<sup>8</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands.</li>
+ <li><b>val2</b>: second four 8-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the first bytes in each operand, in the first byte of the return value.</li>
+ <li>the addition of the second bytes in each operand, in the second byte of the return value.</li>
+ <li>the addition of the third bytes in each operand, in the third byte of the return value.</li>
+ <li>the addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 2<sup>8</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] + val2[7:0]
+res[15:8] = val1[15:8] + val2[15:8]
+res[23:16] = val1[23:16] + val2[23:16]
+res[31:24] = val1[31:24] + val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHADD8"></a>Function __UHADD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit integer additions, halving the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit summands.</li>
+ <li><b>val2</b>: second four 8-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the first bytes in each operand, in the first byte of the return value.</li>
+ <li>the halved addition of the second bytes in each operand, in the second byte of the return value.</li>
+ <li>the halved addition of the third bytes in each operand, in the third byte of the return value.</li>
+ <li>the halved addition of the fourth bytes in each operand, in the fourth byte of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = (val1[7:0] + val2[7:0]) >> 1
+res[15:8] = (val1[15:8] + val2[15:8]) >> 1
+res[23:16] = (val1[23:16] + val2[23:16]) >> 1
+res[31:24] = (val1[31:24] + val2[31:24]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SSUB8"></a>Function __SSUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SSUB8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four 8-bit signed integer subtractions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands of each subtraction.</li>
+ <li><b>val2</b>: second four 8-bit operands of each subtraction.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand, in the first bytes of the return value.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand, in the second byte of the return value.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand, in the third byte of the return value.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation. If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[8:0] ≥ 0 then APSR.GE[0] = 1 else 0</li>
+ <li>if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0</li>
+ <li>if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0</li>
+ <li>if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] - val2[7:0]
+res[15:8] = val1[15:8] - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QSUB8"></a>Function __QSUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QADD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four 8-bit integer subtractions, saturating the results
+ to the 8-bit signed integer range -2<sup>7</sup> ≤ x ≤ 2<sup>7</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands.</li>
+ <li><b>val2</b>: second four 8-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand, in the first byte of the return value.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand, in the second byte of the return value.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand, in the third byte of the return value.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>The returned results are saturated to the 8-bit signed integer range -2<sup>7</sup> ≤ x ≤ 2<sup>7</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] - val2[7:0]
+res[15:8] = val1[15:8] - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHSUB8"></a>Function __SHSUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHSUB8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four signed 8-bit integer subtractions, halving the
+ results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands.</li>
+ <li><b>val2</b>: second four 8-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the first byte in the second operand from the first byte
+ in the first operand, in the first byte of the return value.</li>
+ <li>the halved subtraction of the second byte in the second operand from the second
+ byte in the first operand, in the second byte of the return value.</li>
+ <li>the halved subtraction of the third byte in the second operand from the third byte
+ in the first operand, in the third byte of the return value.</li>
+ <li>the halved subtraction of the fourth byte in the second operand from the fourth
+ byte in the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = (val1[7:0] - val2[7:0]) >> 1
+res[15:8] = (val1[15:8] - val2[15:8]) >> 1
+res[23:16] = (val1[23:16] - val2[23:16] >> 1
+res[31:24] = (val1[31:24] - val2[31:24] >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USUB8"></a>Function __USUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USUB8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function It enables you to perform four 8-bit unsigned integer subtractions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands.</li>
+ <li><b>val2</b>: second four 8-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand, in the first byte of the return value.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand, in the second byte of the return value.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand, in the third byte of the return value.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[7:0] ≥ 0 then APSR.GE[0] = 1 else 0</li>
+ <li>if res[15:8] ≥ 0 then APSR.GE[1] = 1 else 0</li>
+ <li>if res[23:16] ≥ 0 then APSR.GE[2] = 1 else 0</li>
+ <li>if res[31:24] ≥ 0 then APSR.GE[3] = 1 else 0</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] - val2[7:0]
+res[15:8] = val1[15:8] - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQSUB8"></a>Function __UQSUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQSUB8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit integer subtractions, saturating
+ the results to the 8-bit unsigned integer range 0 ≤ x ≤ 2<sup>8</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands.</li>
+ <li><b>val2</b>: second four 8-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand, in the first byte of the return value.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand, in the second byte of the return value.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand, in the third byte of the return value.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 8-bit unsigned integer range 0 ≤ x ≤ 2<sup>8</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = val1[7:0] - val2[7:0]
+res[15:8] = val1[15:8] - val2[15:8]
+res[23:16] = val1[23:16] - val2[23:16]
+res[31:24] = val1[31:24] - val2[31:24]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHSUB8"></a>Function __UHSUB8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHSUB8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit integer subtractions, halving the
+ results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands.</li>
+ <li><b>val2</b>: second four 8-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the first byte in the second operand from the first byte
+ in the first operand, in the first byte of the return value.</li>
+ <li>the halved subtraction of the second byte in the second operand from the second
+ byte in the first operand, in the second byte of the return value.</li>
+ <li>the halved subtraction of the third byte in the second operand from the third byte
+ in the first operand, in the third byte of the return value.</li>
+ <li>the halved subtraction of the fourth byte in the second operand from the fourth
+ byte in the first operand, in the fourth byte of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[7:0] = (val1[7:0] - val2[7:0]) >> 1
+res[15:8] = (val1[15:8] - val2[15:8]) >> 1
+res[23:16] = (val1[23:16] - val2[23:16]) >> 1
+res[31:24] = (val1[31:24] - val2[31:24]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SADD16"></a>Function __SADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed integer additions.<br>
+ The GE bits in the APSR are set according to the results of the additions.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands.</li>
+ <li><b>val2</b>: second two 16-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfwords in the low halfword of the return value.</li>
+ <li>the addition of the high halfwords in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QADD16"></a>Function __QADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit integer arithmetic additions in parallel,
+ saturating the results to the 16-bit signed integer range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands.</li>
+ <li><b>val2</b>: second two 16-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the saturated addition of the low halfwords in the low halfword of the return value.</li>
+ <li>the saturated addition of the high halfwords in the high halfword of the return value.</li>
+ </ul>
+ <p>The returned results are saturated to the 16-bit signed integer
+ range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[15:0]
+res[16:31] = val1[31:16] + val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHADD16"></a>Function __SHADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two signed 16-bit integer additions, halving the
+ results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands.</li>
+ <li><b>val2</b>: second two 16-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the low halfwords from each operand, in the low halfword
+ of the return value.</li>
+ <li>the halved addition of the high halfwords from each operand, in the high halfword
+ of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] + val2[15:0]) >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UADD16"></a>Function __UADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit unsigned integer additions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands for each addition.</li>
+ <li><b>val2</b>: second two 16-bit summands for each addition.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfwords in each operand, in the low halfword of the
+ return value.</li>
+ <li>the addition of the high halfwords in each operand, in the high halfword of the
+ return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0x10000 then APSR.GE[0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0x10000 then APSR.GE[1] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQADD16"></a>Function __UQADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two unsigned 16-bit integer additions, saturating the
+ results to the 16-bit unsigned integer range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands.</li>
+ <li><b>val2</b>: second two 16-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfword in the first operand and the low halfword in the
+ second operand, in the low halfword of the return value.</li>
+ <li>the addition of the high halfword in the first operand and the high halfword in the
+ second operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 16-bit unsigned integer
+ range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[15:0]
+res[31:16] = val1[31:16] + val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHADD16"></a>Function __UHADD16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHADD16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two unsigned 16-bit integer additions, halving the
+ results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit summands.</li>
+ <li><b>val2</b>: second two 16-bit summands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the low halfwords in each operand, in the low halfword of
+ the return value.</li>
+ <li>the halved addition of the high halfwords in each operand, in the high halfword
+ of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] + val2[15:0]) >> 1
+res[31:16] = (val1[31:16] + val2[31:16]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SSUB16"></a>Function __SSUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SSUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed integer subtractions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands of each subtraction.</li>
+ <li><b>val2</b>: second two 16-bit operands of each subtraction.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the low halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the high halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QSUB16"></a>Function __QSUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QSUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit integer subtractions, saturating the
+ results to the 16-bit signed integer range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands.</li>
+ <li><b>val2</b>: second two 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the saturated subtraction of the low halfword in the second operand from the low
+ halfword in the first operand, in the low halfword of the returned result.</li>
+ <li>the saturated subtraction of the high halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the returned result.</li>
+ </ul>
+ <p>The returned results are saturated to the 16-bit signed integer
+ range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHSUB16"></a>Function __SHSUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHSUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two signed 16-bit integer subtractions, halving the
+ results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands.</li>
+ <li><b>val2</b>: second two 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the low halfword in the second operand from the low
+ halfword in the first operand, in the low halfword of the return value.</li>
+ <li>the halved subtraction of the high halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] - val2[15:0]) >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USUB16"></a>Function __USUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit unsigned integer subtractions.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands.</li>
+ <li><b>val2</b>: second two 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the low halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the high halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQSUB16"></a>Function __UQSUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQSUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two unsigned 16-bit integer subtractions, saturating
+ the results to the 16-bit unsigned integer range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands for each subtraction.</li>
+ <li><b>val2</b>: second two 16-bit operands for each subtraction.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the low halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the high halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 16-bit unsigned integer range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[15:0]
+res[31:16] = val1[31:16] - val2[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHSUB16"></a>Function __UHSUB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHSUB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two unsigned 16-bit integer subtractions, halving
+ the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands.</li>
+ <li><b>val2</b>: second two 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the low halfword in the second operand from the low
+ halfword in the first operand, in the low halfword of the return value.</li>
+ <li>the halved subtraction of the high halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] - val2[15:0]) >> 1
+res[31:16] = (val1[31:16] - val2[31:16]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SASX"></a>Function __SASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function inserts an SASX instruction into the instruction stream generated by the
+ compiler. It enables you to exchange the halfwords of the second operand, add the high
+ halfwords and subtract the low halfwords.<br>
+ The GE bits in the APRS are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
+ first operand for the addition in the high halfword.</li>
+ <li><b>val2</b>: second operand for the subtraction in the high halfword, and the
+ second operand for the addition in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the high halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the addition of the high halfword in the first operand and the low halfword in the
+ second operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QASX"></a>Function __QASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the one operand, then add the high
+ halfwords and subtract the low halfwords, saturating the results to the 16-bit signed
+ integer range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
+ first operand for the addition in the high halfword.</li>
+ <li><b>val2</b>: second operand for the subtraction in the high halfword, and the
+ second operand for the addition in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the saturated subtraction of the high halfword in the second operand from the low
+ halfword in the first operand, in the low halfword of the return value.</li>
+ <li>the saturated addition of the high halfword in the first operand and the low
+ halfword in the second operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The returned results are saturated to the 16-bit signed integer
+ range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHASX"></a>Function __SHASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the two halfwords of one operand, perform one
+ signed 16-bit integer addition and one signed 16-bit subtraction, and halve the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands.</li>
+ <li><b>val2</b>: second 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the high halfword in the second operand from the low
+ halfword in the first operand, in the low halfword of the return value.</li>
+ <li>the halved subtraction of the low halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UASX"></a>Function __UASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the two halfwords of the second operand, add the
+ high halfwords and subtract the low halfwords.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
+ first operand for the addition in the high halfword.</li>
+ <li><b>val2</b>: second operand for the subtraction in the high halfword and the
+ second operand for the addition in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the high halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the addition of the high halfword in the first operand and the low halfword in the
+ second operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0x10000 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQASX"></a>Function __UQASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand and perform
+ one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturating the
+ results to the 16-bit unsigned integer range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first two 16-bit operands.</li>
+ <li><b>val2</b>: second two 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the high halfword in the second operand from the low halfword
+ in the first operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the low halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 16-bit unsigned integer
+ range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] - val2[31:16]
+res[31:16] = val1[31:16] + val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHASX"></a>Function __UHASX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHASX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand, add the high
+ halfwords and subtract the low halfwords, halving the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the subtraction in the low halfword, and the
+ first operand for the addition in the high halfword.</li>
+ <li><b>val2</b>: second operand for the subtraction in the high halfword, and the
+ second operand for the addition in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved subtraction of the high halfword in the second operand from the low
+ halfword in the first operand.</li>
+ <li>the halved addition of the high halfword in the first operand and the low halfword
+ in the second operand.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] - val2[31:16]) >> 1
+res[31:16] = (val1[31:16] + val2[15:0]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SSAX"></a>Function __SSAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SSAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the two halfwords of one operand and perform one
+ 16-bit integer subtraction and one 16-bit addition.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the addition in the low halfword, and the first
+ operand for the subtraction in the high halfword.</li>
+ <li><b>val2</b>: second operand for the addition in the high halfword, and the
+ second operand for the subtraction in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfword in the first operand and the high halfword in the
+ second operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the low halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__QSAX"></a>Function __QSAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QSAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of one operand, then subtract the
+ high halfwords and add the low halfwords, saturating the results to the 16-bit signed
+ integer range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the addition in the low halfword, and the first
+ operand for the subtraction in the high halfword.</li>
+ <li><b>val2</b>: second operand for the addition in the high halfword, and the
+ second operand for the subtraction in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the saturated addition of the low halfword of the first operand and the high
+ halfword of the second operand, in the low halfword of the return value.</li>
+ <li>the saturated subtraction of the low halfword of the second operand from the high
+ halfword of the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The returned results are saturated to the 16-bit signed integer
+ range -2<sup>15</sup> ≤ x ≤ 2<sup>15</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SHSAX"></a>Function __SHSAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SHSAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the two halfwords of one operand, perform one
+ signed 16-bit integer subtraction and one signed 16-bit addition, and halve the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands.</li>
+ <li><b>val2</b>: second 16-bit operands.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the low halfword in the first operand and the high halfword
+ in the second operand, in the low halfword of the return value.</li>
+ <li>the halved subtraction of the low halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USAX"></a>Function __USAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand, subtract the
+ high halfwords and add the low halfwords.<br>
+ The GE bits in the APSR are set according to the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the addition in the low halfword, and the first
+ operand for the subtraction in the high halfword.</li>
+ <li><b>val2</b>: second operand for the addition in the high halfword, and the
+ second operand for the subtraction in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfword in the first operand and the high halfword in the
+ second operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the low halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>Each bit in APSR.GE is set or cleared for each byte in the return value, depending on
+ the results of the operation.<br>
+ If <i>res</i> is the return value, then:
+ </p>
+ <ul style="margin-top:0px">
+ <li>if res[15:0] ≥ 0x10000 then APSR.GE[1:0] = 11 else 00</li>
+ <li>if res[31:16] ≥ 0 then APSR.GE[3:2] = 11 else 00</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UQSAX"></a>Function __UQSAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UQSAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand and perform
+ one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturating the
+ results to the 16-bit unsigned integer range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operand for the addition in the low halfword, and the
+ first 16-bit operand for the subtraction in the high halfword.</li>
+ <li><b>val2</b>: second 16-bit halfword for the addition in the high halfword,
+ and the second 16-bit halfword for the subtraction in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the addition of the low halfword in the first operand and the high halfword in the
+ second operand, in the low halfword of the return value.</li>
+ <li>the subtraction of the low halfword in the second operand from the high halfword
+ in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ <p>The results are saturated to the 16-bit unsigned integer
+ range 0 ≤ x ≤ 2<sup>16</sup> - 1.
+ </p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + val2[31:16]
+res[31:16] = val1[31:16] - val2[15:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UHSAX"></a>Function __UHSAX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UHSAX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand, subtract the
+ high halfwords and add the low halfwords, halving the results.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first operand for the addition in the low halfword, and the first
+ operand for the subtraction in the high halfword.</li>
+ <li><b>val2</b>: second operand for the addition in the high halfword, and the
+ second operand for the subtraction in the low halfword.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the halved addition of the high halfword in the second operand and the low
+ halfword in the first operand, in the low halfword of the return value.</li>
+ <li>the halved subtraction of the low halfword in the second operand from the high
+ halfword in the first operand, in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = (val1[15:0] + val2[31:16]) >> 1
+res[31:16] = (val1[31:16] - val2[15:0]) >> 1</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USAD8"></a>Function __USAD8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USAD8(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit subtractions, and add the
+ absolute values of the differences together, returning the result as a single unsigned
+ integer.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands for the subtractions.</li>
+ <li><b>val2</b>: second four 8-bit operands for the subtractions.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the sum of the absolute differences of:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand.</li>
+ </ul>
+ <p>The sum is returned as a single unsigned integer.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+absdiff1 = val1[7:0] - val2[7:0]
+absdiff2 = val1[15:8] - val2[15:8]
+absdiff3 = val1[23:16] - val2[23:16]
+absdiff4 = val1[31:24] - val2[31:24]
+res[31:0] = absdiff1 + absdiff2 + absdiff3 + absdiff4</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USADA8"></a>Function __USADA8</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USADA8(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform four unsigned 8-bit subtractions, and add the
+ absolute values of the differences to a 32-bit accumulate operand.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first four 8-bit operands for the subtractions.</li>
+ <li><b>val2</b>: second four 8-bit operands for the subtractions.</li>
+ <li><b>val3</b>: accumulation value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the sum of the absolute differences of the following
+ bytes, added to the accumulation value:</p>
+ <ul style="margin-top:0px">
+ <li>the subtraction of the first byte in the second operand from the first byte in the
+ first operand.</li>
+ <li>the subtraction of the second byte in the second operand from the second byte in
+ the first operand.</li>
+ <li>the subtraction of the third byte in the second operand from the third byte in the
+ first operand.</li>
+ <li>the subtraction of the fourth byte in the second operand from the fourth byte in
+ the first operand.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+absdiff1 = val1[7:0] - val2[7:0]
+absdiff2 = val1[15:8] - val2[15:8]
+absdiff3 = val1[23:16] - val2[23:16]
+absdiff4 = val1[31:24] - val2[31:24]
+sum = absdiff1 + absdiff2 + absdiff3 + absdiff4
+res[31:0] = sum[31:0] + val3[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SSAT16"></a>Function __SSAT16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SSAT16(uint32_t val1, const uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to saturate two signed 16-bit values to a selected signed range.<br>
+ The Q bit is set if either operation saturates.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: two signed 16-bit values to be saturated.</li>
+ <li><b>val2</b>: bit position for saturation, an integral constant expression in the
+ range 1 to 16.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns:</p>
+ <ul style="margin-top:0px">
+ <li>the signed saturation of the low halfword in <i>val1</i>, saturated to the bit position
+ specified in <i>val2</i> and returned in the low halfword of the return value.</li>
+ <li>the signed saturation of the high halfword in <i>val1</i>, saturated to the bit position
+ specified in <i>val2</i> and returned in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+Saturate halfwords in val1 to the signed range specified by the bit position in val2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__USAT16"></a>Function __USAT16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __USAT16(uint32_t val1, const uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to saturate two signed 16-bit values to a selected unsigned
+ range.<br>
+ The Q bit is set if either operation saturates.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: two 16-bit values that are to be saturated.</li>
+ <li><b>val2</b>: bit position for saturation, and must be an integral constant
+ expression in the range 0 to 15.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the saturation of the two signed 16-bit values, as non-negative values.</p>
+ <ul style="margin-top:0px">
+ <li>the saturation of the low halfword in <i>val1</i>, saturated to the bit position
+ specified in <i>val2</i> and returned in the low halfword of the return value.</li>
+ <li>the saturation of the high halfword in <i>val1</i>, saturated to the bit position
+ specified in <i>val2</i> and returned in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+Saturate halfwords in val1 to the unsigned range specified by the bit position in val2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UXTB16"></a>Function __UXTB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UXTB16(uint32_t val);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to extract two 8-bit values from an operand and zero-extend
+ them to 16 bits each.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the 8-bit values zero-extended to 16-bit values.</p>
+ <ul style="margin-top:0px">
+ <li>zero-extended value of val[7:0] in the low halfword of the return value.</li>
+ <li>zero-extended value of val[23:16] in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = ZeroExtended(val[7:0] )
+res[31:16] = ZeroExtended(val[23:16])</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__UXTAB16"></a>Function __UXTAB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __UXTAB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to extract two 8-bit values from one operand, zero-extend them
+ to 16 bits each, and add the results to two 16-bit values from another operand.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: value added to the zero-extended to 16-bit values.</li>
+ <li><b>val2</b>: two 8-bit values to be extracted and zero-extended.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the 8-bit values in <i>val2</i>, zero-extended to 16-bit values
+ and added to <i>val1</i>.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = ZeroExt(val2[7:0] to 16 bits) + val1[15:0]
+res[31:16] = ZeroExt(val2[31:16] to 16 bits) + val1[31:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SXTB16"></a>Function __SXTB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SXTB16(uint32_t val);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to extract two 8-bit values from an operand and sign-extend
+ them to 16 bits each.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: two 8-bit values in val[7:0] and val[23:16] to be sign-extended.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the 8-bit values sign-extended to 16-bit values.</p>
+ <ul style="margin-top:0px">
+ <li>sign-extended value of val[7:0] in the low halfword of the return value.</li>
+ <li>sign-extended value of val[23:16] in the high halfword of the return value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = SignExtended(val[7:0]
+res[31:16] = SignExtended(val[23:16]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SXTAB16"></a>Function __SXTAB16</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SXTAB16(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to extract two 8-bit values from the second operand (at bit
+ positions [7:0] and [23:16]), sign-extend them to 16-bits each, and add the results to the
+ first operand.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: values added to the zero-extended to 16-bit values.</li>
+ <li><b>val2</b>: two 8-bit values to be extracted and zero-extended.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the addition of <i>val1</i> and <i>val2</i>, where the 8-bit values in
+ val2[7:0] and val2[23:16] have been extracted and sign-extended prior to the addition.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[15:0] = val1[15:0] + SignExtended(val2[7:0])
+res[31:16] = val1[31:16] + SignExtended(val2[23:16])</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMUAD"></a>Function __SMUAD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMUAD(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function It enables you to perform two 16-bit signed multiplications, adding the
+ products together.<br>
+ The Q bit is set if the addition overflows.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the sum of the products of the two 16-bit signed multiplications.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMUADX"></a>Function __SMUADX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMUADX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed multiplications with exchanged
+ halfwords of the second operand, adding the products together.<br>
+ The Q bit is set if the addition overflows.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the sum of the products of the two 16-bit signed multiplications with exchanged
+ halfwords of the second operand.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLAD"></a>Function __SMLAD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMLAD(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two signed 16-bit multiplications, adding both
+ results to a 32-bit accumulate operand.<br>
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the product of each multiplication added to the accumulate
+ value, as a 32-bit integer.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 + p2 + val3[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLADX"></a>Function __SMLADX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMLADX(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two signed 16-bit multiplications with exchanged
+ halfwords of the second operand, adding both results to a 32-bit accumulate operand.<br>
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the product of each multiplication with exchanged
+ halfwords of the second operand added to the accumulate value, as a 32-bit integer.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 + p2 + val3[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLALD"></a>Function __SMLALD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint64_t __SMLALD(uint32_t val1, uint32_t val2, uint64_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two signed 16-bit multiplications, adding both
+ results to a 64-bit accumulate operand. Overflow is only possible as a result of the 64-bit
+ addition. This overflow is not detected if it occurs. Instead, the result wraps around
+ modulo2<sup>64</sup>.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the product of each multiplication added to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0] = sum[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLALDX"></a>Function __SMLALDX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+unsigned long long __SMLALDX(uint32_t val1, uint32_t val2, unsigned long long val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand, and perform
+ two signed 16-bit multiplications, adding both results to a 64-bit accumulate operand.
+ Overflow is only possible as a result of the 64-bit addition. This overflow is not detected
+ if it occurs. Instead, the result wraps around modulo2<sup>64</sup>.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the product of each multiplication added to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+sum = p1 + p2 + val3[63:32][31:0]
+res[63:32] = sum[63:32]
+res[31:0] = sum[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMUSD"></a>Function __SMUSD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMUSD(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed multiplications, taking the
+ difference of the products by subtracting the high halfword product from the low
+ halfword product.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the products of the two 16-bit signed multiplications.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMUSDX"></a>Function __SMUSDX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMUSDX(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed multiplications, subtracting one
+ of the products from the other. The halfwords of the second operand are exchanged
+ before performing the arithmetic. This produces top * bottom and bottom * top
+ multiplication.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the products of the two 16-bit signed multiplications.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLSD"></a>Function __SMLSD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMLSD(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to perform two 16-bit signed multiplications, take the
+ difference of the products, subtracting the high halfword product from the low halfword
+ product, and add the difference to a 32-bit accumulate operand.<br>
+ The Q bit is set if the accumulation overflows. Overflow cannot occur during the multiplications or the
+ subtraction.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val3</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the product of each multiplication, added
+ to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[31:0] = p1 - p2 + val3[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLSDX"></a>Function __SMLSDX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SMLSDX(uint32_t val1, uint32_t val2, uint32_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords in the second operand, then perform
+ two 16-bit signed multiplications. The difference of the products is added to a 32-bit
+ accumulate operand.<br>
+ The Q bit is set if the addition overflows. Overflow cannot occur during the multiplications or the subtraction.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val3</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the product of each multiplication, added
+ to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[31:0] = p1 - p2 + val3[31:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLSLD"></a>Function __SMLSLD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint64_t __SMLSLD(uint32_t val1, uint32_t val2, uint64_t val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function It enables you to perform two 16-bit signed multiplications, take the
+ difference of the products, subtracting the high halfword product from the low halfword
+ product, and add the difference to a 64-bit accumulate operand. Overflow cannot occur
+ during the multiplications or the subtraction. Overflow can occur as a result of the 64-bit
+ addition, and this overflow is not detected. Instead, the result wraps round to
+ modulo2<sup>64</sup>.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val3</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the product of each multiplication,
+ added to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[15:0]
+p2 = val1[31:16] * val2[31:16]
+res[63:0] = p1 - p2 + val3[63:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="__SMLSLDX"></a>Function __SMLSLDX</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+unsigned long long __SMLSLDX(uint32_t val1, uint32_t val2, unsigned long long val3);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to exchange the halfwords of the second operand, perform two
+ 16-bit multiplications, adding the difference of the products to a 64-bit accumulate
+ operand. Overflow cannot occur during the multiplications or the subtraction. Overflow
+ can occur as a result of the 64-bit addition, and this overflow is not detected. Instead,
+ the result wraps round to modulo2<sup>64</sup>.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first 16-bit operands for each multiplication.</li>
+ <li><b>val2</b>: second 16-bit operands for each multiplication.</li>
+ <li><b>val3</b>: accumulate value.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the difference of the product of each multiplication,
+ added to the accumulate value.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+p1 = val1[15:0] * val2[31:16]
+p2 = val1[31:16] * val2[15:0]
+res[63:0] = p1 - p2 + val3[63:0]</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+
+<h3><a name="__SEL"></a>Function __SEL</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __SEL(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function inserts a SEL instruction into the instruction stream generated by the
+ compiler. It enables you to select bytes from the input parameters, whereby the bytes
+ that are selected depend upon the results of previous SIMD instruction function. The
+ results of previous SIMD instruction function are represented by the Greater than or
+ Equal flags in the Application Program Status Register (APSR).
+ The __SEL function works equally well on both halfword and byte operand function
+ results. This is because halfword operand operations set two (duplicate) GE bits per
+ value.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: four selectable 8-bit values.</li>
+ <li><b>val2</b>: four selectable 8-bit values.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function selects bytes from the input parameters and returns them in the
+ return value, res, according to the following criteria:</p>
+ <ul style="margin-top:0px">
+ <li>if APSR.GE[0] == 1 then res[7:0] = val1[7:0] else res[7:0] = val2[7:0]</li>
+ <li>if APSR.GE[1] == 1 then res[15:8] = val1[15:8] else res[15:8] = val2[15:8]</li>
+ <li>if APSR.GE[2] == 1 then res[23:16] = val1[23:16] else res[23:16] = val2[23:16]</li>
+ <li>if APSR.GE[3] == 1 then res[31;24] = val1[31:24] else res = val2[31:24]</li>
+ </ul>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<h3><a name="__QADD"></a>Function __QADD</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QADD(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to obtain the saturating add of two integers.<br>
+ The Q bit is set if the operation saturates.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: first summand of the saturating add operation.</li>
+ <li><b>val2</b>: second summand of the saturating add operation.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the saturating addition of val1 and val2.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[31:0] = SAT(val1 + SAT(val2 * 2))</pre>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<h3><a name="__QSUB"></a>Function __QSUB</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Summary</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t __QSUB(uint32_t val1, uint32_t val2);</pre>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Description</b></td>
+ <td>This function enables you to obtain the saturating subtraction of two integers.<br>
+ The Q bit is set if the operation saturates.
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Parameter</b></td>
+ <td>
+ <ul style="list-style-type:none; margin-left:0px; margin-top:0px">
+ <li><b>val1</b>: minuend of the saturating subtraction operation.</li>
+ <li><b>val2</b>: subtrahend of the saturating subtraction operation.</li>
+ </ul>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Return Value</b></td>
+ <td>
+ <p>The function returns the saturating subtraction of val1 and val2.</p>
+ </td>
+ </tr>
+
+ <tr>
+ <td><b>Operation</b></td>
+ <td>
+ <pre style="margin-left:0px">
+res[31:0] = SAT(val1 - SAT(val2 * 2))</pre>
+ </td>
+ </tr>
+
+ </tbody>
+</table>
+
+<!-- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -->
+<!-- -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- -->
+<p> </p>
+<h2><a name="Examples"></a>Examples</h2>
+<p>Following are some coding examples using the SIMD functions:
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Name</th>
+ <th class="kt">Description</th>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#Addition">Addition</a></b></td>
+ <td class="kt">Add two values using SIMD function</td>
+ </tr>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#Addition">Subtraction</a></b></td>
+ <td class="kt">Subtract two values using SIMD function</td>
+ </tr>
+ </tr>
+
+ <tr>
+ <td class="kt"><b><a href="#Multiplication">Multiplication</a></b></td>
+ <td class="kt">Performing a multiplication using SIMD function</td>
+ </tr>
+ </tr>
+
+ </tbody>
+</table>
+
+
+<h3><a name="Addition"></a>Addition</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Example</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t add_halfwords(uint32_t val1, uint32_t val2)
+{
+ uint32_t res;
+ res = __SADD16(val1, val2);
+ return res;
+}</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="Subtraction"></a>Subtraction</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Example</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t sub_halfwords(uint32_t val1, uint32_t val2)
+{
+ uint32_t res;
+ res = __SSUB16(val1, val2);
+ return res;
+}</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><a name="Multiplication"></a>Multiplication</h3>
+<table border="0" cellpadding="5" cellspacing="5">
+ <tbody>
+ <tr>
+ <td><b>Example</b></td>
+ <td>
+ <pre style="margin-left:0px">
+uint32_t dual_mul_add_products(uint32_t val1, uint32_t val2)
+{
+ uint32_t res;
+ res = __SMUAD(val1, val2);
+ return res;
+}</pre>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+
+</body>
+</html>
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+<body>
+<h1>Cortex Microcontroller Software Interface Standard</h1>
+
+<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
+<p align="center">Version: 2.10 - July 2011</p>
+
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
+ Copyright � ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
+<ul>
+ <li>Version 1.00: initial release. </li>
+ <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
+ <li>Version 1.02: added Cortex-M0. </li>
+ <li>Version 1.10: second review. </li>
+ <li>Version 1.20: third review. </li>
+ <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
+ <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
+ <li>Version 1.30: updated Device Support Packages.</li>
+ <li>Version 2.00: added Cortex-M4 support.</li>
+ <li>Version 2.01: internal review.</li>
+ <li>Version 2.02: updated Device Specific Defines</li>
+ <li>Version 2.10: reworked core include files</li>
+</ul>
+
+<hr>
+
+<h2>Contents</h2>
+
+<ol>
+ <li class="LI2"><a href="#1">About</a></li>
+ <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
+ <li class="LI2"><a href="#3">CMSIS Files</a></li>
+ <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
+ <li class="LI2"><a href="#5">CMSIS Example</a></li>
+ <li class="LI2"><a href="#6">CMSIS MISRA-C:2004 Compliance Exceptions</a></li>
+</ol>
+
+<h2><a name="1"></a>About</h2>
+
+<p>
+ The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
+ that are faced when software components are deployed to physical microcontroller devices based on a
+ Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
+ processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
+ with various silicon and software vendors and provides a common approach to interface to peripherals,
+ real-time operating systems, and middleware components.
+</p>
+
+<p>ARM provides as part of the CMSIS the following software layers that are
+available for various compiler implementations:</p>
+<ul>
+ <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
+ address definitions and helper functions to
+ access core registers and peripherals. It defines also a device
+ independent interface for RTOS Kernels that includes debug channel
+ definitions.</li>
+</ul>
+
+<p>These software layers are expanded by Silicon partners with:</p>
+<ul>
+ <li><strong>Device Peripheral Access Layer</strong>: provides definitions
+ for all device peripherals</li>
+ <li><strong>Access Functions for Peripherals (optional)</strong>: provides
+ additional helper functions for peripherals</li>
+</ul>
+
+<p>CMSIS defines for a Cortex-M Microcontroller System:</p>
+<ul>
+ <li style="text-align: left;">A common way to access peripheral registers
+ and a common way to define exception vectors.</li>
+ <li style="text-align: left;">The register names of the <strong>Core
+ Peripherals</strong> and<strong> </strong>the names of the <strong>Core
+ Exception Vectors</strong>.</li>
+ <li>An device independent interface for RTOS Kernels including a debug
+ channel.</li>
+</ul>
+
+<p>
+ By using CMSIS compliant software components, the user can easier re-use template code.
+ CMSIS is intended to enable the combination of software components from multiple middleware vendors.
+</p>
+
+<h2><a name="2"></a>Coding Rules and Conventions</h2>
+
+<p>
+ The following section describes the coding rules and conventions used in the CMSIS
+ implementation. It contains also information about data types and version number information.
+</p>
+
+<h3>Essentials</h3>
+<ul>
+ <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
+ there are disable and enable sequences for PC-LINT inserted.</li>
+ <li>ANSI standard data types defined in the ANSI C header file
+ <strong><stdint.h></strong> are used.</li>
+ <li>#define constants that include expressions must be enclosed by
+ parenthesis.</li>
+ <li>Variables and parameters have a complete data type.</li>
+ <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
+ re-entrant.</li>
+ <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
+ (which means that wait/query loops are done at other software layers).</li>
+ <li>For each exception/interrupt there is definition for:
+ <ul>
+ <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
+ (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
+ <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
+ <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
+ </ul></li>
+</ul>
+
+<h3>Recommendations</h3>
+
+<p>The CMSIS recommends the following conventions for identifiers.</p>
+<ul>
+ <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
+ <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
+ <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
+ <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
+</ul>
+
+<b>Comments</b>
+
+<ul>
+ <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
+ (<em>// comment</em>). It is assumed that the programming tools support today
+ consistently the C++ comment style.</li>
+ <li><strong>Function Comments</strong> provide for each function the following information:
+ <ul>
+ <li>one-line brief function overview.</li>
+ <li>detailed parameter explanation.</li>
+ <li>detailed information about return values.</li>
+ <li>detailed description of the actual function.</li>
+ </ul>
+ <p><b>Doxygen Example:</b></p>
+ <pre>
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ * @param IRQn interrupt number that specifies the interrupt
+ * @return none.
+ * Enable the specified interrupt in the NVIC Interrupt Controller.
+ * Other settings of the interrupt such as priority are not affected.
+ */</pre>
+ </li>
+</ul>
+
+<h3>Data Types and IO Type Qualifiers</h3>
+
+<p>
+ The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
+ <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
+ to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
+ debug information of peripheral registers.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
+ <th class="kt">#define</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__I</td>
+ <td class="kt">volatile const</td>
+ <td class="kt">Read access only</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__O</td>
+ <td class="kt">volatile</td>
+ <td class="kt">Write access only</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__IO</td>
+ <td class="kt">volatile</td>
+ <td class="kt">Read and write access</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3>CMSIS Version Number</h3>
+<p>
+ File <strong>core_cm4.h</strong> contains the version number of the CMSIS with the following define:
+</p>
+
+<pre>
+#define __CM4_CMSIS_VERSION_MAIN (0x02) /* [31:16] main version */
+#define __CM4_CMSIS_VERSION_SUB (0x10) /* [15:0] sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB)</pre>
+
+<p>
+ File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
+</p>
+
+<pre>
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /* [31:16] main version */
+#define __CM3_CMSIS_VERSION_SUB (0x10) /* [15:0] sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre>
+
+<p>
+ File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
+</p>
+
+<pre>
+#define __CM0_CMSIS_VERSION_MAIN (0x02) /* [31:16] main version */
+#define __CM0_CMSIS_VERSION_SUB (0x10) /* [15:0] sub version */
+#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre>
+
+
+<h3>CMSIS Cortex Core</h3>
+<p>
+ File <strong>core_cm4.h</strong> contains the type of the CMSIS Cortex-M with the following define:
+</p>
+
+<pre>
+#define __CORTEX_M (0x04)</pre>
+
+<p>
+ File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
+</p>
+
+<pre>
+#define __CORTEX_M (0x03)</pre>
+
+<p>
+ File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
+</p>
+
+<pre>
+#define __CORTEX_M (0x00)</pre>
+
+
+<h2><a name="3"></a>CMSIS Files</h2>
+<p>
+ This section describes the Files provided in context with the CMSIS to access the Cortex-M
+ hardware and peripherals.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">File</th>
+ <th class="kt">Provider</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap"><i>device.h</i></td>
+ <td class="kt">Device specific (provided by silicon partner)</td>
+ <td class="kt">Defines the peripherals for the actual device. The file may use
+ several other include files to define the peripherals of the actual device.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cm0.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cm3.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cm4.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the core peripherals for the Cortex-M4 CPU and core peripherals.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cm4_simd.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the Cortex-M4 Core SIMD functions.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cmFunc.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the Cortex-M Core Register access functions.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">core_cmInstr.h</td>
+ <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
+ <td class="kt">Defines the Cortex-M Core instructions.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
+ <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
+ <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">system<i>_device</i></td>
+ <td class="kt">ARM (adapted by silicon partner)</td>
+ <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
+ typically the oscillator (PLL) that is part of the microcontroller device</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3><em>device.h</em></h3>
+
+<p>
+ The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
+ <u><strong>central include file</strong></u> that the application programmer is using in
+ the C source code. This file contains:
+</p>
+<ul>
+ <li>
+ <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
+ (IRQn) for all core and device specific exceptions and interrupts.</p>
+ </li>
+ <li>
+ <p><strong>Configuration for core_cm0.h / core_cm3.h / core_cm4.h</strong>: reflects the
+ actual configuration of the Cortex-M processor that is part of the actual
+ device. As such the file <strong>core_cm0.h / core_cm3.h / core_cm4.h</strong> is included that
+ implements access to processor registers and core peripherals. </p>
+ </li>
+ <li>
+ <p><strong>Device Peripheral Access Layer</strong>: provides definitions
+ for all device peripherals. It contains all data structures and the address
+ mapping for the device specific peripherals. </p>
+ </li>
+ <li><strong>Access Functions for Peripherals (optional)</strong>: provides
+ additional helper functions for peripherals that are useful for programming
+ of these peripherals. Access Functions may be provided as inline functions
+ or can be extern references to a device specific library provided by the
+ silicon vendor.</li>
+</ul>
+
+
+<h4>Interrupt Number Definition</h4>
+
+<p>To access the device specific interrupts the device.h file defines IRQn
+numbers for the complete device using a enum typedef as shown below:</p>
+<pre>
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers ****************************************************************/
+ WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ :
+ :
+ } IRQn_Type;</pre>
+
+
+<h4>Device Specific Defines</h4>
+<p>
+ The following device implementation specific defines are set in the device header file and are
+ used for the Cortex-M core configuration options. Some configuration options are reflected
+ in the CMSIS layer using the #define settings described below.
+</p>
+<p>
+ Several features in <strong>core_cm#.h</strong> are configured by the following defines
+ that must be defined before <strong>#include <core_cm#.h></strong>
+ preprocessor command.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">#define</th>
+ <th class="kt" nowrap="nowrap">Core</th>
+ <th class="kt" nowrap="nowrap">Value</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__CM0_REV</td>
+ <td class="kt" nowrap="nowrap">M0</td>
+ <td class="kt" nowrap="nowrap">0x0000</td>
+ <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__CM3_REV</td>
+ <td class="kt" nowrap="nowrap">M3</td>
+ <td class="kt" nowrap="nowrap">0x0101 | 0x0200</td>
+ <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__CM4_REV</td>
+ <td class="kt" nowrap="nowrap">M4</td>
+ <td class="kt" nowrap="nowrap">0x0000</td>
+ <td class="kt">Core revision number ([15:8] revision number, [7:0] patch number)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">2 .. 8</td>
+ <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">0 | 1</td>
+ <td class="kt">Defines if a MPU is present or not</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__FPU_PRESENT</td>
+ <td class="kt" nowrap="nowrap">M4</td>
+ <td class="kt" nowrap="nowrap">0 | 1</td>
+ <td class="kt">Defines if a FPU is present or not</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">0 | 1</td>
+ <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
+ in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
+ file must contain a vendor specific implementation of this function.</td>
+ </tr>
+ </tbody>
+</table>
+
+
+<h4>Device Peripheral Access Layer</h4>
+<p>
+ Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong>
+ and <strong><peripheral name>_</strong> to identify peripheral registers that access this
+ specific peripheral. The intention of this is to avoid name collisions caused
+ due to short names. If more than one peripheral of the same type exists,
+ identifiers have a postfix (digit or letter). For example:
+</p>
+<ul>
+ <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
+ <pre>
+typedef struct
+{
+ union {
+ __I uint8_t RBR; /*!< Offset: 0x000 (R/ ) Receiver Buffer Register */
+ __O uint8_t THR; /*!< Offset: 0x000 ( /W) Transmit Holding Register */
+ __IO uint8_t DLL; /*!< Offset: 0x000 (R/W) Divisor Latch LSB */
+ uint32_t RESERVED0;
+ };
+ union {
+ __IO uint8_t DLM; /*!< Offset: 0x004 (R/W) Divisor Latch MSB */
+ __IO uint32_t IER; /*!< Offset: 0x004 (R/W) Interrupt Enable Register */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 (R/ ) Interrupt ID Register */
+ __O uint8_t FCR; /*!< Offset: 0x008 ( /W) FIFO Control Register */
+ };
+ __IO uint8_t LCR; /*!< Offset: 0x00C (R/W) Line Control Register */
+ uint8_t RESERVED1[7];
+ __I uint8_t LSR; /*!< Offset: 0x014 (R/ ) Line Status Register */
+ uint8_t RESERVED2[7];
+ __IO uint8_t SCR; /*!< Offset: 0x01C (R/W) Scratch Pad Register */
+ uint8_t RESERVED3[3];
+ __IO uint32_t ACR; /*!< Offset: 0x020 (R/W) Autobaud Control Register */
+ __IO uint8_t ICR; /*!< Offset: 0x024 (R/W) IrDA Control Register */
+ uint8_t RESERVED4[3];
+ __IO uint8_t FDR; /*!< Offset: 0x028 (R/W) Fractional Divider Register */
+ uint8_t RESERVED5[7];
+ __IO uint8_t TER; /*!< Offset: 0x030 (R/W) Transmit Enable Register */
+ uint8_t RESERVED6[39];
+ __I uint8_t FIFOLVL; /*!< Offset: 0x058 (R/ ) FIFO Level Register */
+} LPC_UART_TypeDef;</pre>
+ </li>
+ <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
+ For example UART1->THR is the transmit holding register of UART1.
+ <pre>
+#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
+#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre>
+ </li>
+</ul>
+
+<h5>Minimal Requiements</h5>
+<p>
+ To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
+ and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
+</p>
+<ul>
+ <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
+ Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
+ the peripheral registers. For example:
+ <pre>
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;</pre>
+ </li>
+
+ <li>
+ <strong>Base Address</strong> for each peripheral (in case of multiple peripherals
+ that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
+ <pre>
+#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
+ </li>
+
+ <li>
+ <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
+ the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0,
+ LPC_UART2). For Example:
+ <pre>
+#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
+ </li>
+</ul>
+
+<p>
+ These definitions allow to access the peripheral registers from user code with simple assignments like:
+</p>
+<pre>SysTick->CTRL = 0;</pre>
+
+<h5>Optional Features</h5>
+<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
+<ul>
+ <li>
+ #define constants that simplify access to the peripheral registers.
+ These constant define bit-positions or other specific patterns are that required for the
+ programming of the peripheral registers. The identifiers used start with
+ <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
+ It is recommended to use CAPITAL letters for such #define constants.
+ </li>
+ <li>
+ Functions that perform more complex functions with the peripheral (i.e. status query before
+ a sending register is accessed). Again these function start with
+ <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
+ </li>
+</ul>
+
+<h3>core_cm0.h</h3>
+<p>
+ File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
+ the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
+ and core peripherals with efficient functions (defined as <strong>static inline</strong>).
+</p>
+<p>This file implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
+<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm0.h in generic
+ library projects that are device independent. Only core relevant types and defines are used.</p>
+
+<h3>core_cm3.h</h3>
+<p>
+ File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
+ the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
+ and core peripherals with efficient functions (defined as <strong>static inline</strong>).
+</p>
+<p>This file implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
+<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm3.h in generic
+ library projects that are device independent. Only core relevant types and defines are used.</p>
+
+<h3>core_cm4.h, core_cm4_simd.h</h3>
+<p>
+ File <b>core_cm4.h</b> describes the data structures for the Cortex-M4 core peripherals and does
+ the address mapping of this structures. It also provides basic access to the Cortex-M4 core registers
+ and core peripherals with efficient functions (defined as <strong>static inline</strong>).
+</p>
+<p>
+ File <b>core_cm4_simd.h</b> defines Cortex-M4 SIMD instructions.
+</p>
+<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M4.</p>
+<p>The define <em> <strong>__CMSIS_GENERIC</strong></em> allows to use core_cm4.h in generic
+ library projects that are device independent. Only core relevant types and defines are used.</p>
+
+<h3>core_cmFunc.h and core_cmInstr.h</h3>
+<p>
+ File <b>core_cmFunc.h</b> defines the Cortex-M Core Register access functions (defined as <strong>static inline</strong>).
+</p>
+<p>
+ File <b>core_cmInstr.h</b> defines the Cortex-M Core instructions (defined as <strong>static inline</strong>).
+</p>
+<p>These files are part of the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M.</p>
+
+<h3>startup_<em>device</em></h3>
+<p>
+ A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
+ compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
+ interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
+ to an dummy handler. Therefore the interrupt handler can be directly used in application software
+ without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
+</p>
+<p>
+ The following exception names are fixed and define the start of the vector table for a Cortex-M0:
+</p>
+<pre>
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler</pre>
+
+<p>
+ The following exception names are fixed and define the start of the vector table for a Cortex-M3:
+</p>
+<pre>
+__Vectors DCD __initial_sp ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler</pre>
+
+<p>
+ In the following examples for device specific interrupts are shown:
+</p>
+<pre>
+; External Interrupts
+ DCD WWDG_IRQHandler ; Window Watchdog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detect
+ DCD TAMPER_IRQHandler ; Tamper</pre>
+
+<p>
+ Device specific interrupts must have a dummy function that can be overwritten in user code.
+ Below is an example for this dummy function.
+</p>
+<pre>
+Default_Handler PROC
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_IRQHandler [WEAK]
+ EXPORT TAMPER_IRQHandler [WEAK]
+ :
+ :
+ WWDG_IRQHandler
+ PVD_IRQHandler
+ TAMPER_IRQHandler
+ :
+ :
+ B .
+ ENDP</pre>
+
+<p>
+ The user application may simply define an interrupt handler function by using the handler name
+ as shown below.
+</p>
+<pre>
+void WWDG_IRQHandler(void)
+{
+ :
+ :
+}</pre>
+
+
+<h3><a name="4"></a>system_<em>device</em>.c</h3>
+<p>
+ A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
+ the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
+ this file must provide a device specific system configuration function and a global variable
+ that contains the system frequency. It configures the device and initializes typically the
+ oscillator (PLL) that is part of the microcontroller device.
+</p>
+<p>
+ The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
+ as a minimum requirement the SystemInit function as shown below.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Function Definition</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
+ <td class="kt">Setup the microcontroller system. Typically this function configures the
+ oscillator (PLL) that is part of the microcontroller device. For systems
+ with variable clock speed it also updates the variable SystemCoreClock.<br>
+ SystemInit is called from startup<i>_device</i> file.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
+ <td class="kt">Updates the variable SystemCoreClock and must be called whenever the
+ core clock is changed during program execution. SystemCoreClockUpdate()
+ evaluates the clock register settings and calculates the current core clock.
+</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>
+ Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
+ is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Variable Definition</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
+ <td class="kt">Contains the system core clock (which is the system clock frequency supplied
+ to the SysTick timer and the processor core clock). This variable can be
+ used by the user application to setup the SysTick timer or configure other
+ parameters. It may also be used by debugger to query the frequency of the
+ debug timer or configure the trace clock speed.<br>
+ SystemCoreClock is initialized with a correct predefined value.<br><br>
+ The compiler must be configured to avoid the removal of this variable in
+ case that the application program is not using it. It is important for
+ debug systems that the variable is physically present in memory so that
+ it can be examined to configure the debugger.</td>
+ </tr>
+ </tbody>
+</table>
+
+<p class="Note">Note</p>
+<ul>
+ <li><p>The above definitions are the minimum requirements for the file <strong>
+ system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
+ file may export more functions or variables that provide a more flexible
+ configuration of the microcontroller system.</p>
+ </li>
+</ul>
+
+
+<h2>Core Peripheral Access Layer</h2>
+
+<h3>Cortex-M Core Register Access</h3>
+<p>
+ The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
+ and provide access to Cortex-M core registers.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Function Definition</th>
+ <th class="kt">Core</th>
+ <th class="kt">Core Register</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">PRIMASK = 0</td>
+ <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE i</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">PRIMASK = 1</td>
+ <td class="kt">Global Interrupt disable (using the instruction <strong>CPSID i</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return CONTROL</td>
+ <td class="kt">Return Control Register Value (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">CONTROL = value</td>
+ <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_IPSR (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return IPSR</td>
+ <td class="kt">Return IPSR Register Value (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_APSR (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return APSR</td>
+ <td class="kt">Return APSR Register Value (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_xPSR (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return xPSR</td>
+ <td class="kt">Return xPSR Register Value (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return PSP</td>
+ <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
+ <td class="kt" nowrap="nowrap">>M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">PSP = TopOfProcStack</td>
+ <td class="kt">Set Process Stack Pointer value (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return MSP</td>
+ <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">MSP = TopOfMainStack</td>
+ <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">return PRIMASK</td>
+ <td class="kt">Return Priority Mask Register (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">PRIMASK = value</td>
+ <td class="kt">Assign value to Priority Mask Register (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">FAULTMASK = 0</td>
+ <td class="kt">Global Fault exception and Interrupt enable (using the instruction <strong>CPSIE f</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">FAULTMASK = 1</td>
+ <td class="kt">Global Fault exception and Interrupt disable (using the instruction <strong>CPSID f</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_BASEPRI (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">return BASEPRI</td>
+ <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">BASEPRI = value</td>
+ <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">return FAULTMASK</td>
+ <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">FAULTMASK = value</td>
+ <td class="kt">Assign value to Fault Mask Register (using the instruction <strong>MSR</strong>)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __get_FPSCR (void)</td>
+ <td class="kt" nowrap="nowrap">M4</td>
+ <td class="kt" nowrap="nowrap">return FPSCR</td>
+ <td class="kt">Return Floating Point Status / Control Register</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __set_FPSCR (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M4</td>
+ <td class="kt" nowrap="nowrap">FPSCR = value</td>
+ <td class="kt">Assign value to Floating Point Status / Control Register</td>
+ </tr>
+ </tbody>
+</table>
+
+<h3>Cortex-M Instruction Access</h3>
+<p>
+ The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
+ generate specific Cortex-M instructions. The functions are implemented in the file
+ <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt">Name</th>
+ <th class="kt">Core</th>
+ <th class="kt">Generated CPU Instruction</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __NOP (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">NOP</td>
+ <td class="kt">No Operation</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __WFI (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">WFI</td>
+ <td class="kt">Wait for Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __WFE (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">WFE</td>
+ <td class="kt">Wait for Event</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __SEV (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">SEV</td>
+ <td class="kt">Set Event</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __ISB (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">ISB</td>
+ <td class="kt">Instruction Synchronization Barrier</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __DSB (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">DSB</td>
+ <td class="kt">Data Synchronization Barrier</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __DMB (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">DMB</td>
+ <td class="kt">Data Memory Barrier</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">REV</td>
+ <td class="kt">Reverse byte order in integer value.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">REV16</td>
+ <td class="kt">Reverse byte order in unsigned short value. </td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">REVSH</td>
+ <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">RBIT</td>
+ <td class="kt">Reverse bit order of value</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">LDREXB</td>
+ <td class="kt">Load exclusive byte</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">LDREXH</td>
+ <td class="kt">Load exclusive half-word</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">LDREXW</td>
+ <td class="kt">Load exclusive word</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint8_t __STREXB (uint8_t value, uint8_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">STREXB</td>
+ <td class="kt">Store exclusive byte</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint16_t __STREXH (uint16_t value, uint16_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">STREXH</td>
+ <td class="kt">Store exclusive half-word</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t __STREXW (uint32_t value, uint32_t *addr)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">STREXW</td>
+ <td class="kt">Store exclusive word</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">CLREX</td>
+ <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __SSAT (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">SSAT</td>
+ <td class="kt">saturate a signed value</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void __USAT (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">USAT</td>
+ <td class="kt">saturate an unsigned value</td>
+ </tr>
+ </tbody>
+</table>
+
+
+<h3>NVIC Access Functions</h3>
+<p>
+ The CMSIS provides access to the NVIC via the register interface structure and several helper
+ functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
+ identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
+ IRQn values are used for processor core exceptions.
+</p>
+<p>
+ For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
+ the following enum names.
+</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
+ <th class="kt">Core</th>
+ <th class="kt">IRQn</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">-14</td>
+ <td class="kt">Cortex-M Non Maskable Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">-13</td>
+ <td class="kt">Cortex-M Hard Fault Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">-12</td>
+ <td class="kt">Cortex-M Memory Management Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">-11</td>
+ <td class="kt">Cortex-M Bus Fault Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">-10</td>
+ <td class="kt">Cortex-M Usage Fault Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">-5</td>
+ <td class="kt">Cortex-M SV Call Interrupt </td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">-4</td>
+ <td class="kt">Cortex-M Debug Monitor Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">-2</td>
+ <td class="kt">Cortex-M Pend SV Interrupt</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">-1</td>
+ <td class="kt">Cortex-M System Tick Interrupt</td>
+ </tr>
+ </tbody>
+</table>
+
+<p>The following functions simplify the setup of the NVIC.
+The functions are defined as <strong>static inline</strong>.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">Name</th>
+ <th class="kt">Core</th>
+ <th class="kt">Parameter</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">Priority Grouping Value</td>
+ <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">(void)</td>
+ <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Enable IRQn</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Disable IRQn</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Return 1 if IRQn is pending else 0</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Set IRQn Pending</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Clear IRQn Pending Status</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Return 1 if IRQn is active else 0</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_SetPriority (<br>
+ IRQn_Type IRQn,<br>
+ uint32_t priority)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number, Priority</td>
+ <td class="kt">Set Priority for IRQn<br>
+ (not threadsafe for Cortex-M0)</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number</td>
+ <td class="kt">Get Priority for IRQn</td>
+ </tr>
+ <tr>
+<!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
+ <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (<br>
+ uint32_t PriorityGroup,<br>
+ uint32_t PreemptPriority,<br>
+ uint32_t SubPriority)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap">IRQ Number,<br>
+ Priority Group,<br>
+ Preemptive Priority,<br>
+ Sub Priority</td>
+ <td class="kt">Encode priority for given group, preemptive and sub priority</td>
+ </tr>
+<!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
+ <td class="kt" nowrap="nowrap">void NVIC_DecodePriority (<br>
+ uint32_t Priority,<br>
+ uint32_t PriorityGroup,<br>
+ uint32_t* pPreemptPriority,<br>
+ uint32_t* pSubPriority)</td>
+ <td class="kt" nowrap="nowrap">M3, M4</td>
+ <td class="kt" nowrap="nowrap"><br>
+ Priority,<br>
+ Priority Group,<br>
+ pointer to Preempt. Priority,<br>
+ pointer to Sub Priority</td>
+ <td class="kt">Decode given priority to group, preemptive and sub priority</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
+ <td class="kt" nowrap="nowrap">M0, M3, M4</td>
+ <td class="kt" nowrap="nowrap">(void)</td>
+ <td class="kt">Resets the System</td>
+ </tr>
+ </tbody>
+</table>
+<p class="Note">Note</p>
+<ul>
+ <li><p>The processor exceptions have negative enum values. Device specific interrupts
+ have positive enum values and start with 0. The values are defined in
+ <b><em>device.h</em></b> file.
+ </p>
+ </li>
+ <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
+ used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
+ depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
+ </p>
+ </li>
+</ul>
+
+
+<h3>SysTick Configuration Function</h3>
+
+<p>The following function is used to configure the SysTick timer and start the
+SysTick interrupt.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">Name</th>
+ <th class="kt">Parameter</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig (uint32_t ticks)</span></td>
+ <td class="kt">ticks is SysTick counter reload value</td>
+ <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
+ call the SysTick timer creates interrupts with the specified time interval.<br><br>
+ Return: 0 when successful, 1 on failure.<br>
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+
+<h3>Cortex-M3 / Cortex-M4 ITM Debug Access</h3>
+
+<p>The Cortex-M3 / Cortex-M4 incorporates the Instrumented Trace Macrocell (ITM) that
+provides together with the Serial Viewer Output trace capabilities for the
+microcontroller system. The ITM has 32 communication channels; two ITM
+communication channels are used by CMSIS to output the following information:</p>
+<ul>
+ <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function
+ which can be used for printf-style output via the debug interface.</li>
+ <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
+ kernel awareness debugging.</li>
+</ul>
+<p class="Note">Note</p>
+<ul>
+ <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
+ may use the Privileged level for program execution. ITM
+ channels have 4 groups with 8 channels each, whereby each group can be
+ configured for access rights in the Unprivileged level. The ITM channel 0
+ may be therefore enabled for the user task whereas ITM channel 31 may be
+ accessible only in Privileged level from the RTOS kernel itself.</p>
+ </li>
+</ul>
+
+<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the
+table below.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">Name</th>
+ <th class="kt">Parameter</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
+ <td class="kt">character to output</td>
+ <td class="kt">The function outputs a character via the ITM channel 0. The
+ function returns when no debugger is connected that has booked the
+ output. It is blocking when a debugger is connected, but the
+ previous character send is not transmitted.<br><br>
+ Return: the input character 'chr'.
+ </td>
+ </tr>
+ </tbody>
+</table>
+
+<p>
+ Example for the usage of the ITM Channel 31 for RTOS Kernels:
+</p>
+<pre>
+ // check if debugger connected and ITM channel enabled for tracing
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 31))) {
+ // transmit trace data
+ while (ITM->PORT31_U32 == 0);
+ ITM->PORT[31].u8 = task_id; // id of next task
+ while (ITM->PORT[31].u32 == 0);
+ ITM->PORT[31].u32 = task_status; // status information
+ }</pre>
+
+
+<h3>Cortex-M3 additional Debug Access</h3>
+
+<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
+Data can be transmitted via a certain global buffer variable towards the target system.</p>
+
+<p>The buffer variable and the prototypes of the additional functions are shown in the
+table below.</p>
+
+<table class="kt" border="0" cellpadding="0" cellspacing="0">
+ <tbody>
+ <tr>
+ <th class="kt" nowrap="nowrap">Name</th>
+ <th class="kt">Parameter</th>
+ <th class="kt">Description</th>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
+ <td class="kt"> </td>
+ <td class="kt">Buffer to transmit data towards debug system. <br><br>
+ Value 0x5AA55AA5 indicates that buffer is empty.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
+ <td class="kt">none</td>
+ <td class="kt">The nonblocking functions returns the character stored in
+ ITM_RxBuffer. <br><br>
+ Return: -1 indicates that no character was received.</td>
+ </tr>
+ <tr>
+ <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
+ <td class="kt">none</td>
+ <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
+ Return: 1 indicates that a character is available, 0 indicates that
+ no character is available.</td>
+ </tr>
+ </tbody>
+</table>
+
+
+<h2><a name="5"></a>CMSIS Example</h2>
+<p>
+ The following section shows a typical example for using the CMSIS layer in user applications.
+ The example is based on a STM32F10x Device.
+</p>
+<pre>
+#include "stm32f10x.h"
+
+volatile uint32_t msTicks; /* timeTicks counter */
+
+void SysTick_Handler(void) {
+ msTicks++; /* increment timeTicks counter */
+}
+
+__INLINE static void Delay (uint32_t dlyTicks) {
+ uint32_t curTicks = msTicks;
+
+ while ((msTicks - curTicks) < dlyTicks);
+}
+
+__INLINE static void LED_Config(void) {
+ ; /* Configure the LEDs */
+}
+
+__INLINE static void LED_On (uint32_t led) {
+ ; /* Turn On LED */
+}
+
+__INLINE static void LED_Off (uint32_t led) {
+ ; /* Turn Off LED */
+}
+
+int main (void) {
+ if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
+ ; /* Handle Error */
+ while (1);
+ }
+
+ LED_Config(); /* configure the LEDs */
+
+ while(1) {
+ LED_On (0x100); /* Turn on the LED */
+ Delay (100); /* delay 100 Msec */
+ LED_Off (0x100); /* Turn off the LED */
+ Delay (100); /* delay 100 Msec */
+ }
+}</pre>
+
+
+<h2><a name="6"></a>CMSIS MISRA-C:2004 Compliance Exceptions</h2>
+<p>
+ CMSIS violates following MISRA-C2004 Rules:
+</p>
+<ul>
+ <li>Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.</li>
+
+ <li>Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.</li>
+
+ <li>Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.</li>
+</ul>
+
+<p> </p>
+
+</body></html>
\ No newline at end of file
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+<html>
+
+<head>
+<title>CMSIS Debug Support</title>
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+-----------------------------------------------------------*/
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+<body>
+
+<h1>CMSIS Debug Support</h1>
+<p align="center">This file describes the CMSIS Debug support available with CMSIS (starting V1.30).</p>
+<p align="center">Version: 1.02 - 25. July 2011</p>
+
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
+ Copyright � ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
+<ul>
+ <li>Version 1.00: Initial Release. </li>
+ <li>Version 1.01: Internal Review. </li>
+ <li>Version 1.02: Removed product specific information. </li>
+</ul>
+
+<hr>
+
+<h2>Contents</h2>
+
+<ol>
+ <li class="LI2"><a href="#About">About</a></li>
+ <li class="LI2"><a href="#ITM_DbgAcc">Cortex-M3 / Cortex-M4 ITM Debug Access</a></li>
+ <li class="LI2"><a href="#DbgIn_DbgOut">Debug IN / OUT functions</a></li>
+ <li class="LI2"><a href="#ITM_DbgSup">ITM Debug Support in Debugger</a></li>
+</ol>
+
+<p> </p>
+<h2><a name="About"></a>About</h2>
+<p>
+ CMSIS provides for Cortex-M3 / Cortex-M4 processor based microcontrollers debug support via the Instrumented Trace Macrocell (ITM).
+ This document describes the available CMSIS Debug functions and the used methods.
+</p>
+
+<p> </p>
+<h2><a name="ITM_DbgAcc"></a>Cortex-M3 / Cortex-M4 ITM Debug Access</h2>
+<p>
+ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
+ the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
+ 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
+ communication channels are used by CMSIS to output the following information:
+</p>
+<ul>
+ <li>ITM Channel 0: used for printf-style output via the debug interface.</li>
+ <li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
+</ul>
+
+<p> </p>
+<h2><a name="DbgIn_DbgOut"></a>Debug IN / OUT functions</h2>
+<p>CMSIS provides following debug functions:</p>
+<ul>
+ <li>ITM_SendChar (uses ITM channel 0)</li>
+ <li>ITM_ReceiveChar (uses global variable)</li>
+ <li>ITM_CheckChar (uses global variable)</li>
+</ul>
+
+<h3>ITM_SendChar</h3>
+<p>
+ <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
+ the microcontroller system to the debug system. <br>
+ Only a 8 bit value is transmitted.
+</p>
+<pre>
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ /* check if debugger connected and ITM channel enabled for tracing */
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}</pre>
+
+<h3>ITM_ReceiveChar</h3>
+<p>
+ ITM communication channel is only capable for OUT direction. For IN direction
+ a global variable is used. A simple mechanism detects if a character is received.
+ The project to test need to be build with debug information.
+</p>
+
+<p>
+ The global variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
+ to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to
+ ensure a proper handshake.
+</p>
+<pre>
+extern volatile int32_t ITM_RxBuffer; /* variable to receive characters */
+</pre>
+<p>
+ A dedicated bit pattern is used to determine if <strong>ITM_RxBuffer</strong> is empty
+ or contains a valid value.
+</p>
+<pre>
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+</pre>
+<p>
+ <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
+ It returns the received character or '-1' if no character was available.
+</p>
+<pre>
+static __INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+</pre>
+
+<h3>ITM_CheckChar</h3>
+<p>
+ <strong>ITM_CheckChar</strong> is used to check if a character is received.
+</p>
+<pre>
+static __INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}</pre>
+
+
+<p> </p>
+<h2><a name="ITM_DbgSup"></a>ITM Debug Support in a Debugger</h2>
+<p>
+ The Debugger shall offer a dedicated console window for printf style debug input and output using the CMSIS defined ITM methods described above.
+</p>
+<p>Direction: Microcontroller -> Debugger:</p>
+<ul>
+ <li>
+ at the beginning of a debug session the debugger shall enable ITM trace on channel 0 and continuously snoop for channel 0 data on the ITM trace
+ stream it receives from the Microcontroller's CoreSight ITM unit
+ </li>
+ <li>
+ data received via the ITM communication channel 0 is interpreted as charater and gets redirected into the dedicated <strong>Console Window</strong>
+ </li>
+</ul>
+
+<p>Direction: Debugger -> Microcontroller:</p>
+<ul>
+ <li>
+ at the beginning of a debug session the debugger shall seek for the presence of the global variable named <strong>ITM_RxBuffer</strong> in the debug
+ information of the application being loaded
+ </li>
+ <li>
+ strings entered into the <strong>Console Window</strong> are written by the debugger as a stream of char values via the variable <strong>ITM_RxBuffer</strong>.
+ </li>
+ <li>
+ the debugger writes the next character into the <strong>ITM_RxBuffer</strong> only once the value has been read and the <strong>ITM_RXBUFFER_EMPTY</strong> value being set.
+ (refer to: ITM_ReceiveChar()).
+</ul>
+
+</body>
+
+</html>
\ No newline at end of file
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_History.htm b/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_History.htm
new file mode 100644
index 00000000..a906ae99
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/Documentation/CMSIS_History.htm
@@ -0,0 +1,472 @@
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+
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+<title>CMSIS Version History</title>
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+</style>
+</head>
+
+<body>
+
+<h1>CMSIS Version History</h1>
+<p align="center">This document describes the changes between the different CMSIS versions.</p>
+<p align="center">Version: 2.10 - July 2011</p>
+
+<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
+ Copyright � ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+
+<h2>Contents</h2>
+
+<ol>
+ <li class="LI2"><a href="#Toolchain">Used Toolchains</a></li>
+ <li class="LI2"><a href="#6">Changes to version V2.00</a></li>
+ <li class="LI2"><a href="#5">Changes to version V1.30</a></li>
+ <li class="LI2"><a href="#4">Changes to version V1.20</a></li>
+ <li class="LI2"><a href="#2">Open Points</a></li>
+ <li class="LI2"><a href="#1">Limitations</a></li>
+</ol>
+
+
+<h2><a name="Toolchain"></a>Used Toolchains</h2>
+<p>
+ Following toolchains have been used for test / verification:</i>.
+</p>
+ <ul>
+ <li>ARM: MDK-ARM Version 4.21</li>
+ <li>GNU: Sourcery G++ Lite Edition for ARM 2010.09-51</li>
+ <li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
+ </ul>
+
+
+<h2><a name="6"></a>Changes to version V2.00</h2>
+
+<h3>Added CMSIS DSP Software Library support for Cortex-M0 based MCUs</h3>
+<p>
+ The <strong>CMSIS DSP Software Library</strong> provides now also libraries and examples for Cortex-M0.
+</p>
+<p>
+ For more information refer to <i>CMSIS DSP Library documentation</i>.
+</p>
+
+<h3>Added big endian support for DSP library</h3>
+<p>
+ The <strong>CMSIS DSP Software Library</strong> provides now also pre-build libraries
+ and projects for big endian devices.
+</p>
+<p>
+ For more information refer to <i>CMSIS DSP Library documentation</i>.
+</p>
+
+
+<h3>Simplified folder structure for CMSIS include files</h3>
+<p>
+ All CMSIS core include files as well as the DSP-Library header files are located in
+ a single folder <strong>./CMSIS/Include</strong>.
+</p>
+
+<h3>Changed folder structure for Device Support packages</h3>
+<p>
+ Device Support packages are expected to be in folder <strong>./Device</strong> located at the
+ same level as <strong>./CMSIS</strong>.
+</p>
+<p>The new Device folder contains the following subfolders:</p>
+ <ul>
+ <li><b>Device</b></li>
+ <ul>
+ <li><<b>Vendor</b>>
+ <ul>
+ <li><<b>Device</b>> | <<b>Device Series</b>>
+ <ul>
+ <li><b>Include</b><br>
+ <device>.h<br>
+ system_<device>.h<br>
+ </li>
+ <li><b>Source</b>
+ <ul>
+ <li><b>Templates</b><br>
+ system_<device>.c<br>
+ <ul>
+ <li><<b>Toolchain</b>><br>
+ startup_<device>.s<br>
+ </li>
+ <li><<b>Toolchain</b>></li>
+ <li>...</li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ <li><<b>Device</b>> | <<b>Device Series</b>></li>
+ <li>...</li>
+ </ul>
+ </li>
+ <li><<b>Vendor</b>></li>
+ <li>...</li>
+ </ul>
+ </li>
+ </ul>
+<p>Template files are application specific files and are required to be copied to the project prior to use!</p>
+
+<h3>Removed CMSIS core source files</h3>
+<p>
+ The CMSIS core source files <strong>core_cm0.c, core_cm3.c, core_cm4.c</strong>
+ containing helper functions for older ARM compiler versions got removed.
+</p>
+<p>
+ For the <b>ARM Compiler Toolchain </b>version <b>V4.0.677</b> or later is
+ required!</p>
+
+
+<h2><a name="5"></a>Changes to version V1.30</h2>
+
+<h3>Added CMSIS DSP Software Library</h3>
+<p>
+ The <strong>CMSIS DSP Software Library</strong> is a suite of common signal processing functions targeted
+ to Cortex-M processor based microcontrollers. Even though the code has been specifically
+ optimized towards using the extended DSP instruction set of the Cortex-M4 processor,
+ the library can be compiled for any Cortex-M processor.
+</p>
+<p>
+ For more information see <i>CMSIS DSP Library documentation</i>.
+</p>
+
+<h3>Added CMSIS System View Description</h3>
+<p>
+ The <strong>CMSIS System View Description</strong> answers the challenges of accurate, detailed and
+ timely device aware peripheral debugging support for Cortex Microcontroller based
+ devices by the software development tools vendor community.
+</p>
+<p>
+ Silicon vendors shall create and maintain a formalized description of the debug view
+ for all the peripherals contained in their Cortex Microcontroller based devices.
+ Tool vendors use such descriptions to establish device specific debug support in
+ their debugging tools.
+</p>
+<p>
+ A standardized System View Description shall provide a common approach to
+ capturing peripheral debug related information in a machine readable files.
+</p>
+<p>
+ For more information see <i>CMSIS System View Description</i>.
+</p>
+
+<h3>Added Cortex-M4 Core Support</h3>
+<p>
+ Additional folder <strong>CM4</strong>, containing the Cortex-M4 core support files, has been added.
+</p>
+ <ul>
+ <li>CM0</li>
+ <li>CM3</li>
+ <li>CM4
+ <ul>
+ <li>CoreSupport</li>
+ <li>DeviceSupport</li>
+ </ul>
+ </li>
+ </ul>
+
+<h3>New naming for Core Support Files</h3>
+<p>
+ The new Core Support Files are:
+</p>
+<ul>
+ <li>core_cm#.h (# = 0, 3, 4)</li>
+ <li>core_cmFunc.h (Cortex-M Core Register access functions)</li>
+ <li>core_cmInstr.h (Cortex-M Core instructions)</li>
+ <li>core_cm4_simd.h (Cortex-M4 SIMD instructions)</li>
+</ul>
+
+<h2><a name="4"></a>Changes to version V1.20</h2>
+
+<h3>Removed CMSIS Middelware packages</h3>
+<p>
+ CMSIS Middleware is removed and no longer focus of CMSIS.
+</p>
+
+<h3>SystemFrequency renamed to SystemCoreClock</h3>
+<p>
+ The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
+ because the variable holds the clock value at which the core is running.
+</p>
+
+<h3>Changed startup concept</h3>
+<p>
+ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
+ from main) has the weakness that it does not work for controllers which need a already
+ configuerd clock system to configure the external memory controller.
+</p>
+
+<h5>Changed startup concept</h5>
+<ul>
+ <li>
+ SystemInit() is called from startup file before <strong>premain</strong>.
+ </li>
+ <li>
+ <strong>SystemInit()</strong> configures the clock system and also configures
+ an existing external memory controller.
+ </li>
+ <li>
+ <strong>SystemInit()</strong> must not use global variables.
+ </li>
+ <li>
+ <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
+ </li>
+ <li>
+ Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
+ <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
+ and must be called whenever the core clock is changed.<br>
+ <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
+ the current core clock.
+ </li>
+</ul>
+
+
+<h3>Advanced Debug Functions</h3>
+<p>
+ ITM communication channel is only capable for OUT direction. To allow also communication for
+ IN direction a simple concept is provided.
+</p>
+<ul>
+ <li>
+ Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
+ </li>
+ <li>
+ Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
+ </li>
+ <li>
+ Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
+ </li>
+</ul>
+
+<p>
+ For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
+</p>
+
+
+<h3>Core Register Bit Definitions</h3>
+<p>
+ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
+ defines correspond with the Cortex-M Technical Reference Manual.
+</p>
+<p>
+ e.g. SysTick structure with bit definitions
+</p>
+<pre>
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */</pre>
+
+<h3>DoxyGen Tags</h3>
+<p>
+ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
+ using DoxyGen.
+</p>
+
+<h3>Folder Structure</h3>
+<p>
+ The folder structure is changed to differentiate the single support packages.
+</p>
+
+ <ul>
+ <li>CM0</li>
+ <li>CM3
+ <ul>
+ <li>CoreSupport</li>
+ <li>DeviceSupport</li>
+ <ul>
+ <li>Vendor
+ <ul>
+ <li>Device
+ <ul>
+ <li>Startup
+ <ul>
+ <li>Toolchain</li>
+ <li>Toolchain</li>
+ <li>...</li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ <li>Device</li>
+ <li>...</li>
+ </ul>
+ </li>
+ <li>Vendor</li>
+ <li>...</li>
+ </ul>
+ </li>
+ <li>Example <i>(optional)</i>
+ <ul>
+ <li>Toolchain
+ <ul>
+ <li>Device</li>
+ <li>Device</li>
+ <li>...</li>
+ </ul>
+ </li>
+ <li>Toolchain</li>
+ <li>...</li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+
+ <li>Documentation</li>
+ </ul>
+
+<h2><a name="2"></a>Open Points</h2>
+<p>
+ Following points need to be clarified and solved:
+</p>
+<ul>
+ <li>
+ <p>
+ Equivalent C and Assembler startup files.
+ </p>
+ <p>
+ Is there a need for having C startup files although assembler startup files are
+ very efficient and do not need to be changed?
+ <p/>
+ </li>
+ <li>
+ <p>
+ Placing of HEAP in external RAM.
+ </p>
+ <p>
+ It must be possible to place HEAP in external RAM if the device supports an
+ external memory controller.
+ </p>
+ </li>
+ <li>
+ <p>
+ Placing of STACK /HEAP.
+ </p>
+ <p>
+ STACK should always be placed at the end of internal RAM.
+ </p>
+ <p>
+ If HEAP is placed in internal RAM than it should be placed after RW ZI section.
+ </p>
+ </li>
+</ul>
+
+
+<h2><a name="1"></a>Limitations</h2>
+<p>
+ The following limitations are not covered with the current CMSIS version:
+</p>
+<ul>
+ <li>
+ No <strong>C startup files</strong> are available.
+ </li>
+</ul>
+
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+<h1 class="style1">Cortex Microcontroller Software Interface Standard<br>
+System View Description</h1>
+
+<p class="style1">This file describes the Cortex Microcontroller Software
+Interface Standard - System View Description (CMSIS - SVD) concept and syntax.</p>
+<p class="style1">Version: 1.02 - 27. July 2011</p>
+
+<p class="style1">Information in this file, the accompany manuals, and software is<br>
+ Copyright � ARM Ltd.<br>All rights reserved.
+</p>
+
+<hr>
+
+<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
+<ul>
+ <li>Version 0.91: initial proposal.</li>
+ <li>Version 0.92: revised proposal considering forum feedback (e.g. consider
+ IP-XACT constructs and naming scheme)</li>
+ <li>Version 1.0: new elements: peripheral version, vendor specific
+ extension section, interrupt mapping information, global peripheral disable
+ condition, naming of register arrays, enhanced naming schemes, etc.</li>
+ <li>Version 1.0: SVD versioning and updated schema file</li>
+ <li>Version 1.01: Error corrections in the example code. "include" has been removed. Restricted to one device per file.</li>
+ <li>Version 1.02: Adding the use case of device header file generation.</li>
+</ul>
+
+<p> </p>
+
+<hr>
+
+<h2>Contents</h2>
+
+<ol>
+ <li class="LI2"><a href="#1">About</a></li>
+ <li class="LI2"><a href="#2">Motivation</a></li>
+ <li class="LI2"><a href="#3">Requirements</a></li>
+ <li class="LI2"><a href="#4">Format</a></li>
+ <li class="LI2"><a href="#5">Example</a></li>
+ <li class="LI2"><a href="#6">Questions & Answers</a></li>
+</ol>
+
+<h2><a name="1"></a>About</h2>
+
+<p>
+ The <strong>Cortex Microcontroller Software Interface Standard - System View
+ Description</strong> (CMSIS - SVD) answers the challenges
+ of accurate, detailed and timely device aware peripheral debugging support for Cortex
+ Microcontroller based devices by the software development
+ tools vendor community.
+</p>
+<p>
+ Silicon vendors shall create and maintain a formalized description of the
+ debug view for all the peripherals contained in their Cortex
+ Microcontroller based devices. Tool vendors use such descriptions to
+ establish device specific debug support in their debugging tools with minimal turn around times and
+ manageable effort. Device support across many development tools is
+ essential for silicon provider in order to promote new devices and device
+ variants entering the market. Device aware debug views provide fast and
+ convenient access to all registers and fields as well as a detailed
+ description. This enables software developer to
+ develop and debug code most efficiently and adopt new devices early and
+ quickly.</p>
+<p>
+ A standardized System View Description shall provide a common approach to
+ capturing peripheral debug related information in a machine readable files.
+ The scope of the contained information is agreed to match the level usually
+ provided by silicon vendors in their device reference manuals, however in a
+ formalized XML based format. There
+ are other description languages already available. IP-XACT from the SPIRIT
+ consortium is a prominent example. IP-XACT covers the register description
+ sufficiently, however it comprises many other aspects of the devices like
+ ports, bus-protocols, modeling, tool flows, etc. making a direct use of
+ IP-XACT too complex. The design of the SVD language is
+ taking some guidance from IP-XACT thus allowing straight forward conversion
+ from IP-XACT to CMSIS-SVD where IP-XACT device information is already
+ available.</p>
+<p>
+ In a second step the CMSIS-SVD description shall be used for automatically
+ generating CMSIS compliant a device header file. This enables the
+ information in the header file to be consistent with what the debugger will
+ display and CMSIS compliant by construction. The header file generation will
+ require some additional pieces of information and therefore a future version
+ of the description will need to include some extensions for this purpose.</p>
+<p>
+ Device aware debugging support is only one aspect of device
+ support essential to software development environments, however it is one of
+ the most time consuming and error prone ones.</p>
+<h2><a name="2"></a>Motivation</h2>
+<p>
+
+The software developer of microcontroller devices is faced with a growing number
+of devices with an ever increasing number of peripheral blocks providing a wide
+range of distinct and complex functionality. The development of drivers for
+these peripherals is in the critical path of every project. Modern debuggers are supporting the software developer in getting the
+software to run according to the requirements. A debugger providing peripheral awareness improves the
+ability to access and interpret complex configuration and status information of
+peripherals. Even though this is only one aspect of device support within microcontroller
+development environments it is essential for the successful and timely adoption
+of development tools and the device by the market.</p>
+<p>Today software development environments address device aware
+debugging in various ways. They either use documents or proprietary file formats
+as input for providing peripheral views in the debuggers.
+Extracting peripheral information from written documentation is a very time
+consuming, tedious and error prone task. Having a file containing peripheral specific information to generate peripheral views
+is going to make device support more affordable, reliable and timely.
+The challenge for the tool providers is the support of many
+different and incompatible file formats from a growing number of silicon vendors.
+For silicon vendors it is time consuming and costly to engage with many tool
+provider in order to achieve device support in a wide range of development
+environments.</p>
+<p>Standardizing on a System View Description aims to ease this challenge
+by agreeing on a formal XML-based file format. In conjunction with supporting web server infrastructure silicon partner
+shall upload and maintain such descriptions in a tool vendor agnostic device
+database, hosted e.g. by the web server infrastructure
+<a href="http://cmsis.arm.com">
+cmsis.arm.com</a> . Access control to sensitive information is managed on a per user
+basis. This allows silicon vendors to upload information for devices that have
+not been made public. </p>
+<p>Such an approach provides benefits for silicon and tool vendors as well as
+software developers of Cortex-M based microcontroller devices</p>
+<ul>
+ <li>timely and accurate device support provided by a whole range of tool providers </li>
+ <li>tool providers become more efficient in supporting a multitude of devices
+ and device variants</li>
+ <li>less interaction required between silicon vendors and the
+ tool providers</li>
+ <li>silicon provider has control over and maintains the System View
+ Description during the life cycle of the device</li>
+ <li>high quality device support in terms of completeness and correctness of
+ device aware debugging</li>
+ <li>improved productivity and user experience for the software developer</li>
+</ul>
+<h2><a name="3"></a>Requirements</h2>
+<p>The debug description shall capture the information about all
+the peripherals contained in a specific device. This section describes which
+items of information are deemed relevant for a debugger. Silicon vendors are expected to
+provide the System View Description for their devices, matching the information
+contained in device reference manuals. The System View Description shall be suitable for straight forward
+generation from existing databases like IP-XACT descriptions or SIDSC. The size
+of device description is a concern and therefore redundancy in the description
+shall be avoided. The size of SVD files affects the efficiency of
+distribution as well as the loading time by the development tools. Last but not least manual editing of SVD files shall be possible for
+the purpose of customization by SW developers.</p>
+<h4>Required content of the description</h4>
+<p>From a programmer's perspective a peripheral can be seen as a set of registers
+with unique<em> names</em> being mapped to fixed<em> addresses</em> allocated
+within a defined <em>range</em> of an address space.</p>
+<p>From a debugger's point of view read accesses to a physical register need to be
+executed in order to display its current value. The debugger executes a write
+access to a register when a user edits its value. For this purpose the debugger
+needs to know about the following additional attributes: </p>
+<ul>
+ <li><em>minimal addressable unit </em>= smallest series of bits
+ identified by a unique address (e.g. byte-addressable memory) </li>
+ <li><em>register size</em> = number of bits forming a register (ARM Cortex-M usually
+ 32 bits)</li>
+ <li><em>access permission</em> = read and write, read only,
+ write only</li>
+ <li><em>access side effects</em> = accesses by the debugger must
+ be avoided if it has side effects. Some side effects may be
+ reversed by the debugger to compensate for the side effect</li>
+</ul>
+<p>In many cases peripheral registers are partitioned into chunks of bits of
+distinct functionality. In this document these chunks are referred to as <em>
+field</em>. Each
+register that consists of fields shall be described by a list
+of <em>uniquely named</em> fields (Note: field names are not required to be
+unique across registers). In order for a debugger to extract the
+value of a field from the corresponding register the following attributes are required:</p>
+<ul>
+ <li><em>most significant bit </em>= highest bit position of the
+ bit-field in the corresponding register</li>
+ <li><em>least significant bit</em> = lowest bit position of the
+ bit-field within the corresponding register</li>
+ <li><em>access permission</em> = read and write, read only,
+ write only</li>
+</ul>
+<p>An enumerated value maps a number to a specific descriptive string
+representing the semantics of the value of a field. The debugger displays the
+descriptive string rather than the number to simplify the access to the
+information thus
+avoiding the necessity of a look-up in the device reference manual. Each item of
+an enumerated value has the following attributes:</p>
+<ul>
+ <li><em>value</em> = value of the bit-field that corresponds to
+ the string attribute</li>
+ <li><em>name</em> = short string that describes the semantics of a
+ field when the corresponding value is set</li>
+ <li><em>description</em> = detailed description of the semantics
+ of the field when the corresponding value is set</li>
+</ul>
+<p>The hierarchical structure of the description looks like this:</p>
+<p><strong>Device =</strong></p>
+<ul>
+ <li>
+ <p> <strong>Peripherals</strong></p>
+ <ul>
+ <li>
+ <p class="style2"><strong>Peripheral</strong></p>
+ <ul>
+ <li>
+ <p class="style2"><strong>Registers</strong></p>
+ <ul>
+ <li>
+ <p class="style2">
+ <strong>Register</strong></p>
+ <ul>
+ <li>
+ <p class="style2">
+ <strong>Fields</strong></p>
+ <ul>
+ <li>
+ <p class="style2"><strong>Field</strong></p>
+ <ul>
+ <li>
+ <p class="style2"><strong>Enumerated Values</strong></p>
+ <ul>
+ <li>
+ <p class="style2"><strong>Enumerated Value</strong></p>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+</ul>
+
+<p>One file can only contain a description for a single device or device family
+sharing the identical description. Devices consists of a one or more peripherals.
+Each peripheral contains
+one or more registers, where each register may consist of one or more fields.
+The values of a field maybe represented through descriptive strings and detailed
+descriptions, the enumerated values.</p>
+<p>In many cases there are multiple
+instances of the same peripheral in a device (e.g. Timer0, Timer1, etc.). For
+this reason the description has the concept of deriving a peripheral from a peripheral
+that has already been described. The attribute <em>derivedFrom </em>specifies
+such a relationship.
+Similarly registers or fields can be reused within the device description. The
+grouping of peripherals providing
+similar functionality (e.g. Simple Timer, Complex Timer) is controlled via the element <em>groupName</em>.
+All peripherals associated with the same group name are collectively listed under this group
+in the order they have been specified in the file.
+Collecting
+similar or related peripherals into peripheral groups helps structuring the list
+of peripherals e.g. in a drop down menu (tool dependent). Devices with a large
+set of peripherals will benefit from this additional level of structure.</p>
+<p>Each of the items (i.e. Device, Peripheral, Register and
+Field) owns an <em>description </em>element containing verbose information about
+the respective element. The description field plays
+an important part in improving the software development productivity. Instead of
+searching through the reference manual the detailed explanation from the manual
+could become immediately accessible from within the development environment.</p>
+<p>Details about the exact display format and layout of the peripheral view are
+considered beyond the scope of the description. It is up to the tool vendor to
+visualize the contained information appropriately. The
+silicon vendor provides details about the device's peripherals that is commonly available. </p>
+<p>System View Description files need to be validated for:</p>
+<ol>
+ <li>syntactical correctness using XML-Schema checking utilities</li>
+ <li>consistency of the provided information (e.g. multiple registers mapped to the same address,
+ all registers located within the specified address ranges of a
+ peripheral, all fields are within the range of the register
+ size, etc.) by a utility developed by ARM (SVDConv.exe)</li>
+ <li> semantical correctness of the System View Description
+ against the silicon specification executed by the silicon vendor</li>
+</ol>
+<p>The SVD description format was extended by numerous elements during the
+review period targeting version 1.0 and new extensions are expected for future
+versions of this format. A new section named "vendorExtensions" has been added
+to the end of the top level to allow silicon vendors and tool partners to
+innovate and expand the description in order to overcome limitations of the
+current specification until these can be incorporated into new versions of
+CMSIS-SVD. <br>
+</p>
+
+<h2> <a name="4"></a><span class="style9">Format</span></h2>
+
+<p>
+ The following section describes the SVD file format in detail. Each subsection
+ defines a single hierarchy level of the description and lists all mandatory
+ and optional language elements for that specific level including type
+ information for each element. Each element is discussed in more detail and a
+ brief snippet is provided as an example. The sequence of elements shown
+ below is binding. Optional elements are highlighted in green, blue elements
+ are mandatory unless they have been already specified globally on a higher
+ level.</p>
+<p>
+ An XML-schema file is provided alongside this document for syntactical
+ checking of descriptions being developed.</p>
+<h4><device schemaVersion="xs:decimal" <span class="style2"><em>xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd</em></span>"></h4>
+<p> <<span class="style2">name><em>xs:Name</em></name><br>
+ <version<em>>xs:string<</em>/version><br>
+ <description><em>xs:string</em></description><br>
+</span> <<span class="style2">addressUnitBits><em>scaledNonNegativeInteger</em></addressUnitBits><br>
+ <width><em>scaledNonNegativeInteger</em> </width></span><br>
+<br>
+ <span class="style4"> <</span><span class="style2"><span class="style4">size><em>scaledNonNegativeInteger</em></size><em><br>
+</em> <access><em>accessType</em></access><br>
+ <resetValue><em>scaledNonNegativeIntege</em>r</resetValue><br>
+ <resetMask><em>scaledNonNegativeInteger</em></resetMask></span></span></p>
+<p> <peripherals><br>
+ ...<br>
+ </peripherals><br>
+<span class="style4"> <vendorExtensions><br>
+ ...<br>
+ </vendorExtensions></span></p>
+<h4></device></h4>
+<p>The <strong>device</strong> provides the outermost frame of the description. All other
+elements like peripherals, registers and fields are described inside of this scope. A device contains one or more peripherals.
+The optional elements size, access, resetValue and resetMask are used as default values throughout the
+device description unless they get overruled on a lower level of the description
+(e.g. peripheral or register).</p>
+<h4>Mandatory items:</h4>
+<p><strong>name = </strong>the unique name string is used to identify the device.
+All devices of a silicon vendor are required to have a unique name. In case an
+SVD description covers a family or series of devices, the name of the series or
+family is placed here. The device names of the members of the series or family
+are listed in <memberDevices></p>
+<p><strong>description = </strong>string describing main features of a device
+(e.g. CPU, clock frequency, peripheral overview, etc.)</p>
+<p><strong>version = </strong>the string is defining the version of the
+description for this device. Silicon vendors will maintain the description
+throughout the lifecycle of the device and need to ensure that all updated and
+released copies have a unique version string indicating the order in which. Note: this must not be used for
+detailing the version of the device.</p>
+<p> </p>
+<p><strong>addressUnitBits = </strong>defines the number of data bits for each address
+increment. The value for Cortex-M based devices is 8 (byte-addressable).</p>
+<p><strong>width = </strong>defines the number of bits for the maximum single
+transfer size allowed by the bus interface hence the maximum size of a single
+register that can be defined for the address space. This information is relevant
+for debuggers when determining the size of debug transfers. The expected value
+for Cortex-M based devices is 32.</p>
+<p><strong>peripherals = </strong>next level of description (see next section
+for details)</p>
+<h4>Optional Items:</h4>
+<p><strong>size = </strong>defines the default bit-width of registers contained
+in the device. This element can be overruled by re-specifying the size element on a lower level of the
+description.</p>
+<p><strong>access =</strong> defines the default access permissions for all
+registers in the device. The allowed tokens are:<br>
+ - <em>read-only</em>: read access is permitted. Write operations have an undefined
+result.<br>
+ - <em>write-only</em>: write access is permitted. Read operations have an
+undefined result. <br>
+ -<em>read-write</em>: both read and write accesses are permitted. Writes affect
+the state of the register and reads return a value related to the register<br>
+ -<em>writeOnce</em>: only the first write after reset has an effect on the
+register. Read operations deliver undefined results<br>
+ -<em>read-writeOnce</em>: Read operations deliver a result related to the register
+content. Only the first write access to this register after a reset will have an
+effect on the register content.</p>
+<p><strong>resetValue = </strong>defines the default value of all registers
+after a reset. There are scenarios where SW developers need to know, what the
+reset value of a register or field is. Even though listed as optional on this
+level of the description, silicon vendors should ensure that this information is
+provided for all registers. </p>
+<p><strong>resetMask =</strong> defines those bit positions set to one to be
+taken from resetValue element. All other elements are undefined. If a register
+does not have a defined reset value the resetMask needs to be set to 0.</p>
+<p><strong>vendorExtensions </strong>= the content and format of this section of
+the description is unspecified. Silicon vendors may choose to provide additional
+information. The assumption is that by default this section is completely
+ignored by the debugger. It is up to the silicon vendor to specify the content
+of this section and share the specification with the tool vendors. The new
+elements shall be considered for a future version of the description format.</p>
+<h4>Example:</h4>
+<pre><device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+ <name>CMSIS_Cortex-M3</name>
+ <version>0.1</version>
+ <description>ARM Cortex-M3 based Microcontroller demonstration device</description>
+ <addressUnitBits>8</addressUnitBits>
+ <width>32</width>
+ <size>32</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0xffffffff</resetMask></pre>
+<pre> <peripherals>
+ ...
+ </peripherals>
+</device></pre>
+<p>The device description above is at version 0.1 and uniquely identifies the
+device by the name "CMSIS_Cortex-M3". The peripherals are memory mapped in a
+byte-addressable address space with a bus width of 32 bits. The default size of
+the registers contained in the peripherals is set to 32 bits. Unless redefined
+for specific peripherals, registers or fields all registers are read-write
+accessible. A reset value of 0 valid for all 32 bits as specified by the reset
+mask is set for all registers unless overruled at a lower level of the description.</p>
+<hr>
+<h4><peripherals></h4>
+<p> <peripheral><br>
+ ...<br>
+ </peripheral></p>
+<p> ...</p>
+<p> <peripheral><br>
+ ...<br>
+ </peripheral></p>
+<h4></peripherals></h4>
+<p>This construct sets the frame for all peripherals and peripheral groups contained in a device. This
+creates a container element which ease-up processing with languages like Java.</p>
+<hr>
+<h4><peripheral <span class="style2"><span class="style4">derivedFrom=<em>"xs:Name"</em></span></span>></h4>
+<p> <name><em>xs:Name</em></name><br>
+ <span class="style4"><version>xs:string</name></span><br>
+ <description><em>xs:string </em></description><br>
+ <span class="style4"><groupName><em>xs:string</em></groupName><br>
+ <prependToName><em>xs:string</em></prependToName><br>
+ <appendToName><em>xs:string</em></appendToName></span><br>
+ <span class="style4"><disableCondition><em>xs:string</em></disableCondition></span><br>
+ <baseAddress><em>scaledNonNegativeInteger</em></baseAddress><br>
+ <span class="style4"> <</span><span class="style2"><span class="style4">size><em>scaledNonNegativeInteger</em></size><em><br>
+</em> <access><em>accessType</em></access><br>
+ <resetValue><em>scaledNonNegativeIntege</em>r</resetValue><br>
+ <resetMask><em>scaledNonNegativeInteger</em></resetMask></span></span></p>
+<p> <span class="style10"><addressBlock><br>
+ <offset></span><em>scaledNonNegativeInteger</em><span class="style10"></offset><br>
+ <size></span><em>scaledNonNegativeInteger</em><span class="style10"></size><br>
+ <usage<em>>usageType<</em>/usage><br>
+<em> </</em>addressBlock><em><br>
+</em> ...<br>
+</span> <span class="style10"><span class="style4"><addressBlock><br>
+ <offset></span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4"></offset><br>
+ <size></span></span><span class="style4"><em>scaledNonNegativeInteger</em></span><span class="style10"><span class="style4"></size><br>
+ <usage><em>usageType</em></usage><br>
+<em> </</em>addressBlock><br>
+ <interrupt><br>
+ <name><em>xs:string</em></name><br>
+ <value><em>scaledNonNegativeInteger</em></value><br>
+ </interrupt></span><em><br>
+</em></span> <registers><br>
+ ...<br>
+ </registers></p>
+<h4></peripheral></h4>
+<p>A peripheral encloses the description of one or more registers belonging to
+this named peripheral. The address range allocated in the address space for this
+peripheral is defined through one or more address ranges. An address range is
+specified relative to the base address of the peripheral. This information
+allows to display a memory map overview for all peripherals. Please note that
+such a memory map does not contain any information for memories and unoccupied
+address ranges.</p>
+<h4>Mandatory items:</h4>
+<p><strong>name = </strong>name string used to identify the peripheral. Peripheral
+names are required to be unique within the scope of a device.</p>
+<p><strong>baseAddress </strong>= lowest address reserved or used by the peripheral</p>
+<p><strong>description = </strong>string providing an overview of the purpose
+and functionality of the peripheral</p>
+<p><strong>addressBlock = </strong>a peripheral may occupy one or more disparate
+blocks in the address space. An addressBlock is a complex element consisting of
+the mandatory elements:<br>
+ <strong>offset</strong>: specifying the start address of an address block. It
+is calculated from the sum of baseAddress and offset<br>
+ <strong>size</strong>: specifying the number of addressUnitBits being covered
+by this address block. The end address of an address block is the sum of start
+address and the size - 1.<br>
+ <strong>usage</strong>: the usage element is of <em>usageType </em>specifying
+if the addresses within the specified address block is used for<strong> </strong>
+<em>registers</em><strong> </strong>or <em>buffer</em><strong> </strong>or is <em>reserved</em>.
+<br>
+Note: registers must not be allocated
+to an address within a reserved or buffer address range.</p>
+<p><strong>registers = </strong>next lower level of description (see next section
+for details)</p>
+<h4>Optional items:</h4>
+<p><strong>derivedFrom = </strong>this attribute specifies the name of a peripheral
+that has already been described for this device. The description of that device
+will be copied. It is mandatory to overwrite the name as well as the
+addressOffset. All other specified information will overwrite the respective
+elements in the copy.</p>
+<p><strong>version = </strong>the string specifies the version of this
+peripheral description.</p>
+<p><strong>disableCondition = </strong>C language compliant logical expression
+resulting in a true or false result. If "true" the refresh of the display
+for this peripheral is disabled
+and related accesses by the debugger are suppressed. Only constants and references to other registers
+contained in the description are allowed:
+<peripheral>-><register>-><field> (e.g.: (System->ClockControl->apbEnable == 0)).
+Only the following operators are allowed [&&,||, ==, !=, >>, <<, &, |]. Warning!
+This feature must only be use in case accesses from the debugger to registers of
+un-clocked peripherals result in severe debugging failures. SVD is intended to
+be fully static information and not include any run-time computation or
+functions such capabilities may be added by the tools but is considered beyond
+the scope of this description language.</p>
+<p><strong>prependToName = </strong>all register names of this peripheral have
+their names prepended with the string specified</p>
+<p><strong>appendToName = </strong>all register names of this peripheral have
+their names appended with the string specified</p>
+<p><strong>size = </strong>defines the default bit-width of registers contained
+in the device. This element can be overruled by re-specifying the size element on a lower level of the
+description.</p>
+<p><strong>access =</strong> defines the default access permissions for all
+registers in the peripheral. The value can be reset on a lower level of the
+description. The allowed tokens are:<br>
+ - <em>read-only</em>: read access is permitted. Write operations have an undefined
+result.<br>
+ - <em>write-only</em>: write access is permitted. Read operations have an
+undefined result. <br>
+ -<em>read-write</em>: both read and write accesses are permitted. Writes affect
+the state of the register and reads return a value related to the register<br>
+ -<em>writeOnce</em>: only the first write after reset has an effect on the
+register. Read operations deliver undefined results<br>
+ -<em>read-writeOnce</em>: Read operations deliver a result related to the register
+content. Only the first write access to this register after a reset will have an
+effect on the register content.</p>
+<p><strong>resetValue = </strong>defines the default value of all registers
+after a reset but can be set for individual registers and fields on a lower
+level of the description.</p>
+<p><strong>resetMask =</strong> defines those bit positions set to one to be
+taken from resetValue element. All other elements are undefined. This is the
+default value for the whole peripheral but can be readjusted on lower levels. If
+a register does not have a defined reset value the resetMask needs to be set to
+0.</p>
+<p><strong>interrupt = </strong>is a complex type that consists of the <strong>name</strong> of
+the interrupt and the associated enumeration<strong> value</strong>. A peripheral can also have
+multiple associated interrupts. This entry is mainly intended for information
+only purposes in order to display the interrupts and respective interrupt
+numbers associated with a peripheral.</p>
+<h4>Example:</h4>
+<pre>...
+ <peripheral>
+ <name>Timer0</name>
+ <version>1.0.32</version>
+ <description>Timer 0 is a simple 16 bit timer counting down ... </description>
+ <baseAddress>0x40000000</baseAddress>
+ <addressBlock>
+ <offset>0x0</offset>
+ <size>0x400</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <interrupt><name>TIM0_INT</name><value>34</value></interrupt>
+ <registers>
+ ...
+ </registers>
+ </peripheral>
+ <peripheral derivedFrom="Timer0">
+ <name>Timer1</name>
+ <baseAddress>0x40000400</baseAddress>
+ </peripheral>
+
+...</pre>
+<hr>
+<h4><registers> ... </registers></h4>
+<p>This construct sets the frame for all registers contained in a peripheral.
+This creates container elements which ease-up processing with languages like Java.</p>
+<hr>
+<h4><register <span class="style2">derivedFrom=<em>xs:Name</em></span>></h4>
+<p> <span class="style4"><dim><em>scaledNonNegativeInteger</em></dim><br>
+ <dimIncrement><em>scaledNonNegativeInteger</em></dimIncrement><br>
+ <dimIndex><em>xs:string</em></dimIndex></span><br>
+ <<span class="style2">name><em>xs:Name</em></name><br>
+ <span class="style4"><displayName><em>xs:string</em></displayName></span><br>
+</span> <span class="style2"><description><em>xs:string</em></description></span><br>
+ <span class="style2"> <span class="style4"><alternateGroup><em>xs:Name</em></alternateGroup></span><br>
+</span> <span class="style2"> <addressOffset><em>scaledNonNegativeInteger</em>
+</addressOffset><br>
+ <span class="style5"> <size><em>scaledNonNegativeInteger</em></size><br>
+</span><span class="style4"> </span><span class="style5"> <access><em>accessType</em></access><br>
+ </span><span class="style4"><</span><span class="style5">resetValue><em>scaledNonNegativeInteger</em></resetValue><br>
+ <resetMask><em>scaledNonNegativeInteger</em></resetMask><br>
+</span>
+</span><span class="style4"> <modifiedWriteValues><em>writeValueType</em></modifiedWriteValues><br>
+ <writeConstraint><em>writeConstraintType</em></writeConstraint><br>
+ <readAction><em>readActionType</em> </readAction></span><span class="style2"><br>
+</span> <span class="style4"><fields><br>
+ ...<br>
+ </fields></span> </p>
+<h4></register></h4>
+<p>The definition of registers is the central part of the description. A
+register may use its complete size for a single purpose and therefore not
+consist of fields. Otherwise the description
+of fields is mandatory.</p>
+<h4>Mandatory items:<br>
+</h4>
+<p><strong>name = </strong>name string used to identify the register. Register
+names are required to be unique within the scope of a peripheral.</p>
+<p><strong>description = </strong>string describing the details of the register.</p>
+<p><strong>addressOffset = </strong>value defining the address of the register relative to
+the baseAddress defined by the peripheral the register belongs to.<br>
+</p>
+<p><span class="style5">The following elements can be omitted</span> if the corresponding value has been set
+on a higher level of the description and matches the value required for this register:</p>
+<p><strong>size =</strong>value defining the bit-width of the register</p>
+<p><strong>access =</strong> predefined tokens: read-only, write-only, read-write,
+writeOnce, read-writeOnce strings defining the allowed
+accesses for this register.</p>
+<p><strong>resetValue =</strong> element defining the value of the register
+immediately after a reset.</p>
+<p><strong>resetMask= </strong>element specifying those bits of the resetValue that
+are defined<strong> </strong>(bit positions containing a 0 bit are ignored, bit
+positions containing a 1 bit are taken from the corresponding bit position of
+the resetValue). If a register does not have a defined reset value the resetMask
+needs to be set to 0.</p>
+<h4>Optional items:</h4>
+<p><strong>dim = </strong>if this field is specified the value defines the
+number of elements in an array of registers.</p>
+<p><strong>dimIncrement =</strong> if dim is specified this element becomes
+mandatory and specifies the address increment in between
+two neighboring registers of the register array in the address map.</p>
+<p><strong>dimIndex = </strong>this element specifies the substrings within the
+register array names that will replace the %s within the register name. By
+default the index is a decimal value starting with 0 for the first register.
+Examples:<br>
+ <dim>6</dim> <dimIncrement>4</dimIncrement> <dimIndex>A,B,C,D,E,Z</dimIndex>
+<name>GPIO_%s_CTRL</name> ...<br>
+ => GPIO_A_CTRL, GPIO_B_CTRL, GPIO_C_CTRL, GPIO_D_CTRL, GPIO_E_CTRL,
+GPIO_Z_CTRL<br>
+ <dim>4</dim> <dimIncrement>4</dimIncrement> <dimIndex>3-6</dimIndex>
+<name>IRQ%s</name> ... <br>
+ => IRQ3, IRQ4, IRQ5, IRQ6 </p>
+<p><strong>displayName = </strong>when used, this is the string being used by a
+graphical frontend to visualize the register otherwise the name element is used.
+Note: the display name may contain special characters and white spaces. It also
+uses "%s" as the place holder for the dimIndex substring.</p>
+<p><strong>alternateGroup =</strong> when used, this element specifies a name of
+a group that all alternate register with the same name a associated with. At the
+same time it indicates that there is a register description allocating the same
+absolute address in the address space. </p>
+<p><strong>modifiedWriteValues = </strong>element to describe the manipulation of
+data written to a register. If not specified the value written to the field is the
+value stored in the field. The other options are bitwise operations: <br>
+ <em>oneToClear:</em> write data bits of one shall clear (set to zero) the
+corresponding bit in the register<br>
+ <em>oneToSet:</em> write data bits of one shall set (set to one) the
+corresponding bit in the register<br>
+ <em>oneToToggle:</em> write data bits of one shall toggle (invert) the
+corresponding bit in the register<br>
+ <em>zeroToClear:</em> write data bits of zero shall clear (set to zero)
+the corresponding bit in the register<br>
+ <em>zeroToSet:</em> write data bits of zero shall set (set to one) the
+corresponding bit in the register<br>
+ <em>zeroToToggle:</em> write data bits of zero shall toggle (invert) the
+corresponding bit in the register<br>
+ <em>clear:</em> after a write operation all bits in the field are cleared (set to
+zero)<br>
+ <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
+ <em>modify:</em> after a write operation all bit in the field may be modified
+(default)</p>
+<p><strong>writeConstraint: </strong>has a set of options:<br>
+ <em>writeAsRead</em> = if true only the last read value can be written<br>
+ <em>useEnumeratedValues</em> = if true only those values listed in the
+enumeratedValues list are considered valid write values<br>
+ <em>minimum</em> = specifies the smallest number to be written to the
+register<br>
+ <em>maximum</em> = specifies the largest number to be written to the
+register</p>
+<p><strong>readAction: </strong>if set it specifies the side effect following
+read operations. If not set the register is not modified following a read
+operations. The defined side effects are:<br>
+ <em>clear:</em> indicates that the register is cleared (set to zero)
+following a read operation<br>
+ <em>set:</em> indicates that the register is set (set to ones) following a
+read operation<br>
+ <em>modify</em>: indicates that the register is modified in some way
+after a read operation<br>
+ <em>modifyExternal: </em>indicates that one or more dependent resources
+other than the current register
+are immediately affected by a read (it is recommended that the register
+description specifies these dependencies). Debuggers are not expected to read
+this register location unless explicitly instructed by user.</p>
+<p><strong>fields = </strong>next lower level of description (see next section
+for details).</p>
+<h4>Optional attribute:</h4>
+<p><strong>derivedFrom = </strong>specifies the name of the register to be
+replicated. Elements being specified underneath will override the values specified
+from the register being derived from. Note that it is mandatory to overwrite at
+least name and addressOffset.</p>
+<h4>Example:</h4>
+<pre>...
+ <register>
+ <name>TimerCtrl0</name>
+ <description>Timer Control Register</description>
+ <addressOffset>0x0</addressOffset>
+ <access>read-write</access>
+ <resetValue>0x00008001</resetValue>
+ <resetMask>0x0000ffff</resetMask>
+ <size>32<size>
+ <fields>
+ ...
+ </fields>
+ </register>
+ <register derivedFrom="TimerCtrl0">
+ <name>TimerCtrl1</name>
+ <addressOffset>0x4<addressOffset>
+ </register>
+...</pre>
+<hr>
+<h4><fields> ... </fields></h4>
+<p>This construct sets the frame for all fields contained in a register.
+This creates container elements which ease-up processing with languages like Java.</p>
+<hr>
+<h4> <field <span class="style2">derivedFrom=<em>"xs:Name</em>"</span>></h4>
+<p> <span class="style2"> <name><em>xs:Name</name><br>
+ </em></span> <description><em>xs:string</em></description><br>
+<span class="style5"> </span><span class="style2"><span class="style5"><em> </em>
+</span><<span class="style5">bitOffset><em>scaledNonNegativeInteger</</em>bitOffset>
+</span><<span class="style5">bitWidth><em>scaledNonNegativeInteger</em></bitWidth><br>
+ </span><span class="style6">or</span><span class="style5"><br>
+ <lsb>scaledNonNegativeInteger</lsb> <msb>scaledNonNegativeInteger</msb><br>
+ </span><span class="style6">or</span><span class="style5"><br>
+ <bitRange><em>pattern</em></bitRange><br>
+ <access><em>accessType</em></access><br>
+</span></span><span class="style4"> <modifiedWriteValues><em>writeValueType</em></modifiedWriteValues><br>
+ <writeConstraint><em>writeConstraintType</em></writeConstraint><br>
+ <readAction><em>readActionType</em> </readAction></span><span class="style2"><br>
+ </span> <span class="style4"><enumeratedValues><br>
+ ...<br>
+ </enumeratedValues></span></p>
+<h4></field></h4>
+<p>A bit-field has a name that is unique for the register it belongs to. The
+position and size within the register is either described by the combination of
+the least significant bit's position (lsb) and the most significant bit's
+position (msb) or the lsb and the size, specifying the bit-width of the
+field. A field may define an enumeratedValue in order to make the display
+more intuitive to read. </p>
+<h4>Mandatory items:</h4>
+<p><strong>name = </strong>name string used to identify the field. Field names
+are required to be unique within the scope of a register.<br>
+</p>
+<p><strong>description = </strong>string describing the details of the register.<br>
+</p>
+<p>There are 3 ways to describe a field to be used mutually exclusive:<br>
+a) specifying bitOffset and bitWidth (IP-XACT like)<br>
+b) specifying lsb and msb of the field.<br>
+c) specifying a bit range in the format "[<msb>:<lsb>]"</p>
+<p><strong>bitOffset = </strong>value defining the position of the least significant bit
+of the field within the register it belongs to.<br>
+<strong>bitWidth = </strong>value defining the bit-width of the bitfield within the
+register it belongs to.<br>
+</p>
+<p>
+<strong>lsb =</strong> value defining the bit position of the least significant
+bit within the register it belongs to.<br>
+<strong>msb =</strong> value defining the bit position of the most significant
+bit within the register it belongs to.
+</p>
+<p><strong>bitRange = </strong>a string in the format: [<msb>:<lsb>]<br>
+</p>
+<h4>Optional items:</h4>
+<p><strong>derivedFrom = </strong>the field is cloned
+from a previously defined field with a unique name.</p>
+<p><strong>access =</strong> predefined strings defining the allowed
+accesses for this register: <em>read-only, write-only, read-write, writeOnce,
+read-writeOnce</em><strong>.</strong> Can be omitted if it matches the access permission set for the parent register.</p>
+<p><strong>enumeratedValues = </strong>next lower level of description (see next section
+for details)</p>
+<p><strong>modifiedWriteValues = </strong>element to describe the manipulation of
+data written to a field. If not specified the value written to the field is the
+value stored in the field. The other options are bitwise operations: <br>
+ <em>oneToClear:</em> write data bit of one shall clear (set to zero) the
+corresponding bit in the field<br>
+ <em>oneToSet:</em> write data bit of one shall set (set to one) the corresponding
+bit in the field<br>
+ <em>oneToToggle:</em> write data bit of one shall toggle (invert) the
+corresponding bit in the field<br>
+ <em>zeroToClear:</em> write data bit of zero shall clear (set to zero) the
+corresponding bit in the field<br>
+ <em>zeroToSet:</em> write data bit of zero shall set (set to one) the
+corresponding bit in the field<br>
+ <em>zeroToToggle:</em> write data bit of zero shall toggle (invert) the
+corresponding bit in the field<br>
+ <em>clear:</em> after a write operation all bits in the field are cleared (set to
+zero)<br>
+ <em>set:</em> after a write operation all bits in the field are set (set to one)<br>
+ <em>modify:</em> after a write operation all bit in the field may be modified
+(default)</p>
+<p><strong>writeConstraint: </strong>has a set of options:<br>
+ <em>writeAsRead</em> = if true only the last read value can be written<br>
+ <em>useEnumeratedValues</em> = if true only those values listed in the
+enumeratedValues list are considered valid write values<br>
+ <em>minimum</em> = specifies the smallest number to be written to the field<br>
+ <em>maximum</em> = specifies the largest number to be written to the field</p>
+<p><strong>readAction: </strong>if set it specifies the side effect following
+read operations. If not set the field is not modified following a read
+operations. The defined side effects are:<br>
+ <em>clear:</em> indicates that the field is cleared (set to zero)
+following a read operation<br>
+ <em>set:</em> indicates that the field is set (set to ones) following a
+read operation<br>
+ <em>modify</em>: indicates that the field is modified in some way after a
+read operation
+<br>
+ <em>modifyExternal: </em>indicates that one or more dependent resources
+other than this field are immediately affected by a read (it is recommended that
+the field description specifies these dependencies). Debuggers are not expected
+to read the field unless explicitly instructed by user.</p>
+<h4>Example:</h4>
+<pre>...
+ <field>
+ <name>TimerCtrl0_IntSel</name>
+ <description>Select interrupt line t<span class="style8">hat is triggered by timer overflow</span>.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>3</bitWidth>
+ <access>read-write</access>
+ <resetValue>0x0</resetValue>
+ <modifiedWriteValues>oneToSet</modifiedWriteValues>
+ <writeConstraint>
+ <range>
+ <minimum>0</minimum>
+ <maximum>5</maximum>
+ </range>
+ </writeConstraint>
+ <readAction>clear</readAction>
+
+ <enumeratedValues>
+ ...
+ </enumeratedValues>
+ </field>
+...</pre>
+<hr>
+<h4 class="style3"><enumeratedValues <span class="style2">
+<span class="style4">derivedFrom=</span><em>"<span class="style4">xs:Name"</span></em></span>></h4>
+<p> <span class="style2"><span class="style4"> <name><em>xs:Name</em></name</span></span>><span class="style4"><br>
+ <usage><em>usageType</em></usage></span><br>
+ <enumeratedValue><br>
+ ...<br>
+ </enumeratedValue></p>
+<p> ... </p>
+<p> <enumeratedValue><br>
+ ...<br>
+ </enumeratedValue></p>
+<h4></enumeratedValues></h4>
+<p>An enumerated value provides one or more enumeration items (enumeratedValue), defining a map
+between all possible values of the bit-field it belongs to and the corresponding
+human readable semantics of that value.</p>
+<p>Mandatory items:<br>
+<strong>enumeratedValue = </strong>next lower level of description (see next section
+for details)</p>
+<p>Optional items:<br>
+<strong>derivedFrom = </strong>the enumeratedValues can be copied or derived
+from a previously defined enumeratedValue that has been given a unique name.<br>
+<strong>name =</strong> name string to identify an enumeratedValue. Named
+enumeratedValues need to be unique in the scope of a device in order to be reusable
+throughout the description of a device.<br>
+<strong>usage = </strong>possible values are <strong>read, write </strong>or
+<strong>read-write.</strong> This allows to specify two different enumerated values
+depending whether it is to be used for a read or a write access. If not specified the enueratedValues are valid for read and write.</p>
+<h4>Example:</h4>
+<pre>...
+ <enumeratedValues>
+ <name>TimerIntSelect</name>
+ <usage>read-write</usage>
+ <enumeratedValue>
+ <name>disabled</name>
+ <description>disabled bit</description>
+ <value>0</value>
+ </enumeratedValue>
+ ...
+ <enumeratedValue>
+ <name>reserved</name>
+ <description>reserved values. Do not use</description>
+ <isDefault>true</isDefault>
+ </enumeratedValue>
+ </enumeratedValues>
+...</pre>
+<hr>
+<h4><enumeratedValue></h4>
+<p> <name<em>>xs:name</em></name><br>
+ <span class="style10"><span class="style4"><description>xs:<em>string</em></description></span><br>
+</span><em> <</em>value<span class="style2">><em>scaledNonNegativeInteger</em></value><em><br>
+
+</em>or<em><br>
+ <</em>isDefault><em>xs:boolean</em></isDefault><em><br>
+</em></span></p>
+<h4></enumeratedValue></h4>
+<p>An enumeratedValue defines a map between a value and the string reading the
+corresponding human readable semantics for that value in a brief and a detailed
+version</p>
+<h4>Mandatory items:</h4>
+<p><strong>name=</strong> brief string verbally describing the semantics of the value
+defined for this enumeratedValue. E.g. used for display in visualization of a bit-field
+instead of the value.</p>
+<p>
+<strong>value = </strong>defines the constant of the bit-field that the name
+corresponds to<strong>.</strong></p>
+<p><strong>isDefault = </strong>defines the name and description for all other
+values that are not explicitly listed</p>
+<h4>Optional item:</h4>
+<p><strong>description = </strong>extended string verbally describing the semantics
+of the value defined for this enumeratedValue in full detail.</p>
+<h4>Example:</h4>
+<pre>...
+ <enumeratedValue>
+ <name>disabled</name>
+ <description>Timer does not generate interrupts</description>
+ <value>0</value>
+ </enumeratedValue>
+ ...
+ <enumeratedValue>
+ <name>enabled</name>
+ <description>Timer does not generate interrupts</description>
+ <isDefault>true</isDefault>
+ </enumeratedValue>
+
+...</pre>
+<hr>
+<h4>Names</h4>
+<p>Names shall comply with ANSI C variable naming restrictions.</p>
+<h4>Constants</h4>
+<p>Number constants shall be entered in hexadecimal, decimal or binary format.</p>
+<ul>
+ <li>hexadecimal is indicated by a leading "0x"</li>
+ <li>binary format is indicated by a leading "#"</li>
+ <li>all other formats are interpreted as decimal numbers</li>
+ <li>the value tag in enumeratedValue accepts do not care bits
+ represented by "x"</li>
+</ul>
+<h4><b>Comments</b> </h4>
+<p>Comments have the standard XML format <strong>"<!--"</strong> starts a comment
+ <strong><span class="style2">"-->"</span></strong> terminates a comment</p>
+<h2>Example</h2>
+<pre>
+<?xml version="1.0" encoding="utf-8"?>
+
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd" >
+ <name>Cortex_M3_Sample</name>
+ <version>0.1</version>
+ <description>ARM Cortex-M3 based Microcontroller dummy device</description>
+ <!-- Bus Interface Properties -->
+ <!-- Cortex-M3 is byte addressable -->
+ <addressUnitBits>8</addressUnitBits>
+ <!-- the maximum data bit width accessible within a single transfer is 32bits -->
+ <width>32</width>
+
+ <!-- Register Default Properties -->
+ <!-- the size of the registers is set to a bit width of 32. This can be overruled for individual peripherals and/or registers -->
+ <size>32</size>
+ <!-- the access to all registers is set to be readable and writeable. This can be overruled for individual peripherals and/or registers -->
+ <access>read-write</access>
+ <!-- for demonstration purposes the resetValue for all registers of the device is set to be 0. This can be overruled within the description -->
+ <resetValue>0</resetValue>
+ <!-- the resetMask = 0 specifies that by default no register of this device has a defined reset value -->
+ <resetMask>0</resetMask>
+
+ <peripherals>
+ <peripheral>
+ <name>Timer0</name>
+ <description>A simple 16 bit timer counting down ... </description>
+ <groupName>Timer</groupName>
+ <baseAddress>0x40000000</baseAddress>
+ <!-- the first addressBlock is occupied by registers. The second block is reserved -> no access permission -->
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x8</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <addressBlock>
+ <offset>0x8</offset>
+ <size>0x3f8</size>
+ <usage>reserved</usage>
+ </addressBlock>
+ <interrupt>
+ <name>TIM0_IRQn</name>
+ <value>34</value>
+ </interrupt>
+ <registers>
+ <register>
+ <name>TimerCtrl0</name>
+ <!-- the display name is an unrestricted string. -->
+ <displayName>Timer Ctrl 0</displayName>
+ <description>Timer Control Register</description>
+ <addressOffset>0x0</addressOffset>
+ <!-- size=32, access=read-write, resetValue=0x0, resetMask=0xffffffff, volatile=false -->
+ <fields>
+ <field>
+ <name>TimerCtrl0_En</name>
+ <description>Enable Bit activates the timer.</description>
+ <!-- Spirit like bit range description: [0:0] -->
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <!-- Writing 1 enables, writing 0 has no effect -->
+ <modifiedWriteValues>oneToSet</modifiedWriteValues>
+ <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+ <writeConstraint>
+ <useEnumeratedValues>true</useEnumeratedValues>
+ </writeConstraint>
+ <!-- there is no side effect on reads, therefore <readAction> is not set -->
+ <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+ <enumeratedValues>
+ <name>oneBitEnable</name>
+ <!-- the same enumerated Values are used for read and write. This default is assumed when this tag is missing -->
+ <usage>read-write</usage>
+ <enumeratedValue>
+ <name>enabled</name>
+ <description>Timer is enabled and active</description>
+ <value>0x0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>disabled</name>
+ <description>Timer is disabled and inactive</description>
+ <value>0x1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>TimerCtrl0_Dis</name>
+ <description>Disable Bit deactivates the timer.</description>
+ <!-- Spirit like bit range description: [1:1] -->
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <!-- Writing 1 sets, writing 0 has no effect -->
+ <modifiedWriteValues>oneToSet</modifiedWriteValues>
+ <!-- The write constraint is defined to be that only the values provided by the enumeratedValues below are allowed -->
+ <writeConstraint>
+ <useEnumeratedValues>true</useEnumeratedValues>
+ </writeConstraint>
+ <!-- there is no side effect on reads, therefore <readAction> is not set -->
+ <!-- oneBitEnable named enumeration that can be reused in other parts of the description -->
+ <enumeratedValues derivedFrom="oneBitEnable"></enumeratedValues>
+ </field>
+ <field>
+ <name>TimerCtrl0_Int</name>
+ <description>Select interrupt line that is triggered by timer overflow.</description>
+ <!-- the position of the bit field is described in the bitRange style. -->
+ <bitRange>[4:2]</bitRange>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>disabled</name>
+ <description>Timer does not generate interrupts</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>int 0</name>
+ <description>Timer does generate interrupts on interrupt line 0</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>int 1</name>
+ <description>Timer does generate interrupts on interrupt line 1</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>int 2</name>
+ <description>Timer does generate interrupts on interrupt line 2</description>
+ <value>3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>int 3</name>
+ <description>Timer does generate interrupts on interrupt line 3</description>
+ <value>4</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>int 4</name>
+ <description>Timer does generate interrupts on interrupt line 4</description>
+ <value>5</value>
+ </enumeratedValue>
+ <!-- this is the default element. All the valid value not listed above (6,7) have the following name and description -->
+ <enumeratedValue>
+ <name>reserved</name>
+ <description>Timer is configured incorrectly and the functionality is considered unpredictable</description>
+ <isDefault>true</isDefault>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>TimerCounter0</name>
+ <description>Timer0 16 Bit Counter Register</description>
+ <addressOffset>0x4</addressOffset>
+ <size>16</size>
+ </register>
+ <!-- a copy of the counter register TimerCounter0 with the name="TimerCounter1" and the addressOffset="0x8" -->
+ <register derivedFrom="TimerCounter0">
+ <name>TimerCounter1</name>
+ <addressOffset>0x6</addressOffset>
+ </register>
+ <!-- ... this is a restricted demo example and a real timer peripheral would have more register to be complete -->
+ </registers>
+ </peripheral>
+ <!-- a copy of Timer0 with the name="Timer1 and the baseAddress="0x40000400" -->
+ <peripheral derivedFrom="Timer0">
+ <name>Timer1</name>
+ <baseAddress>0x40000400</baseAddress>
+ <interrupt>
+ <name>TIM1_IRQn</name>
+ <value>35</value>
+ </interrupt>
+ </peripheral>
+ </peripherals>
+</device></pre>
+
+<h2><a name="6"></a>Questions & Answers</h2>
+<h3>Is there any relation between the System View Description and the CMSIS
+standard?</h3>
+<p>Initiallly there was no immediate link but both initiatives had a common goal:
+Create a sound software development eco-system for Cortex-M based
+Microcontroller, giving the customers the free choice of devices and software
+development environments and all resources required for a successful product
+development in a single location. Meanwhile we have started to generate
+CMSIS compliant device header files from the same CMSIS-SVD description. We will
+introduce a small number of additional description tags in the next version of
+the specification. The benefit is the synchronization between symbols used in
+the application and the symbols displayed by the debugger. </p>
+<h3>Why does the format not provide constructs like macros and
+conditional statements?</h3>
+<p>It is assumed that the description is generated from other sources and
+therefore such concepts would only complicate the language unnecessarily. It is
+recommended to use a standard C pre-processor to generate the debug description
+format from a redundancy optimized description.</p>
+<h3>Do we need to consider endianess in the description?</h3>
+<p>This should be specified on a device configuration level and is not specific
+to the visualization of peripheral details in a System View. Endianess becomes
+relevant when using bit fields in the CMSIS compliant device header file.</p>
+<h3>Is the System View Description limited to Cortex-M based devices ?</h3>
+
+
+<p>There may have been assumptions made about the structure of the device due to
+it being developed around a Cortex-M processor. E.g. that all peripherals are
+assumed to be memory mapped and to reside in a single address space. It is quite
+likely that the description format may also serve other architectures
+sufficiently. There is no intent to limit the format to Cortex-M
+processor based devices. </p>
+
+
+</body></html>
\ No newline at end of file
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cm3.h b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cm3.h
new file mode 100644
index 00000000..c15e10ae
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cm3.h
@@ -0,0 +1,1236 @@
+/**************************************************************************//**
+ * @file core_cm3.h
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version V2.10
+ * @date 19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+ This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+ It consists of:
+
+ - Cortex-M Core Register Definitions
+ - Cortex-M functions
+ - Cortex-M instructions
+
+ The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+ access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
+ CMSIS violates following MISRA-C2004 Rules:
+
+ - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+ This file defines all structures and symbols for CMSIS core:
+ - CMSIS version number
+ - Cortex-M core
+ - Cortex-M core Revision Number
+ @{
+ */
+
+/* CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED 0
+
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #endif
+
+#elif defined ( __TASKING__ )
+ /* add preprocessor checks */
+#endif
+
+#include <stdint.h> /*!< standard types definitions */
+#include "core_cmInstr.h" /*!< Core Instruction Access */
+#include "core_cmFunc.h" /*!< Core Function Access */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM3_REV
+ #define __CM3_REV 0x0200
+ #warning "__CM3_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+ #define __I volatile /*!< defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< defines 'read only' permissions */
+#endif
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+*/
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE CMSIS Core
+ Type definitions for the Cortex-M Core Registers
+ @{
+ */
+
+/** \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
+#else
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+#endif
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+#if (__CORTEX_M != 0x04)
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
+#else
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+#endif
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+
+/** \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC CMSIS NVIC
+ Type definitions for the Cortex-M NVIC Registers
+ @{
+ */
+
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB CMSIS SCB
+ Type definitions for the Cortex-M System Control Block Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5];
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+ Type definitions for the Cortex-M System Control and ID Register not in the SCB
+ @{
+ */
+
+/** \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1];
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+#else
+ uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick CMSIS SysTick
+ Type definitions for the Cortex-M System Timer Registers
+ @{
+ */
+
+/** \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM CMSIS ITM
+ Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU CMSIS MPU
+ Type definitions for the Cortex-M Memory Protection Unit (MPU)
+ @{
+ */
+
+/** \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug CMSIS Core Debug
+ Type definitions for the Cortex-M Core Debug Registers
+ @{
+ */
+
+/** \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup CMSIS_core_register
+ @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+ @{
+ */
+
+/** \brief Set Priority Grouping
+
+ This function sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+ \param [in] PriorityGroup Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/** \brief Get Priority Grouping
+
+ This function gets the priority grouping from NVIC Interrupt Controller.
+ Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+ \return Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
+}
+
+
+/** \brief Enable External Interrupt
+
+ This function enables a device specific interrupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief Disable External Interrupt
+
+ This function disables a device specific interrupt in the NVIC interrupt controller.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief Get Pending Interrupt
+
+ This function reads the pending register in the NVIC and returns the pending bit
+ for the specified interrupt.
+
+ \param [in] IRQn Number of the interrupt for get pending
+ \return 0 Interrupt status is not pending
+ \return 1 Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief Set Pending Interrupt
+
+ This function sets the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief Clear Pending Interrupt
+
+ This function clears the pending bit for the specified interrupt.
+ The interrupt number cannot be a negative value.
+
+ \param [in] IRQn Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief Get Active Interrupt
+
+ This function reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Number of the interrupt for get active
+ \return 0 Interrupt status is not active
+ \return 1 Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief Set Interrupt Priority
+
+ This function sets the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ Note: The priority cannot be set for every core interrupt.
+
+ \param [in] IRQn Number of the interrupt for set priority
+ \param [in] priority Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
+ else {
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+
+/** \brief Get Interrupt Priority
+
+ This function reads the priority for the specified interrupt. The interrupt
+ number can be positive to specify an external (device specific)
+ interrupt, or negative to specify an internal (core) interrupt.
+
+ The returned priority value is automatically aligned to the implemented
+ priority bits of the microcontroller.
+
+ \param [in] IRQn Number of the interrupt for get priority
+ \return Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+/** \brief Encode Priority
+
+ This function encodes the priority for an interrupt with the given priority group,
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The returned priority value can be used for NVIC_SetPriority(...) function
+
+ \param [in] PriorityGroup Used priority group
+ \param [in] PreemptPriority Preemptive priority value (starting from 0)
+ \param [in] SubPriority Sub priority value (starting from 0)
+ \return Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ return (
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
+ );
+}
+
+
+/** \brief Decode Priority
+
+ This function decodes an interrupt priority value with the given priority group to
+ preemptive priority value and sub priority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+ The priority value can be retrieved with NVIC_GetPriority(...) function
+
+ \param [in] Priority Priority value
+ \param [in] PriorityGroup Used priority group
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0)
+ \param [out] pSubPriority Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
+}
+
+
+/** \brief System Reset
+
+ This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+ while(1); /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief System Tick Configuration
+
+ This function initialises the system tick timer and its interrupt and start the system tick timer.
+ Counter is in free running mode to generate periodical interrupts.
+
+ \param [in] ticks Number of ticks between two interrupts
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief ITM Send Character
+
+ This function transmits a character via the ITM channel 0.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \param [in] ch Character to transmit
+ \return Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+
+/** \brief ITM Receive Character
+
+ This function inputs a character via external variable ITM_RxBuffer.
+ It just returns when no debugger is connected that has booked the output.
+ It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+ \return Received character
+ \return -1 No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/** \brief ITM Check Character
+
+ This function checks external variable ITM_RxBuffer whether a character is available or not.
+ It returns '1' if a character is available and '0' if no character is available.
+
+ \return 0 No character available
+ \return 1 Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmFunc.h b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmFunc.h
new file mode 100644
index 00000000..c999b1c8
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V2.10
+ * @date 26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmInstr.h b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmInstr.h
new file mode 100644
index 00000000..ceb4f875
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/core_cmInstr.h
@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V2.10
+ * @date 19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/stm32l1xx.h b/miosix/arch/cortexM3_stm32l1/common/CMSIS/stm32l1xx.h
new file mode 100644
index 00000000..a9de83dd
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/stm32l1xx.h
@@ -0,0 +1,6348 @@
+/**
+ ******************************************************************************
+ * @file stm32l1xx.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 24-January-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
+ * This file contains all the peripheral register's definitions, bits
+ * definitions and memory mapping for STM32L1xx High-, Medium-density
+ * and Medium-density Plus devices.
+ *
+ * The file is the unique include file that the application programmer
+ * is using in the C source code, usually in main.c. This file contains:
+ * - Configuration section that allows to select:
+ * - The device used in the target application
+ * - To use or not the peripheral�s drivers in application code(i.e.
+ * code will be based on direct access to peripheral�s registers
+ * rather than drivers API), this option is controlled by
+ * "#define USE_STDPERIPH_DRIVER"
+ * - To change few application-specific parameters such as the HSE
+ * crystal frequency
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral�s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+ *
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx
+ * @{
+ */
+
+#ifndef __STM32L1XX_H
+#define __STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup Library_configuration_section
+ * @{
+ */
+
+/* Uncomment the line below according to the target STM32L device used in your
+ application
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ /* #define STM32L1XX_MD */ /*!< STM32L1XX_MD: STM32L Ultra Low Power Medium-density devices */
+ /* #define STM32L1XX_MDP */ /*!< STM32L1XX_MDP: STM32L Ultra Low Power Medium-density Plus devices */
+ #define STM32L1XX_HD /*!< STM32L1XX_HD: STM32L Ultra Low Power High-density devices */
+#endif
+/* Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor.
+
+ - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx
+ microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
+ - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and
+ STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes.
+ - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx
+ microcontrollers where the Flash memory density is 384 Kbytes.
+ */
+
+#if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD)
+ #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
+#endif
+
+#if !defined USE_STDPERIPH_DRIVER
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
+ */
+ /*#define USE_STDPERIPH_DRIVER*/
+#endif
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+ used in your application
+
+ Tip: To avoid modifying this file each time you need to use different HSE, you
+ can define the HSE value in your toolchain compiler preprocessor.
+ */
+#if !defined (HSE_VALUE)
+#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ Timeout value
+ */
+#if !defined (HSE_STARTUP_TIMEOUT)
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
+#endif
+
+/**
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ Timeout value
+ */
+#if !defined (HSI_STARTUP_TIMEOUT)
+#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */
+#endif
+
+#if !defined (HSI_VALUE)
+#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSI_VALUE)
+#define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature. */
+#endif
+
+#if !defined (LSE_VALUE)
+#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
+#endif
+
+/**
+ * @brief STM32L1xx Standard Peripheral Library version number V1.1.0
+ */
+#define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
+#define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
+ |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
+ |(__STM32L1XX_STDPERIPH_VERSION_RC))
+
+/**
+ * @}
+ */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief STM32L1xx Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+#define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
+#define __MPU_PRESENT 1 /*!< STM32L provides MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*!< Interrupt Number Definition */
+typedef enum IRQn
+{
+/****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
+ SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
+
+/****** STM32L specific Interrupt Numbers ***********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
+ TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
+ USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
+ DAC_IRQn = 21, /*!< DAC Interrupt */
+ COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ LCD_IRQn = 24, /*!< LCD Interrupt */
+ TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
+ TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
+ TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
+ USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
+ TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
+#ifdef STM32L1XX_MD
+ TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
+#endif
+
+#ifdef STM32L1XX_MDP
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif
+
+#ifdef STM32L1XX_HD
+ TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
+ SDIO_IRQn = 45, /*!< SDIO global Interrupt */
+ TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
+ SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
+ UART4_IRQn = 48, /*!< UART4 global Interrupt */
+ UART5_IRQn = 49, /*!< UART5 global Interrupt */
+ DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
+ AES_IRQn = 55, /*!< AES global Interrupt */
+ COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
+#endif
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm3.h"
+#include "system_stm32l1xx.h"
+#include <stdint.h>
+
+/** @addtogroup Exported_types
+ * @{
+ */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+ * @brief __RAM_FUNC definition
+ */
+#if defined ( __CC_ARM )
+/* ARM Compiler
+ ------------
+ RAM functions are defined using the toolchain options.
+ Functions that are executed in RAM should reside in a separate source
+ module. Using the 'Options for File' dialog you can simply change the
+ 'Code / Const' area of a module to a memory space in physical RAM.
+ Available memory areas are declared in the 'Target' tab of the
+ 'Options for Target' dialog.
+*/
+ #define __RAM_FUNC FLASH_Status
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+ ---------------
+ RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+ #define __RAM_FUNC __ramfunc FLASH_Status
+
+#elif defined ( __GNUC__ )
+/* GNU Compiler
+ ------------
+ RAM functions are defined using a specific toolchain attribute
+ "__attribute__((section(".data")))".
+*/
+ #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
+
+#elif defined ( __TASKING__ )
+/* TASKING Compiler
+ ----------------
+ RAM functions are defined using a specific toolchain pragma. This pragma is
+ defined in the stm32l1xx_flash_ramfunc.c
+*/
+ #define __RAM_FUNC FLASH_Status
+
+#endif
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
+ __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
+ __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
+} ADC_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief AES hardware accelerator
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
+} AES_TypeDef;
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+} CRC_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+} DAC_TypeDef;
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */
+ __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */
+ __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */
+ __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
+ __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */
+ __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
+ __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
+ __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
+ __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
+ __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
+ __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
+ __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
+ __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
+ uint32_t RESERVED[23]; /*!< Reserved, 0x24 */
+ __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */
+ __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */
+} FLASH_TypeDef;
+
+/**
+ * @brief Option Bytes Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
+ __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
+ __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
+ __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
+ __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
+ __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
+ __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
+ __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
+} OB_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
+} FSMC_Bank1_TypeDef;
+
+/**
+ * @brief Flexible Static Memory Controller Bank1E
+ */
+
+typedef struct
+{
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/**
+ * @brief General Purpose IO
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ uint16_t RESERVED0; /*!< Reserved, 0x06 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ uint16_t RESERVED1; /*!< Reserved, 0x12 */
+ __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ uint16_t RESERVED2; /*!< Reserved, 0x16 */
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
+ __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
+ uint16_t RESERVED3; /*!< Reserved, 0x2A */
+} GPIO_TypeDef;
+
+/**
+ * @brief SysTem Configuration
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+} SYSCFG_TypeDef;
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/**
+ * @brief LCD
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
+ __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
+ __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
+ __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
+} LCD_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
+ __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
+ __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
+ __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
+ __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
+ __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
+} RCC_TypeDef;
+
+/**
+ * @brief Routing Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
+ __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
+ __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
+ __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
+ __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
+ __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
+ __IO uint32_t HYSCR4; /*!< RI Hysteresis control register, Address offset: 0x18 */
+} RI_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
+} RTC_TypeDef;
+
+/**
+ * @brief SD host Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+} SPI_TypeDef;
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ uint16_t RESERVED10; /*!< Reserved, 0x2A */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ uint32_t RESERVED12; /*!< Reserved, 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ uint32_t RESERVED17; /*!< Reserved, 0x44 */
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ uint16_t RESERVED18; /*!< Reserved, 0x4A */
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ uint16_t RESERVED19; /*!< Reserved, 0x4E */
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
+ uint16_t RESERVED20; /*!< Reserved, 0x52 */
+} TIM_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */
+} USART_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define LCD_BASE (APB1PERIPH_BASE + 0x2400)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
+#define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
+#define RI_BASE (APB1PERIPH_BASE + 0x7C04)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
+
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
+#define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
+#define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
+#define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
+#define ADC_BASE (APB2PERIPH_BASE + 0x2700)
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
+
+#define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
+#define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
+#define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
+#define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
+#define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
+#define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
+#define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
+#define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define RCC_BASE (AHBPERIPH_BASE + 0x3800)
+
+
+#define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
+#define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
+
+#define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
+
+#define DMA2_BASE (AHBPERIPH_BASE + 0x6400)
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
+
+#define AES_BASE ((uint32_t)0x50060000)
+
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
+
+#define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define LCD ((LCD_TypeDef *) LCD_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define UART4 ((USART_TypeDef *) UART4_BASE)
+#define UART5 ((USART_TypeDef *) UART5_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC_BASE)
+#define COMP ((COMP_TypeDef *) COMP_BASE)
+#define RI ((RI_TypeDef *) RI_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
+
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define OB ((OB_TypeDef *) OB_BASE)
+
+#define AES ((AES_TypeDef *) AES_BASE)
+
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers Bits Definition */
+/******************************************************************************/
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter (ADC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for ADC_SR register ********************/
+#define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
+#define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
+#define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
+#define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
+#define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
+#define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
+#define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
+#define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
+#define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
+
+/******************* Bit definition for ADC_CR1 register ********************/
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
+
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
+#define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
+
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
+
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
+
+/******************* Bit definition for ADC_CR2 register ********************/
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
+#define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
+
+#define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
+#define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
+
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
+
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
+
+/****************** Bit definition for ADC_SMPR1 register *******************/
+#define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
+#define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
+#define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
+#define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
+#define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
+#define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
+#define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
+#define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
+#define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
+#define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
+#define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR2 register *******************/
+#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
+#define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_SMPR3 register *******************/
+#define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+#define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
+#define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
+#define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
+#define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
+#define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
+
+/****************** Bit definition for ADC_JOFR1 register *******************/
+#define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
+
+/****************** Bit definition for ADC_JOFR2 register *******************/
+#define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
+
+/****************** Bit definition for ADC_JOFR3 register *******************/
+#define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
+
+/****************** Bit definition for ADC_JOFR4 register *******************/
+#define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
+
+/******************* Bit definition for ADC_HTR register ********************/
+#define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
+
+/******************* Bit definition for ADC_LTR register ********************/
+#define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
+
+/******************* Bit definition for ADC_SQR1 register *******************/
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
+#define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
+#define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
+#define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
+#define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR2 register *******************/
+#define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
+#define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
+#define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
+#define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
+#define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
+#define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
+#define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR3 register *******************/
+#define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
+#define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
+#define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR4 register *******************/
+#define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+/******************* Bit definition for ADC_SQR5 register *******************/
+#define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+#define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
+
+#define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
+#define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
+#define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
+#define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
+
+
+/******************* Bit definition for ADC_JSQR register *******************/
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
+
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+
+/******************* Bit definition for ADC_JDR1 register *******************/
+#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR2 register *******************/
+#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR3 register *******************/
+#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************* Bit definition for ADC_JDR4 register *******************/
+#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
+
+/****************** Bit definition for ADC_SMPR0 register *******************/
+#define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
+#define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+
+#define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
+#define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+#define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
+
+/******************* Bit definition for ADC_CSR register ********************/
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
+#define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
+
+/******************* Bit definition for ADC_CCR register ********************/
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
+
+/******************************************************************************/
+/* */
+/* Advanced Encryption Standard (AES) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for AES_CR register *********************/
+#define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */
+#define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */
+#define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */
+#define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */
+
+#define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */
+#define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */
+#define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */
+
+#define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */
+#define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */
+#define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */
+
+#define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */
+#define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */
+#define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */
+#define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
+#define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */
+#define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */
+
+/******************* Bit definition for AES_SR register *********************/
+#define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */
+#define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */
+#define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */
+
+/******************* Bit definition for AES_DINR register *******************/
+#define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */
+
+/******************* Bit definition for AES_DOUTR register ******************/
+#define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */
+
+/******************* Bit definition for AES_KEYR0 register ******************/
+#define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */
+
+/******************* Bit definition for AES_KEYR1 register ******************/
+#define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */
+
+/******************* Bit definition for AES_KEYR2 register ******************/
+#define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */
+
+/******************* Bit definition for AES_KEYR3 register ******************/
+#define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */
+
+/******************* Bit definition for AES_IVR0 register *******************/
+#define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */
+
+/******************* Bit definition for AES_IVR1 register *******************/
+#define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */
+
+/******************* Bit definition for AES_IVR2 register *******************/
+#define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */
+
+/******************* Bit definition for AES_IVR3 register *******************/
+#define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */
+
+/******************************************************************************/
+/* */
+/* Analog Comparators (COMP) */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for COMP_CSR register ********************/
+#define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
+#define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
+#define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
+#define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
+
+#define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
+#define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
+#define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
+
+#define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
+#define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
+
+#define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
+#define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
+
+#define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
+#define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+
+#define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
+#define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
+#define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
+#define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
+
+#define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
+#define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
+#define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
+
+#define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
+#define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
+#define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
+
+/******************************************************************************/
+/* */
+/* Operational Amplifier (OPAMP) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for OPAMP_CSR register ******************/
+#define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
+#define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
+#define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
+#define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
+#define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
+#define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
+#define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
+#define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
+#define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
+#define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
+#define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
+#define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
+#define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */
+#define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */
+#define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */
+#define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */
+#define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */
+#define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */
+#define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */
+#define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */
+#define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
+#define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
+#define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */
+#define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
+#define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
+#define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
+#define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
+#define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */
+
+/******************* Bit definition for OPAMP_OTR register ******************/
+#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */
+#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */
+#define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
+
+/******************* Bit definition for OPAMP_LPOTR register ****************/
+#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */
+#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */
+#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */
+
+/******************************************************************************/
+/* */
+/* CRC calculation unit (CRC) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for CRC_DR register *********************/
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
+
+/******************* Bit definition for CRC_IDR register ********************/
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
+
+/******************** Bit definition for CRC_CR register ********************/
+#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
+
+/******************************************************************************/
+/* */
+/* Digital to Analog Converter (DAC) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for DAC_CR register ********************/
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
+
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
+
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable */
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
+
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
+
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
+
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
+/***************** Bit definition for DAC_SWTRIGR register ******************/
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
+
+/***************** Bit definition for DAC_DHR12R1 register ******************/
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L1 register ******************/
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R1 register ******************/
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12R2 register ******************/
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12L2 register ******************/
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8R2 register ******************/
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12RD register ******************/
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
+
+/***************** Bit definition for DAC_DHR12LD register ******************/
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
+
+/****************** Bit definition for DAC_DHR8RD register ******************/
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
+
+/******************* Bit definition for DAC_DOR1 register *******************/
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
+
+/******************* Bit definition for DAC_DOR2 register *******************/
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
+
+/******************** Bit definition for DAC_SR register ********************/
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/* */
+/* Debug MCU (DBGMCU) */
+/* */
+/******************************************************************************/
+
+/**************** Bit definition for DBGMCU_IDCODE register *****************/
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
+
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
+#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/****************** Bit definition for DBGMCU_CR register *******************/
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
+
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
+
+/****************** Bit definition for DBGMCU_APB1_FZ register **************/
+
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
+
+/****************** Bit definition for DBGMCU_APB2_FZ register **************/
+
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
+
+/******************************************************************************/
+/* */
+/* DMA Controller (DMA) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for DMA_ISR register ********************/
+#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
+#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
+#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
+#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
+#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
+#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
+#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
+#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
+#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
+#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
+#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
+#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
+#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
+#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
+#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
+#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
+#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
+#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
+#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
+#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
+#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
+#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
+#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
+#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
+#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
+#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
+#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
+#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
+
+/******************* Bit definition for DMA_IFCR register *******************/
+#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
+#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
+#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
+#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
+#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
+#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
+#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
+#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
+#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
+#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
+#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
+#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
+#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
+#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
+#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
+#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
+#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
+#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
+#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
+#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
+#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
+#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
+#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
+#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
+#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
+#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
+#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
+#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
+
+/******************* Bit definition for DMA_CCR1 register *******************/
+#define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
+#define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
+#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR2 register *******************/
+#define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
+#define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR3 register *******************/
+#define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/*!<****************** Bit definition for DMA_CCR4 register *******************/
+#define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/****************** Bit definition for DMA_CCR5 register *******************/
+#define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/******************* Bit definition for DMA_CCR6 register *******************/
+#define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
+
+/******************* Bit definition for DMA_CCR7 register *******************/
+#define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
+#define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
+#define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
+#define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
+#define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
+#define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
+#define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
+#define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
+
+#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
+#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
+
+#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
+#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
+
+#define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
+#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
+
+/****************** Bit definition for DMA_CNDTR1 register ******************/
+#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR2 register ******************/
+#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR3 register ******************/
+#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR4 register ******************/
+#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR5 register ******************/
+#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR6 register ******************/
+#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CNDTR7 register ******************/
+#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
+
+/****************** Bit definition for DMA_CPAR1 register *******************/
+#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR2 register *******************/
+#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR3 register *******************/
+#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR4 register *******************/
+#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR5 register *******************/
+#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CPAR6 register *******************/
+#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+
+/****************** Bit definition for DMA_CPAR7 register *******************/
+#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
+
+/****************** Bit definition for DMA_CMAR1 register *******************/
+#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR2 register *******************/
+#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR3 register *******************/
+#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+
+/****************** Bit definition for DMA_CMAR4 register *******************/
+#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR5 register *******************/
+#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR6 register *******************/
+#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/****************** Bit definition for DMA_CMAR7 register *******************/
+#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
+
+/******************************************************************************/
+/* */
+/* External Interrupt/Event Controller (EXTI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for EXTI_IMR register *******************/
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
+#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
+
+/******************* Bit definition for EXTI_EMR register *******************/
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
+#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
+
+/****************** Bit definition for EXTI_RTSR register *******************/
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
+#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_FTSR register *******************/
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
+#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
+
+/****************** Bit definition for EXTI_SWIER register ******************/
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
+#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
+
+/******************* Bit definition for EXTI_PR register ********************/
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
+#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
+#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
+#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
+#define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
+
+/******************************************************************************/
+/* */
+/* FLASH, DATA EEPROM and Option Bytes Registers */
+/* (FLASH, DATA_EEPROM, OB) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for FLASH_ACR register ******************/
+#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
+#define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
+#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
+#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
+
+/******************* Bit definition for FLASH_PECR register ******************/
+#define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
+#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
+#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
+#define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
+#define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
+#define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
+#define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
+#define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
+#define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
+#define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
+#define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
+#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
+
+/****************** Bit definition for FLASH_PDKEYR register ******************/
+#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PEKEYR register ******************/
+#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
+
+/****************** Bit definition for FLASH_PRGKEYR register ******************/
+#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
+
+/****************** Bit definition for FLASH_OPTKEYR register ******************/
+#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
+
+/****************** Bit definition for FLASH_SR register *******************/
+#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
+#define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
+#define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
+#define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
+
+#define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
+#define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
+#define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
+#define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
+#define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
+
+/****************** Bit definition for FLASH_OBR register *******************/
+#define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) /*!< Read Protection */
+#define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
+#define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
+#define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
+#define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
+#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
+#define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) /*!< BFB2 */
+
+/****************** Bit definition for FLASH_WRPR register ******************/
+#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/****************** Bit definition for FLASH_WRPR1 register *****************/
+#define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+
+/****************** Bit definition for FLASH_WRPR2 register *****************/
+#define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
+/******************************************************************************/
+/* */
+/* Flexible Static Memory Controller */
+/* */
+/******************************************************************************/
+/****************** Bit definition for FSMC_BCR1 register *******************/
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR2 register *******************/
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR3 register *******************/
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BCR4 register *******************/
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
+
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
+
+/****************** Bit definition for FSMC_BTR1 register ******************/
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR2 register *******************/
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************* Bit definition for FSMC_BTR3 register *******************/
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BTR4 register *******************/
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR1 register ******************/
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR2 register ******************/
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR3 register ******************/
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/****************** Bit definition for FSMC_BWTR4 register ******************/
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
+
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+
+/******************************************************************************/
+/* */
+/* General Purpose IOs (GPIO) */
+/* */
+/******************************************************************************/
+/******************* Bit definition for GPIO_MODER register *****************/
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_OTYPER register ****************/
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
+
+/******************* Bit definition for GPIO_OSPEEDR register ***************/
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_PUPDR register *****************/
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
+
+/****************** Bits definition for GPIO_IDR register *******************/
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
+
+/****************** Bits definition for GPIO_ODR register *******************/
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
+
+/******************* Bit definition for GPIO_BSRR register ******************/
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
+
+/******************* Bit definition for GPIO_LCKR register ******************/
+#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
+#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
+#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
+#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
+#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
+#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
+#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
+#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
+#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
+#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
+#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
+#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
+#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
+#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
+#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
+#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
+#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
+
+/******************* Bit definition for GPIO_AFRL register ******************/
+#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
+#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
+#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
+#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
+#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
+#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
+#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
+#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
+
+/******************* Bit definition for GPIO_AFRH register ******************/
+#define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)
+#define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)
+#define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)
+#define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)
+#define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)
+#define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)
+#define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)
+#define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)
+
+/******************************************************************************/
+/* */
+/* Inter-integrated Circuit Interface (I2C) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for I2C_CR1 register ********************/
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
+
+/******************* Bit definition for I2C_CR2 register ********************/
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
+
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
+
+/******************* Bit definition for I2C_OAR1 register *******************/
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
+
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
+
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
+
+/******************* Bit definition for I2C_OAR2 register *******************/
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
+
+/******************** Bit definition for I2C_DR register ********************/
+#define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
+
+/******************* Bit definition for I2C_SR1 register ********************/
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
+
+/******************* Bit definition for I2C_SR2 register ********************/
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
+
+/******************* Bit definition for I2C_CCR register ********************/
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
+
+/****************** Bit definition for I2C_TRISE register *******************/
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/* */
+/* Independent WATCHDOG (IWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for IWDG_KR register ********************/
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
+
+/******************* Bit definition for IWDG_PR register ********************/
+#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
+
+/******************* Bit definition for IWDG_RLR register *******************/
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
+
+/******************* Bit definition for IWDG_SR register ********************/
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
+
+/******************************************************************************/
+/* */
+/* LCD Controller (LCD) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for LCD_CR register *********************/
+#define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
+#define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
+
+#define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
+#define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
+#define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
+#define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
+
+#define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
+#define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
+#define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
+
+#define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
+
+/******************* Bit definition for LCD_FCR register ********************/
+#define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
+#define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
+#define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
+
+#define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
+#define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+
+#define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
+#define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
+#define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
+#define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
+
+#define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
+#define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+
+#define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
+#define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
+#define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
+#define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
+
+#define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
+#define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
+#define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
+
+/******************* Bit definition for LCD_SR register *********************/
+#define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
+#define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
+#define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
+#define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
+#define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
+#define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
+
+/******************* Bit definition for LCD_CLR register ********************/
+#define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
+#define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
+
+/******************* Bit definition for LCD_RAM register ********************/
+#define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
+
+/******************************************************************************/
+/* */
+/* Power Control (PWR) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for PWR_CR register ********************/
+#define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
+#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
+#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
+#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
+#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
+
+#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
+#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
+#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
+
+#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
+#define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */
+#define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */
+
+#define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
+#define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+#define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */
+
+/******************* Bit definition for PWR_CSR register ********************/
+#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
+#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
+#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
+#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
+#define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
+#define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */
+
+#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
+#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
+#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
+
+/******************************************************************************/
+/* */
+/* Reset and Clock Control (RCC) */
+/* */
+/******************************************************************************/
+/******************** Bit definition for RCC_CR register ********************/
+#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
+
+#define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
+#define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
+
+#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
+#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
+
+#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
+#define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
+
+#define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
+#define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
+#define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
+
+/******************** Bit definition for RCC_ICSCR register *****************/
+#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
+#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
+
+#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
+#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
+#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
+#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
+#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
+
+/******************** Bit definition for RCC_CFGR register ******************/
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+
+/*!< SW configuration */
+#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
+
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
+
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
+
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
+
+#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
+
+/*!< PLL entry clock source*/
+#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
+
+#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
+#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
+
+
+#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
+#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
+#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
+#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
+
+/*!< PLLMUL configuration */
+#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
+#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
+#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
+#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
+#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
+#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
+#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
+#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
+#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
+#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
+#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
+
+
+/*!< PLLDIV configuration */
+#define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
+#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
+#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
+#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
+
+
+#define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
+
+/*!< MCO configuration */
+#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
+#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
+#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
+#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
+#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
+#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
+#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
+
+#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
+#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
+#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
+#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
+
+/*!< MCO Prescaler configuration */
+#define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
+#define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
+#define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
+#define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
+#define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
+
+/*!<****************** Bit definition for RCC_CIR register ********************/
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
+#define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
+#define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
+#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
+
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
+#define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
+#define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
+
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
+#define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
+#define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
+#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
+
+
+/***************** Bit definition for RCC_AHBRSTR register ******************/
+#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
+#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
+#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
+#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
+#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
+#define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
+#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */
+#define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */
+#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
+#define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
+#define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
+#define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
+#define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) /*!< AES reset */
+#define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) /*!< FSMC reset */
+
+/***************** Bit definition for RCC_APB2RSTR register *****************/
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
+#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) /*!< SDIO reset */
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
+
+/***************** Bit definition for RCC_APB1RSTR register *****************/
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
+#define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
+#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
+#define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
+
+/****************** Bit definition for RCC_AHBENR register ******************/
+#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
+#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
+#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
+#define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
+#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
+#define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
+#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */
+#define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */
+#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
+#define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
+ the Flash memory is in power down mode) */
+#define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
+#define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
+#define RCC_AHBENR_AESEN ((uint32_t)0x08000000) /*!< AES clock enable */
+#define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) /*!< FSMC clock enable */
+
+
+/****************** Bit definition for RCC_APB2ENR register *****************/
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) /*!< SDIO clock enable */
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
+
+
+/***************** Bit definition for RCC_APB1ENR register ******************/
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
+#define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
+#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
+#define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
+
+/****************** Bit definition for RCC_AHBLPENR register ****************/
+#define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */
+#define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */
+#define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
+#define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
+ (has effect only when the Flash memory is
+ in power down mode) */
+#define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
+#define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
+#define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
+#define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) /*!< AES clock enabled in sleep mode */
+#define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) /*!< FSMC clock enabled in sleep mode */
+
+/****************** Bit definition for RCC_APB2LPENR register ***************/
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) /*!< SDIO clock enabled in sleep mode */
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
+
+/***************** Bit definition for RCC_APB1LPENR register ****************/
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
+#define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
+#define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
+#define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
+
+/******************* Bit definition for RCC_CSR register ********************/
+#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
+
+#define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
+#define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
+#define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
+#define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
+#define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
+
+#define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+/*!< RTC congiguration */
+#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
+#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
+#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
+
+#define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
+#define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
+
+#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
+#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
+#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
+#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
+
+
+/******************************************************************************/
+/* */
+/* Real-Time Clock (RTC) */
+/* */
+/******************************************************************************/
+/******************** Bits definition for RTC_TR register *******************/
+#define RTC_TR_PM ((uint32_t)0x00400000)
+#define RTC_TR_HT ((uint32_t)0x00300000)
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TR_HU ((uint32_t)0x000F0000)
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TR_MNT ((uint32_t)0x00007000)
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TR_MNU ((uint32_t)0x00000F00)
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TR_ST ((uint32_t)0x00000070)
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TR_SU ((uint32_t)0x0000000F)
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_DR register *******************/
+#define RTC_DR_YT ((uint32_t)0x00F00000)
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)
+#define RTC_DR_YU ((uint32_t)0x000F0000)
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)
+#define RTC_DR_WDU ((uint32_t)0x0000E000)
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_DR_MT ((uint32_t)0x00001000)
+#define RTC_DR_MU ((uint32_t)0x00000F00)
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)
+#define RTC_DR_DT ((uint32_t)0x00000030)
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)
+#define RTC_DR_DU ((uint32_t)0x0000000F)
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_CR register *******************/
+#define RTC_CR_COE ((uint32_t)0x00800000)
+#define RTC_CR_OSEL ((uint32_t)0x00600000)
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
+#define RTC_CR_POL ((uint32_t)0x00100000)
+#define RTC_CR_COSEL ((uint32_t)0x00080000)
+#define RTC_CR_BCK ((uint32_t)0x00040000)
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)
+#define RTC_CR_TSIE ((uint32_t)0x00008000)
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
+#define RTC_CR_TSE ((uint32_t)0x00000800)
+#define RTC_CR_WUTE ((uint32_t)0x00000400)
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)
+#define RTC_CR_DCE ((uint32_t)0x00000080)
+#define RTC_CR_FMT ((uint32_t)0x00000040)
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
+
+/******************** Bits definition for RTC_ISR register ******************/
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
+#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
+#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
+#define RTC_ISR_TSF ((uint32_t)0x00000800)
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
+#define RTC_ISR_INIT ((uint32_t)0x00000080)
+#define RTC_ISR_INITF ((uint32_t)0x00000040)
+#define RTC_ISR_RSF ((uint32_t)0x00000020)
+#define RTC_ISR_INITS ((uint32_t)0x00000010)
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_PRER register *****************/
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_WUTR register *****************/
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CALIBR register ***************/
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)
+
+/******************** Bits definition for RTC_ALRMAR register ***************/
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_ALRMBR register ***************/
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_WPR register ******************/
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)
+
+/******************** Bits definition for RTC_SSR register ******************/
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_SHIFTR register ***************/
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
+
+/******************** Bits definition for RTC_TSTR register *****************/
+#define RTC_TSTR_PM ((uint32_t)0x00400000)
+#define RTC_TSTR_HT ((uint32_t)0x00300000)
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
+#define RTC_TSTR_ST ((uint32_t)0x00000070)
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSDR register *****************/
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
+#define RTC_TSDR_MT ((uint32_t)0x00001000)
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
+#define RTC_TSDR_DT ((uint32_t)0x00000030)
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
+
+/******************** Bits definition for RTC_TSSSR register ****************/
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
+
+/******************** Bits definition for RTC_CAL register *****************/
+#define RTC_CALR_CALP ((uint32_t)0x00008000)
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
+
+/******************** Bits definition for RTC_TAFCR register ****************/
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
+#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
+#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
+#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
+#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
+
+/******************** Bits definition for RTC_ALRMASSR register *************/
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_ALRMBSSR register *************/
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
+
+/******************** Bits definition for RTC_BKP0R register ****************/
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP1R register ****************/
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP2R register ****************/
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP3R register ****************/
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP4R register ****************/
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP5R register ****************/
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP6R register ****************/
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP7R register ****************/
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP8R register ****************/
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP9R register ****************/
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP10R register ***************/
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP11R register ***************/
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP12R register ***************/
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP13R register ***************/
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP14R register ***************/
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP15R register ***************/
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP16R register ***************/
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP17R register ***************/
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP18R register ***************/
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP19R register ***************/
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP20R register ***************/
+#define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP21R register ***************/
+#define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP22R register ***************/
+#define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP23R register ***************/
+#define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP24R register ***************/
+#define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP25R register ***************/
+#define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP26R register ***************/
+#define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP27R register ***************/
+#define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP28R register ***************/
+#define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP29R register ***************/
+#define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP30R register ***************/
+#define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
+
+/******************** Bits definition for RTC_BKP31R register ***************/
+#define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
+
+/******************************************************************************/
+/* */
+/* SD host Interface */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for SDIO_POWER register ******************/
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
+
+/****************** Bit definition for SDIO_CLKCR register ******************/
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
+
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
+
+/******************* Bit definition for SDIO_ARG register *******************/
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
+
+/******************* Bit definition for SDIO_CMD register *******************/
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
+
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
+
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
+
+/***************** Bit definition for SDIO_RESPCMD register *****************/
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
+
+/****************** Bit definition for SDIO_RESP0 register ******************/
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP1 register ******************/
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP2 register ******************/
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP3 register ******************/
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_RESP4 register ******************/
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
+
+/****************** Bit definition for SDIO_DTIMER register *****************/
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
+
+/****************** Bit definition for SDIO_DLEN register *******************/
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
+
+/****************** Bit definition for SDIO_DCTRL register ******************/
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
+
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
+
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
+
+/****************** Bit definition for SDIO_DCOUNT register *****************/
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
+
+/****************** Bit definition for SDIO_STA register ********************/
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
+
+/******************* Bit definition for SDIO_ICR register *******************/
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
+
+/****************** Bit definition for SDIO_MASK register *******************/
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
+
+/***************** Bit definition for SDIO_FIFOCNT register *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
+
+/****************** Bit definition for SDIO_FIFO register *******************/
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
+
+/******************************************************************************/
+/* */
+/* Serial Peripheral Interface (SPI) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for SPI_CR1 register ********************/
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
+
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
+
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
+
+/******************* Bit definition for SPI_CR2 register ********************/
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
+#define SPI_CR2_FRF ((uint8_t)0x08) /*!< Frame format */
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
+
+/******************** Bit definition for SPI_SR register ********************/
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
+#define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
+#define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
+#define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
+#define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
+#define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
+
+/******************** Bit definition for SPI_DR register ********************/
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
+
+/******************* Bit definition for SPI_CRCPR register ******************/
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
+
+/****************** Bit definition for SPI_RXCRCR register ******************/
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
+
+/****************** Bit definition for SPI_TXCRCR register ******************/
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
+
+/****************** Bit definition for SPI_I2SCFGR register *****************/
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
+
+/****************** Bit definition for SPI_I2SPR register *******************/
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
+
+/******************************************************************************/
+/* */
+/* System Configuration (SYSCFG) */
+/* */
+/******************************************************************************/
+/***************** Bit definition for SYSCFG_MEMRMP register ****************/
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
+#define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+
+/***************** Bit definition for SYSCFG_PMC register *******************/
+#define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
+
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
+
+/**
+ * @brief EXTI0 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) /*!< PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) /*!< PG[0] pin */
+
+/**
+ * @brief EXTI1 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) /*!< PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) /*!< PG[1] pin */
+
+/**
+ * @brief EXTI2 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) /*!< PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) /*!< PG[2] pin */
+
+/**
+ * @brief EXTI3 configuration
+ */
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) /*!< PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) /*!< PG[3] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
+
+/**
+ * @brief EXTI4 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) /*!< PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) /*!< PG[4] pin */
+
+/**
+ * @brief EXTI5 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) /*!< PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) /*!< PG[5] pin */
+
+/**
+ * @brief EXTI6 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) /*!< PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) /*!< PG[6] pin */
+
+/**
+ * @brief EXTI7 configuration
+ */
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) /*!< PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) /*!< PG[7] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
+
+/**
+ * @brief EXTI8 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) /*!< PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) /*!< PG[8] pin */
+
+/**
+ * @brief EXTI9 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) /*!< PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) /*!< PG[9] pin */
+
+/**
+ * @brief EXTI10 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) /*!< PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) /*!< PG[10] pin */
+
+/**
+ * @brief EXTI11 configuration
+ */
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) /*!< PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) /*!< PG[11] pin */
+
+/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
+
+/**
+ * @brief EXTI12 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) /*!< PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) /*!< PG[12] pin */
+
+/**
+ * @brief EXTI13 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) /*!< PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) /*!< PG[13] pin */
+
+/**
+ * @brief EXTI14 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) /*!< PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) /*!< PG[14] pin */
+
+/**
+ * @brief EXTI15 configuration
+ */
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) /*!< PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) /*!< PG[15] pin */
+
+/******************************************************************************/
+/* */
+/* Routing Interface (RI) */
+/* */
+/******************************************************************************/
+
+/******************** Bit definition for RI_ICR register ********************/
+#define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
+#define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+
+#define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
+#define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */
+#define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */
+#define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */
+#define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */
+
+#define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
+#define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+#define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */
+
+#define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
+#define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */
+#define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */
+#define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */
+#define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */
+
+#define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
+#define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+
+#define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
+#define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
+#define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
+#define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
+
+/******************** Bit definition for RI_ASCR1 register ********************/
+#define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
+#define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+#define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
+#define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
+#define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
+#define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
+#define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
+#define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
+#define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
+#define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
+#define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
+#define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
+#define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
+#define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
+#define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
+#define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
+#define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
+
+/******************** Bit definition for RI_ASCR2 register ********************/
+#define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
+#define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
+#define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
+#define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
+#define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
+#define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
+#define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
+#define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
+#define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
+#define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
+#define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
+#define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
+#define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
+#define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
+#define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */
+#define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */
+#define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */
+#define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */
+#define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */
+#define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */
+#define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */
+#define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */
+#define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */
+#define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */
+#define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
+#define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
+#define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
+
+/******************** Bit definition for RI_HYSCR1 register ********************/
+#define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
+#define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
+#define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR2 register ********************/
+#define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
+#define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
+#define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR3 register ********************/
+#define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
+#define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+#define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
+#define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */
+#define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */
+#define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */
+#define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */
+#define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */
+#define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */
+#define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */
+#define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */
+#define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */
+#define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */
+#define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */
+#define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */
+#define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */
+#define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */
+#define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */
+#define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */
+
+/******************** Bit definition for RI_HYSCR4 register ********************/
+#define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
+#define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
+#define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
+#define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
+#define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
+#define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
+#define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
+#define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
+#define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
+#define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
+#define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
+#define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
+#define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
+#define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
+#define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
+#define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
+#define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
+
+/******************************************************************************/
+/* */
+/* Timers (TIM) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for TIM_CR1 register ********************/
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
+
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
+
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
+
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+/******************* Bit definition for TIM_CR2 register ********************/
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
+
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
+
+/******************* Bit definition for TIM_SMCR register *******************/
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
+
+#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */
+
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
+
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
+
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
+
+/******************* Bit definition for TIM_DIER register *******************/
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
+
+/******************** Bit definition for TIM_SR register ********************/
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
+
+/******************* Bit definition for TIM_EGR register ********************/
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
+
+/****************** Bit definition for TIM_CCMR1 register *******************/
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
+
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
+
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
+
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/****************** Bit definition for TIM_CCMR2 register *******************/
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
+
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
+
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
+
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
+
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
+
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
+
+/******************* Bit definition for TIM_CCER register *******************/
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
+
+/******************* Bit definition for TIM_CNT register ********************/
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
+
+/******************* Bit definition for TIM_PSC register ********************/
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
+
+/******************* Bit definition for TIM_ARR register ********************/
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
+
+/******************* Bit definition for TIM_CCR1 register *******************/
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
+
+/******************* Bit definition for TIM_CCR2 register *******************/
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
+
+/******************* Bit definition for TIM_CCR3 register *******************/
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
+
+/******************* Bit definition for TIM_CCR4 register *******************/
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
+
+/******************* Bit definition for TIM_DCR register ********************/
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
+
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
+
+/******************* Bit definition for TIM_DMAR register *******************/
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
+
+/******************* Bit definition for TIM_OR register *********************/
+#define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */
+#define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
+#define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
+
+/******************************************************************************/
+/* */
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for USART_SR register *******************/
+#define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
+#define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
+#define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
+#define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
+#define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
+#define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
+#define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
+#define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
+
+/******************* Bit definition for USART_DR register *******************/
+#define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
+
+/****************** Bit definition for USART_BRR register *******************/
+#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
+#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
+
+/****************** Bit definition for USART_CR1 register *******************/
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
+#define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
+#define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
+#define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
+#define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
+#define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */
+
+/****************** Bit definition for USART_CR2 register *******************/
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
+
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
+
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
+
+/****************** Bit definition for USART_CR3 register *******************/
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */
+
+/****************** Bit definition for USART_GTPR register ******************/
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
+
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
+
+/******************************************************************************/
+/* */
+/* Universal Serial Bus (USB) */
+/* */
+/******************************************************************************/
+
+/*!<Endpoint-specific registers */
+/******************* Bit definition for USB_EP0R register *******************/
+#define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP1R register *******************/
+#define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP2R register *******************/
+#define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP3R register *******************/
+#define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP4R register *******************/
+#define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP5R register *******************/
+#define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP6R register *******************/
+#define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/******************* Bit definition for USB_EP7R register *******************/
+#define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
+
+#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
+#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
+#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
+#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
+#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
+
+#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
+#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
+#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
+
+#define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
+
+#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
+#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
+#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
+
+#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
+#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
+
+/*!<Common registers */
+/******************* Bit definition for USB_CNTR register *******************/
+#define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
+#define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
+#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
+#define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
+#define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
+#define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
+#define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
+#define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
+#define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
+#define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
+#define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
+#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
+#define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
+
+/******************* Bit definition for USB_ISTR register *******************/
+#define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
+#define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
+#define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
+#define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
+#define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
+#define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
+#define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
+#define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
+#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
+#define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
+
+/******************* Bit definition for USB_FNR register ********************/
+#define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
+#define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
+#define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
+#define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
+#define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
+
+/****************** Bit definition for USB_DADDR register *******************/
+#define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
+#define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
+#define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
+#define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
+#define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
+#define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
+#define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
+#define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
+
+#define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
+
+/****************** Bit definition for USB_BTABLE register ******************/
+#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
+
+/*!< Buffer descriptor table */
+/***************** Bit definition for USB_ADDR0_TX register *****************/
+#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_TX register *****************/
+#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_TX register *****************/
+#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_TX register *****************/
+#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_TX register *****************/
+#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_TX register *****************/
+#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_TX register *****************/
+#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_TX register *****************/
+#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_TX register ****************/
+#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
+
+/***************** Bit definition for USB_COUNT1_TX register ****************/
+#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
+
+/***************** Bit definition for USB_COUNT2_TX register ****************/
+#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
+
+/***************** Bit definition for USB_COUNT3_TX register ****************/
+#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
+
+/***************** Bit definition for USB_COUNT4_TX register ****************/
+#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
+
+/***************** Bit definition for USB_COUNT5_TX register ****************/
+#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
+
+/***************** Bit definition for USB_COUNT6_TX register ****************/
+#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
+
+/***************** Bit definition for USB_COUNT7_TX register ****************/
+#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
+#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
+
+/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
+#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
+
+/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
+#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
+
+/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
+#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
+
+/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
+#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
+
+/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
+#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
+
+/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
+#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
+
+/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
+#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
+
+/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
+#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
+
+/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
+#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
+
+/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
+#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
+
+/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
+#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
+
+/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
+#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
+
+/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
+#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
+
+/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
+#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
+
+/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
+#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_ADDR0_RX register *****************/
+#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
+
+/***************** Bit definition for USB_ADDR1_RX register *****************/
+#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
+
+/***************** Bit definition for USB_ADDR2_RX register *****************/
+#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
+
+/***************** Bit definition for USB_ADDR3_RX register *****************/
+#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
+
+/***************** Bit definition for USB_ADDR4_RX register *****************/
+#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
+
+/***************** Bit definition for USB_ADDR5_RX register *****************/
+#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
+
+/***************** Bit definition for USB_ADDR6_RX register *****************/
+#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
+
+/***************** Bit definition for USB_ADDR7_RX register *****************/
+#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
+
+/*----------------------------------------------------------------------------*/
+
+/***************** Bit definition for USB_COUNT0_RX register ****************/
+#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT1_RX register ****************/
+#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT2_RX register ****************/
+#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT3_RX register ****************/
+#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT4_RX register ****************/
+#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT5_RX register ****************/
+#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT6_RX register ****************/
+#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/***************** Bit definition for USB_COUNT7_RX register ****************/
+#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
+
+#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
+#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
+#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
+#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
+#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
+#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
+
+/*----------------------------------------------------------------------------*/
+
+/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
+#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
+#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
+#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
+#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
+#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
+#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
+#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
+#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
+#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
+#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
+#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
+#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
+#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
+#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
+#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
+
+#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
+#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
+
+/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
+#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
+
+#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
+#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
+
+#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
+
+/******************************************************************************/
+/* */
+/* Window WATCHDOG (WWDG) */
+/* */
+/******************************************************************************/
+
+/******************* Bit definition for WWDG_CR register ********************/
+#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
+
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
+
+/******************* Bit definition for WWDG_CFR register *******************/
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
+
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
+
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
+
+/******************* Bit definition for WWDG_SR register ********************/
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/* */
+/* SystemTick (SysTick) */
+/* */
+/******************************************************************************/
+
+/***************** Bit definition for SysTick_CTRL register *****************/
+#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
+#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
+#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
+#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
+
+/***************** Bit definition for SysTick_LOAD register *****************/
+#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
+
+/***************** Bit definition for SysTick_VAL register ******************/
+#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
+
+/***************** Bit definition for SysTick_CALIB register ****************/
+#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
+#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
+#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
+
+/******************************************************************************/
+/* */
+/* Nested Vectored Interrupt Controller (NVIC) */
+/* */
+/******************************************************************************/
+
+/****************** Bit definition for NVIC_ISER register *******************/
+#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
+#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICER register *******************/
+#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
+#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ISPR register *******************/
+#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
+#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_ICPR register *******************/
+#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
+#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_IABR register *******************/
+#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
+#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
+#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
+#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
+#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
+#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
+#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
+#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
+#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
+#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
+#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
+#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
+#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
+#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
+#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
+#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
+#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
+#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
+#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
+#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
+#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
+#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
+#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
+#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
+#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
+#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
+#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
+#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
+#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
+#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
+#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
+#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
+#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
+
+/****************** Bit definition for NVIC_PRI0 register *******************/
+#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
+#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
+#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
+#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
+
+/****************** Bit definition for NVIC_PRI1 register *******************/
+#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
+#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
+#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
+#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
+
+/****************** Bit definition for NVIC_PRI2 register *******************/
+#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
+#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
+#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
+#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
+
+/****************** Bit definition for NVIC_PRI3 register *******************/
+#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
+#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
+#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
+#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
+
+/****************** Bit definition for NVIC_PRI4 register *******************/
+#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
+#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
+#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
+#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
+
+/****************** Bit definition for NVIC_PRI5 register *******************/
+#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
+#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
+#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
+#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
+
+/****************** Bit definition for NVIC_PRI6 register *******************/
+#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
+#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
+#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
+#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
+
+/****************** Bit definition for NVIC_PRI7 register *******************/
+#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
+#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
+#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
+#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
+
+/****************** Bit definition for SCB_CPUID register *******************/
+#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
+#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
+#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
+#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
+#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
+
+/******************* Bit definition for SCB_ICSR register *******************/
+#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
+#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
+#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
+#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
+#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
+#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
+#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
+#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
+#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
+#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
+
+/******************* Bit definition for SCB_VTOR register *******************/
+#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
+#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
+
+/*!<***************** Bit definition for SCB_AIRCR register *******************/
+#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
+#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
+#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
+
+#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
+#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
+#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
+#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
+
+/* prority group configuration */
+#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
+#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
+#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
+
+#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
+#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
+
+/******************* Bit definition for SCB_SCR register ********************/
+#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
+#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
+#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
+
+/******************** Bit definition for SCB_CCR register *******************/
+#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
+#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
+#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
+#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
+#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
+#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
+
+/******************* Bit definition for SCB_SHPR register ********************/
+#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
+#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
+#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
+#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
+
+/****************** Bit definition for SCB_SHCSR register *******************/
+#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
+#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
+#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
+#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
+#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
+#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
+#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
+#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
+#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
+#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
+#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
+#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
+#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
+#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
+
+/******************* Bit definition for SCB_CFSR register *******************/
+/*!< MFSR */
+#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
+#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
+#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
+#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
+#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
+/*!< BFSR */
+#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
+#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
+#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
+#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
+#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
+#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
+/*!< UFSR */
+#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
+#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
+#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
+#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
+#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
+#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
+
+/******************* Bit definition for SCB_HFSR register *******************/
+#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
+#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
+#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
+
+/******************* Bit definition for SCB_DFSR register *******************/
+#define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
+#define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
+#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
+#define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
+#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
+
+/******************* Bit definition for SCB_MMFAR register ******************/
+#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
+
+/******************* Bit definition for SCB_BFAR register *******************/
+#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
+
+/******************* Bit definition for SCB_afsr register *******************/
+#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm32l1xx_conf.h"
+#endif
+
+/** @addtogroup Exported_macro
+ * @{
+ */
+
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT) ((REG) & (BIT))
+
+#define CLEAR_REG(REG) ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))
+
+#define READ_REG(REG) ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L1XX_H */
+
+/**
+ * @}
+ */
+
+ /**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.c b/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.c
new file mode 100644
index 00000000..34720a24
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.c
@@ -0,0 +1,549 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l1xx.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 24-January-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+ * This file contains the system clock configuration for STM32L1xx Ultra
+ * Low Power devices, and is generated by the clock configuration
+ * tool "STM32L1xx_Clock_Configuration_V1.1.0.xls".
+ *
+ * 1. This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+ * and Divider factors, AHB/APBx prescalers and Flash settings),
+ * depending on the configuration made in the clock xls tool.
+ * This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32l1xx_xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * 3. If the system clock source selected by user fails to startup, the SystemInit()
+ * function will do nothing and MSI still used as system clock source. User can
+ * add some code to deal with this issue inside the SetSysClock() function.
+ *
+ * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
+ * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
+ * through PLL, and you are using different crystal you have to adapt the HSE
+ * value to your own configuration.
+ *
+ * 5. This file configures the system clock as follows:
+ *=============================================================================
+ * System Clock Configuration
+ *=============================================================================
+ * System Clock source | PLL(HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK | 32000000 Hz
+ *-----------------------------------------------------------------------------
+ * HCLK | 32000000 Hz
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * HSE Frequency | 8000000 Hz
+ *-----------------------------------------------------------------------------
+ * PLL DIV | 3
+ *-----------------------------------------------------------------------------
+ * PLL MUL | 12
+ *-----------------------------------------------------------------------------
+ * VDD | 3.3 V
+ *-----------------------------------------------------------------------------
+ * Vcore | 1.8 V (Range 1)
+ *-----------------------------------------------------------------------------
+ * Flash Latency | 1 WS
+ *-----------------------------------------------------------------------------
+ * SDIO clock (SDIOCLK) | 48000000 Hz
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB clock | Disabled
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+ *
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx_system
+ * @{
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32l1xx.h"
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Defines
+ * @{
+ */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+ on STM32L152D_EVAL board as data memory */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Variables
+ * @{
+ */
+#ifdef _BOARD_ALS_MAINBOARD
+uint32_t SystemCoreClock = 16000000;
+#else //_BOARD_ALS_MAINBOARD
+uint32_t SystemCoreClock = 32000000;
+#endif //_BOARD_ALS_MAINBOARD
+__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * Initialize the Embedded Flash Interface, the PLL and update the
+ * SystemCoreClock variable.
+ * @param None
+ * @retval None
+ */
+void SystemInit (void)
+{
+ #ifdef _BOARD_ALS_MAINBOARD
+ //For low power reasons, this board runs off of the HSI 16MHz oscillator
+ RCC->CR |= RCC_CR_HSION;
+ //We should wait at least 6us for the HSI to stabilize. Therefore we wait
+ //8us. However, the current clock is 2MHs (MSI) instead of 16, so ...
+ //This is a dirty trick to call a C++ function from C, use the mangled name
+ _ZN6miosix7delayUsEj(8*2/16);
+ RCC->CFGR = 0x00000001; //Select HSI
+ RCC->CR &= ~RCC_CR_MSION;
+ /*!< Disable all interrupts */
+ RCC->CIR = 0x00000000;
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+ return;
+ #endif //_BOARD_ALS_MAINBOARD
+
+ /*!< Set MSION bit */
+ RCC->CR |= (uint32_t)0x00000100;
+
+ /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
+ RCC->CFGR &= (uint32_t)0x88FFC00C;
+
+ /*!< Reset HSION, HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xEEFEFFFE;
+
+ /*!< Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
+ RCC->CFGR &= (uint32_t)0xFF02FFFF;
+
+ /*!< Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM */
+
+ /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
+ SetSysClock();
+
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock according to Clock Register Values
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
+ * value as defined by the MSI range.
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ case 0x04: /* HSI used as system clock */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x08: /* HSE used as system clock */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x0C: /* PLL used as system clock */
+ /* Get PLL clock source and multiplication factor ----------------------*/
+ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
+ plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
+ pllmul = PLLMulTable[(pllmul >> 18)];
+ plldiv = (plldiv >> 22) + 1;
+
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+
+ if (pllsource == 0x00)
+ {
+ /* HSI oscillator clock selected as PLL clock entry */
+ SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
+ }
+ else
+ {
+ /* HSE selected as PLL clock entry */
+ SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
+ }
+ break;
+ default: /* MSI used as system clock */
+ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
+ SystemCoreClock = (32768 * (1 << (msirange + 1)));
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/**
+ * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
+ * settings.
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+static void SetSysClock(void)
+{
+ __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+ /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+ /* Enable HSE */
+ RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ HSEStatus = RCC->CR & RCC_CR_HSERDY;
+ StartUpCounter++;
+ } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+ if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+ {
+ HSEStatus = (uint32_t)0x01;
+ }
+ else
+ {
+ HSEStatus = (uint32_t)0x00;
+ }
+
+ if (HSEStatus == (uint32_t)0x01)
+ {
+ /* Enable 64-bit access */
+ FLASH->ACR |= FLASH_ACR_ACC64;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACR |= FLASH_ACR_PRFTEN;
+
+ /* Flash 1 wait state */
+ FLASH->ACR |= FLASH_ACR_LATENCY;
+
+ /* Power enable */
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+ /* Select the Voltage Range 1 (1.8 V) */
+ PWR->CR = PWR_CR_VOS_0;
+
+ /* Wait Until the Voltage Regulator is ready */
+ while((PWR->CSR & PWR_CSR_VOSF) != RESET)
+ {
+ }
+
+ /* HCLK = SYSCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+ /* PCLK2 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+ /* PCLK1 = HCLK /1*/
+ RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
+
+ /* PLL configuration */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL |
+ RCC_CFGR_PLLDIV));
+ RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3);
+
+ /* Enable PLL */
+ RCC->CR |= RCC_CR_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CR & RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ /* Select PLL as system clock source */
+ RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+ RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
+ {
+ }
+ }
+ else
+ {
+ /* If HSE fails to start-up, the application will have wrong clock
+ configuration. User can add here some code to deal with this error */
+ }
+}
+
+#ifdef DATA_IN_ExtSRAM
+/**
+ * @brief Setup the external memory controller.
+ * Called in SystemInit() function before jump to main.
+ * This function configures the external SRAM mounted on STM32L152D_EVAL board
+ * This SRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ + SRAM pins assignment +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
+ | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
+ | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+
+ | PD15 <-> FSMC_D1 |--------------------+
+ +-------------------+
+*/
+
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHBENR = 0x000080D8;
+
+ /* Connect PDx pins to FSMC Alternate function */
+ GPIOD->AFR[0] = 0x00CC00CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A0A;
+ /* Configure PDx pins speed to 40 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0F0F;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FSMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 40 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC00F;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FSMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 40 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FSMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x00000C00;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00200AAA;
+ /* Configure PGx pins speed to 40 MHz */
+ GPIOG->OSPEEDR = 0x00300FFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FSMC Configuration ------------------------------------------------------*/
+ /* Enable the FSMC interface clock */
+ RCC->AHBENR = 0x400080D8;
+
+ /* Configure and enable Bank1_SRAM3 */
+ FSMC_Bank1->BTCR[4] = 0x00001011;
+ FSMC_Bank1->BTCR[5] = 0x00000300;
+ FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
+/*
+ Bank1_SRAM3 is configured as follow:
+
+ p.FSMC_AddressSetupTime = 0;
+ p.FSMC_AddressHoldTime = 0;
+ p.FSMC_DataSetupTime = 3;
+ p.FSMC_BusTurnAroundDuration = 0;
+ p.FSMC_CLKDivision = 0;
+ p.FSMC_DataLatency = 0;
+ p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+
+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
+
+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
+*/
+
+}
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.h b/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.h
new file mode 100644
index 00000000..1668a6bb
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/CMSIS/system_stm32l1xx.h
@@ -0,0 +1,101 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l1xx.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 24-January-2012
+ * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+ ******************************************************************************
+ * @attention
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * FOR MORE INFORMATION PLEASE READ CAREFULLY THE LICENSE AGREEMENT FILE
+ * LOCATED IN THE ROOT DIRECTORY OF THIS FIRMWARE PACKAGE.
+ *
+ * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l1xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32L1XX_H
+#define __SYSTEM_STM32L1XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L1xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32L1xx_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L1xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L1XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/******************* (C) COPYRIGHT 2012 STMicroelectronics *****END OF FILE****/
diff --git a/miosix/arch/cortexM3_stm32l1/common/arch_settings.h b/miosix/arch/cortexM3_stm32l1/common/arch_settings.h
new file mode 100644
index 00000000..686e61a3
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/arch_settings.h
@@ -0,0 +1,56 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef ARCH_SETTINGS_H
+#define ARCH_SETTINGS_H
+
+namespace miosix {
+
+/**
+ * \addtogroup Settings
+ * \{
+ */
+
+/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes)
+/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and
+/// old sp are saved by hardware on the process stack on Cortex M3 CPUs.
+const unsigned char CTXSAVE_SIZE=9;
+
+/// \internal some architectures save part of the context on their stack.
+/// This constant is used to increase the stack size by the size of context
+/// save frame. If zero, this architecture does not save anything on stack
+/// during context save. Size is in bytes, not words.
+/// MUST be divisible by 4.
+const unsigned int CTXSAVE_ON_STACK=32;
+
+/**
+ * \}
+ */
+
+} //namespace miosix
+
+#endif /* ARCH_SETTINGS_H */
diff --git a/miosix/arch/cortexM3_stm32l1/common/core/interrupts.cpp b/miosix/arch/cortexM3_stm32l1/common/core/interrupts.cpp
new file mode 100644
index 00000000..550d6432
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/core/interrupts.cpp
@@ -0,0 +1,190 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#include "kernel/logging.h"
+#include "config/miosix_settings.h"
+#include "interfaces/portability.h"
+#include "interfaces/arch_registers.h"
+#include "interrupts.h"
+
+using namespace miosix;
+
+#ifdef WITH_ERRLOG
+
+/**
+ * \internal
+ * Used to print an unsigned int in hexadecimal format, and to reboot the system
+ * Note that printf/iprintf cannot be used inside an IRQ, so that's why there's
+ * this function.
+ * \param x number to print
+ */
+static void printUnsignedInt(unsigned int x)
+{
+ static const char hexdigits[]="0123456789abcdef";
+ char result[]="0x........\r\n";
+ for(int i=9;i>=2;i--)
+ {
+ result[i]=hexdigits[x & 0xf];
+ x>>=4;
+ }
+ IRQerrorLog(result);
+}
+
+/**
+ * \internal
+ * Print the program counter of the thread that was running when the exception
+ * occurred.
+ */
+static void printProgramCounter()
+{
+ register unsigned int pc;
+ // Get program counter when the exception was thrown from stack frame
+ asm volatile("mrs %0, psp \n\t"
+ "add %0, %0, #24 \n\t"
+ "ldr %0, [%0] \n\t":"=r"(pc));
+ printUnsignedInt(pc);
+}
+
+#endif //WITH_ERRLOG
+
+/**
+ * \internal
+ * Wait until all data is sent to the console and reboot
+ */
+static void waitConsoleAndReboot()
+{
+ while(!Console::IRQtxComplete()) ; //Wait until all data sent
+ miosix_private::IRQsystemReboot();
+}
+
+void NMI_Handler()
+{
+ IRQerrorLog("\r\n***Unexpected NMI\r\n");
+ waitConsoleAndReboot();
+}
+
+void HardFault_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected HardFault @ ");
+ printProgramCounter();
+ unsigned int hfsr=SCB->HFSR;
+ if(hfsr & SCB_HFSR_FORCED_Msk)
+ IRQerrorLog("Fault escalation occurred\r\n");
+ if(hfsr & SCB_HFSR_VECTTBL_Msk)
+ IRQerrorLog("A BusFault occurred during a vector table read\r\n");
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void MemManage_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected MemManage @ ");
+ printProgramCounter();
+ unsigned int cfsr=SCB->CFSR;
+ if(cfsr & 0x00000080)
+ {
+ IRQerrorLog("Fault caused by attempted access to ");
+ printUnsignedInt(SCB->MMFAR);
+ } else IRQerrorLog("The address that caused the fault is missing\r\n");
+ if(cfsr & 0x00000010)
+ IRQerrorLog("Fault occurred during exception stacking\r\n");
+ if(cfsr & 0x00000008)
+ IRQerrorLog("Fault occurred during exception unstacking\r\n");
+ if(cfsr & 0x00000002)
+ IRQerrorLog("Fault was caused by invalid PC\r\n");
+ if(cfsr & 0x00000001)
+ IRQerrorLog("Fault was caused by attempted execution from XN area\r\n");
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void BusFault_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected BusFault @ ");
+ printProgramCounter();
+ unsigned int cfsr=SCB->CFSR;
+ if(cfsr & 0x00008000)
+ {
+ IRQerrorLog("Fault caused by attempted access to ");
+ printUnsignedInt(SCB->BFAR);
+ } else IRQerrorLog("The address that caused the fault is missing\r\n");
+ if(cfsr & 0x00001000)
+ IRQerrorLog("Fault occurred during exception stacking\r\n");
+ if(cfsr & 0x00000800)
+ IRQerrorLog("Fault occurred during exception unstacking\r\n");
+ if(cfsr & 0x00000400)
+ IRQerrorLog("Fault is imprecise\r\n");
+ if(cfsr & 0x00000200)
+ IRQerrorLog("Fault is precise\r\n");
+ if(cfsr & 0x00000100)
+ IRQerrorLog("Fault happened during instruction fetch\r\n");
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void UsageFault_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected UsageFault @ ");
+ printProgramCounter();
+ unsigned int cfsr=SCB->CFSR;
+ if(cfsr & 0x02000000) IRQerrorLog("Divide by zero\r\n");
+ if(cfsr & 0x01000000) IRQerrorLog("Unaligned memory access\r\n");
+ if(cfsr & 0x00080000) IRQerrorLog("Attempted coprocessor access\r\n");
+ if(cfsr & 0x00040000) IRQerrorLog("EXC_RETURN not expected now\r\n");
+ if(cfsr & 0x00020000) IRQerrorLog("Invalid EPSR usage\r\n");
+ if(cfsr & 0x00010000) IRQerrorLog("Undefined instruction\r\n");
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void DebugMon_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected DebugMon @ ");
+ printProgramCounter();
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void PendSV_Handler()
+{
+ #ifdef WITH_ERRLOG
+ IRQerrorLog("\r\n***Unexpected PendSV @ ");
+ printProgramCounter();
+ #endif //WITH_ERRLOG
+ waitConsoleAndReboot();
+}
+
+void unexpectedInterrupt()
+{
+ IRQerrorLog("\r\n***Unexpected Peripheral interrupt\r\n");
+ waitConsoleAndReboot();
+}
diff --git a/miosix/arch/cortexM3_stm32l1/common/core/interrupts.h b/miosix/arch/cortexM3_stm32l1/common/core/interrupts.h
new file mode 100644
index 00000000..6b74a54f
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/core/interrupts.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef INTERRUPTS_H
+#define INTERRUPTS_H
+
+/**
+ * Called when an unexpected interrupt occurs.
+ * It is called by stage_1_boot.cpp for all weak interrupts not defined.
+ */
+void unexpectedInterrupt();
+
+#endif //INTERRUPTS_H
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h
new file mode 100644
index 00000000..74aecf53
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h
@@ -0,0 +1,9 @@
+
+#ifndef ARCH_REGISTERS_IMPL_H
+#define ARCH_REGISTERS_IMPL_H
+
+#include "CMSIS/stm32l1xx.h"
+#include "CMSIS/core_cm3.h"
+#include "CMSIS/system_stm32l1xx.h"
+
+#endif //ARCH_REGISTERS_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp
new file mode 100644
index 00000000..48e0bf3e
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp
@@ -0,0 +1,77 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#include "interfaces/delays.h"
+
+namespace miosix {
+
+void delayMs(unsigned int mseconds)
+{
+ #ifndef __CODE_IN_XRAM
+
+ #ifdef SYSCLK_FREQ_16MHz
+ register const unsigned int count=4000;
+ #else
+ #warning "Delays are uncalibrated for this clock frequency"
+ #endif
+
+ for(unsigned int i=0;i<mseconds;i++)
+ {
+ // This delay has been calibrated to take 1 millisecond
+ // It is written in assembler to be independent on compiler optimization
+ asm volatile(" mov r1, #0 \n"
+ "___loop_m: cmp r1, %0 \n"
+ " itt lo \n"
+ " addlo r1, r1, #1 \n"
+ " blo ___loop_m \n"::"r"(count):"r1");
+ }
+
+ #else //__CODE_IN_XRAM
+ #error "No delays"
+ #endif //__CODE_IN_XRAM
+}
+
+void delayUs(unsigned int useconds)
+{
+ #ifndef __CODE_IN_XRAM
+
+ // This delay has been calibrated to take x microseconds
+ // It is written in assembler to be independent on compiler optimization
+ asm volatile(" mov r1, #4 \n"
+ " mul r2, %0, r1 \n"
+ " mov r1, #0 \n"
+ "___loop_u: cmp r1, r2 \n"
+ " itt lo \n"
+ " addlo r1, r1, #1 \n"
+ " blo ___loop_u \n"::"r"(useconds):"r1","r2");
+
+ #else //__CODE_IN_XRAM
+ #error "No delays"
+ #endif //__CODE_IN_XRAM
+}
+
+} //namespace miosix
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/endianness_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/endianness_impl.h
new file mode 100644
index 00000000..f34043ea
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/endianness_impl.h
@@ -0,0 +1,92 @@
+/***************************************************************************
+ * Copyright (C) 2011 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef ENDIANNESS_IMPL_H
+#define ENDIANNESS_IMPL_H
+
+//This target is little endian
+#define MIOSIX_LITTLE_ENDIAN
+
+#ifdef __cplusplus
+#define __MIOSIX_INLINE inline
+#else //__cplusplus
+#define __MIOSIX_INLINE static inline
+#endif //__cplusplus
+
+__MIOSIX_INLINE unsigned short swapBytes16(unsigned short x)
+{
+ //It's kind of a shame that GCC can't automatically make use of
+ //instructions like rev and rev16 to do byte swapping.
+ //Moreover, while for 32 and 64 bit integers it has builtins, for 16 bit
+ //we're forced to use inline asm.
+ #ifdef __GNUC__
+ if(!__builtin_constant_p(x))
+ {
+ unsigned short y;
+ asm("rev16 %0, %1":"=r"(y):"r"(x));
+ return y;
+ } else {
+ //It gets worse: if value is constant inlining assembler disables
+ //contant folding, wtf...
+ return (x>>8) | (x<<8);
+ }
+ #else
+ return (x>>8) | (x<<8);
+ #endif
+}
+
+__MIOSIX_INLINE unsigned int swapBytes32(unsigned int x)
+{
+ #ifdef __GNUC__
+ return __builtin_bswap32(x);
+ #else
+ return ( x>>24) |
+ ((x<< 8) & 0x00ff0000) |
+ ((x>> 8) & 0x0000ff00) |
+ ( x<<24);
+ #endif
+}
+
+__MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x)
+{
+ #ifdef __GNUC__
+ return __builtin_bswap64(x);
+ #else
+ return ( x>>56) |
+ ((x<<40) & 0x00ff000000000000ull) |
+ ((x<<24) & 0x0000ff0000000000ull) |
+ ((x<< 8) & 0x000000ff00000000ull) |
+ ((x>> 8) & 0x00000000ff000000ull) |
+ ((x>>24) & 0x0000000000ff0000ull) |
+ ((x>>40) & 0x000000000000ff00ull) |
+ ( x<<56);
+ #endif
+}
+
+#undef __MIOSIX_INLINE
+
+#endif //ENDIANNESS_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.cpp b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.cpp
new file mode 100644
index 00000000..b2457bf2
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.cpp
@@ -0,0 +1,61 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#include "gpio_impl.h"
+
+namespace miosix {
+
+void GpioBase::modeImpl(unsigned int p, unsigned char n, Mode::Mode_ m)
+{
+ GPIO_TypeDef* gpio=reinterpret_cast<GPIO_TypeDef*>(p);
+
+ gpio->MODER &= ~(3<<(n*2));
+ gpio->OTYPER &= ~(1<<n);
+ gpio->PUPDR &= ~(3<<(n*2));
+
+ gpio->MODER |= (m>>3)<<(n*2);
+ gpio->OTYPER |= ((m>>2) & 1)<<n;
+ gpio->PUPDR |= (m & 3)<<(n*2);
+}
+
+void GpioBase::afImpl(unsigned int p, unsigned char n, unsigned char af)
+{
+ GPIO_TypeDef* gpio=reinterpret_cast<GPIO_TypeDef*>(p);
+ af &= 0xf;
+
+ if(n<8)
+ {
+ gpio->AFR[0] &= ~(0xf<<(n*4));
+ gpio->AFR[0] |= af<<(n*4);
+ } else {
+ n-=8;
+ gpio->AFR[1] &= ~(0xf<<(n*4));
+ gpio->AFR[1] |= af<<(n*4);
+ }
+}
+
+} //namespace miosix
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.h
new file mode 100644
index 00000000..a55d55d7
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/gpio_impl.h
@@ -0,0 +1,265 @@
+/***************************************************************************
+ * Copyright (C) 2009, 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/*
+ * Versions:
+ * 1.0 First release
+ * 1.1 Made Mode, Gpio and GpioBase contructor private to explicitly disallow
+ * creating instances of these classes.
+ * 1.2 Fixed a bug
+ * 1.3 Applied patch by Lee Richmond (http://pastebin.com/f7ae1a65f). Now
+ * mode() is inlined too.
+ * 1.4 Adapted to stm32f2
+ * 1.5 Added GpioPin for easily passing a Gpio as a parameter to a function
+ */
+
+#ifndef GPIO_IMPL_H
+#define GPIO_IMPL_H
+
+#include "interfaces/arch_registers.h"
+
+namespace miosix {
+
+/**
+ * This class just encapsulates the Mode_ enum so that the enum names don't
+ * clobber the global namespace.
+ */
+class Mode
+{
+public:
+ /**
+ * GPIO mode (INPUT, OUTPUT, ...)
+ * \code pin::mode(Mode::INPUT);\endcode
+ */
+ enum Mode_
+ {
+ INPUT = 0, ///Floating Input (MODE=00 TYPE=0 PUP=00)
+ INPUT_PULL_UP = 1, ///Pullup Input (MODE=00 TYPE=0 PUP=01)
+ INPUT_PULL_DOWN = 2, ///Pulldown Input (MODE=00 TYPE=0 PUP=10)
+ INPUT_ANALOG = 24, ///Analog Input (MODE=11 TYPE=0 PUP=00)
+ OUTPUT = 8, ///Push Pull Output (MODE=01 TYPE=0 PUP=00)
+ OPEN_DRAIN = 12, ///Open Drain Output (MODE=01 TYPE=1 PUP=00)
+ ALTERNATE = 16, ///Alternate function (MODE=10 TYPE=0 PUP=00)
+ ALTERNATE_OD = 20, ///Alternate Open Drain (MODE=10 TYPE=1 PUP=00)
+ };
+private:
+ Mode(); //Just a wrapper class, disallow creating instances
+};
+
+/**
+ * This class just encapsulates the Speed_ enum so that the enum names don't
+ * clobber the global namespace.
+ */
+class Speed
+{
+public:
+ /**
+ * GPIO speed
+ * \code pin::speed(Speed::_100MHz);\endcode
+ */
+ enum Speed_
+ {
+ _400KHz = 0x0,
+ _2MHz = 0x1,
+ _10MHz = 0x2,
+ _40MHz = 0x3
+ };
+private:
+ Speed(); //Just a wrapper class, disallow creating instances
+};
+
+/**
+ * Base class to implement non template-dependent functions that, if inlined,
+ * would significantly increase code size
+ */
+class GpioBase
+{
+protected:
+ static void modeImpl(unsigned int p, unsigned char n, Mode::Mode_ m);
+ static void afImpl(unsigned int p, unsigned char n, unsigned char af);
+};
+
+/**
+ * This class allows to easiliy pass a Gpio as a parameter to a function.
+ * Accessing a GPIO through this class is slower than with just the Gpio,
+ * but is a convenient alternative in some cases. Also, an instance of this
+ * class occupies a few bytes of memory, unlike the Gpio class.
+ */
+class GpioPin : private GpioBase
+{
+public:
+ /**
+ * Constructor
+ * \param p GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f2xx.h
+ * \param n which pin (0 to 15)
+ */
+ GpioPin(unsigned int p, unsigned char n)
+ : p(reinterpret_cast<GPIO_TypeDef*>(p)), n(n) {}
+
+ /**
+ * Set the GPIO to the desired mode (INPUT, OUTPUT, ...)
+ * \param m enum Mode_
+ */
+ void mode(Mode::Mode_ m)
+ {
+ modeImpl(reinterpret_cast<unsigned int>(p),n,m);
+ }
+
+ /**
+ * Set the GPIO speed
+ * \param s speed value
+ */
+ void speed(Speed::Speed_ s)
+ {
+ p->OSPEEDR &= ~(3<<(n*2));
+ p->OSPEEDR |= s<<(n*2);
+ }
+
+ /**
+ * Select which of the many alternate functions is to be connected with the
+ * GPIO pin.
+ * \param af alternate function number, from 0 to 15
+ */
+ void alternateFunction(unsigned char af)
+ {
+ afImpl(reinterpret_cast<unsigned int>(p),n,af);
+ }
+
+ /**
+ * Set the pin to 1, if it is an output
+ */
+ void high()
+ {
+ p->BSRRL= 1<<n;
+ }
+
+ /**
+ * Set the pin to 0, if it is an output
+ */
+ void low()
+ {
+ p->BSRRH=1<<n;
+ }
+
+ /**
+ * Allows to read the pin status
+ * \return 0 or 1
+ */
+ int value()
+ {
+ return (p->IDR & (1<<n)) ? 1 : 0;
+ }
+
+private:
+ GPIO_TypeDef *p; //Pointer to the port
+ unsigned char n; //Number of the GPIO within the port
+};
+
+/**
+ * Gpio template class
+ * \param P GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f2xx.h
+ * \param N which pin (0 to 15)
+ * The intended use is to make a typedef to this class with a meaningful name.
+ * \code
+ * typedef Gpio<PORTA_BASE,0> green_led;
+ * green_led::mode(Mode::OUTPUT);
+ * green_led::high();//Turn on LED
+ * \endcode
+ */
+template<unsigned int P, unsigned char N>
+class Gpio : private GpioBase
+{
+public:
+ /**
+ * Set the GPIO to the desired mode (INPUT, OUTPUT, ...)
+ * \param m enum Mode_
+ */
+ static void mode(Mode::Mode_ m)
+ {
+ modeImpl(P,N,m);
+ }
+
+ /**
+ * Set the GPIO speed
+ * \param s speed value
+ */
+ static void speed(Speed::Speed_ s)
+ {
+ reinterpret_cast<GPIO_TypeDef*>(P)->OSPEEDR &= ~(3<<(N*2));
+ reinterpret_cast<GPIO_TypeDef*>(P)->OSPEEDR |= s<<(N*2);
+ }
+
+ /**
+ * Select which of the many alternate functions is to be connected with the
+ * GPIO pin.
+ * \param af alternate function number, from 0 to 15
+ */
+ static void alternateFunction(unsigned char af)
+ {
+ afImpl(P,N,af);
+ }
+
+ /**
+ * Set the pin to 1, if it is an output
+ */
+ static void high()
+ {
+ reinterpret_cast<GPIO_TypeDef*>(P)->BSRRL= 1<<N;
+ }
+
+ /**
+ * Set the pin to 0, if it is an output
+ */
+ static void low()
+ {
+ reinterpret_cast<GPIO_TypeDef*>(P)->BSRRH= 1<<N;
+ }
+
+ /**
+ * Allows to read the pin status
+ * \return 0 or 1
+ */
+ static int value()
+ {
+ return ((reinterpret_cast<GPIO_TypeDef*>(P)->IDR & 1<<N)? 1 : 0);
+ }
+
+ /**
+ * \return this Gpio converted as a GpioPin class
+ */
+ static GpioPin getPin()
+ {
+ return GpioPin(P,N);
+ }
+
+private:
+ Gpio();//Only static member functions, disallow creating instances
+};
+
+} //namespace miosix
+
+#endif //GPIO_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp
new file mode 100644
index 00000000..ac8c64f7
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp
@@ -0,0 +1,253 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+ //Miosix kernel
+
+#include "interfaces/portability.h"
+#include "kernel/kernel.h"
+#include "kernel/error.h"
+#include "interfaces/bsp.h"
+#include "kernel/scheduler/scheduler.h"
+#include "kernel/scheduler/tick_interrupt.h"
+#include <algorithm>
+
+/**
+ * \internal
+ * timer interrupt routine.
+ * Since inside naked functions only assembler code is allowed, this function
+ * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls
+ * the implementation code in ISR_preempt()
+ */
+void SysTick_Handler() __attribute__((naked));
+void SysTick_Handler()
+{
+ saveContext();
+ //Call ISR_preempt(). Name is a C++ mangled name.
+ asm volatile("bl _ZN14miosix_private11ISR_preemptEv");
+ restoreContext();
+}
+
+/**
+ * \internal
+ * software interrupt routine.
+ * Since inside naked functions only assembler code is allowed, this function
+ * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls
+ * the implementation code in ISR_yield()
+ */
+void SVC_Handler() __attribute__((naked));
+void SVC_Handler()
+{
+ saveContext();
+ //Call ISR_yield(). Name is a C++ mangled name.
+ asm volatile("bl _ZN14miosix_private9ISR_yieldEv");
+ restoreContext();
+}
+
+#ifdef SCHED_TYPE_CONTROL_BASED
+/**
+ * \internal
+ * Auxiliary timer interupt routine.
+ * Used for variable lenght bursts in control based scheduler.
+ * Since inside naked functions only assembler code is allowed, this function
+ * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls
+ * the implementation code in ISR_yield()
+ */
+void TIM3_IRQHandler() __attribute__((naked));
+void TIM3_IRQHandler()
+{
+ saveContext();
+ //Call ISR_auxTimer(). Name is a C++ mangled name.
+ asm volatile("bl _ZN14miosix_private12ISR_auxTimerEv");
+ restoreContext();
+}
+#endif //SCHED_TYPE_CONTROL_BASED
+
+namespace miosix_private {
+
+/**
+ * \internal
+ * Called by the timer interrupt, preempt to next thread
+ * Declared noinline to avoid the compiler trying to inline it into the caller,
+ * which would violate the requirement on naked functions. Function is not
+ * static because otherwise the compiler optimizes it out...
+ */
+void ISR_preempt() __attribute__((noinline));
+void ISR_preempt()
+{
+ IRQstackOverflowCheck();
+ miosix::IRQtickInterrupt();
+}
+
+/**
+ * \internal
+ * Called by the software interrupt, yield to next thread
+ * Declared noinline to avoid the compiler trying to inline it into the caller,
+ * which would violate the requirement on naked functions. Function is not
+ * static because otherwise the compiler optimizes it out...
+ */
+void ISR_yield() __attribute__((noinline));
+void ISR_yield()
+{
+ IRQstackOverflowCheck();
+ miosix::Scheduler::IRQfindNextThread();
+}
+
+#ifdef SCHED_TYPE_CONTROL_BASED
+/**
+ * \internal
+ * Auxiliary timer interupt routine.
+ * Used for variable lenght bursts in control based scheduler.
+ */
+void ISR_auxTimer() __attribute__((noinline));
+void ISR_auxTimer()
+{
+ IRQstackOverflowCheck();
+ miosix::Scheduler::IRQfindNextThread();//If the kernel is running, preempt
+ if(miosix::kernel_running!=0) miosix::tick_skew=true;
+ TIM3->SR=0;
+}
+#endif //SCHED_TYPE_CONTROL_BASED
+
+void IRQstackOverflowCheck()
+{
+ const unsigned int watermarkSize=miosix::WATERMARK_LEN/sizeof(unsigned int);
+ for(unsigned int i=0;i<watermarkSize;i++)
+ {
+ if(miosix::cur->watermark[i]!=miosix::WATERMARK_FILL)
+ miosix::errorHandler(miosix::STACK_OVERFLOW);
+ }
+ if(miosix::cur->ctxsave[0] < reinterpret_cast<unsigned int>(
+ miosix::cur->watermark+watermarkSize))
+ miosix::errorHandler(miosix::STACK_OVERFLOW);
+}
+
+void IRQsystemReboot()
+{
+ NVIC_SystemReset();
+}
+
+void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp,
+ void *argv)
+{
+ unsigned int *stackPtr=sp;
+ stackPtr--; //Stack is full descending, so decrement first
+ *stackPtr=0x01000000; stackPtr--; //--> xPSR
+ *stackPtr=reinterpret_cast<unsigned long>(
+ &miosix::Thread::threadLauncher); stackPtr--; //--> pc
+ *stackPtr=0xffffffff; stackPtr--; //--> lr
+ *stackPtr=0; stackPtr--; //--> r12
+ *stackPtr=0; stackPtr--; //--> r3
+ *stackPtr=0; stackPtr--; //--> r2
+ *stackPtr=reinterpret_cast<unsigned long >(argv); stackPtr--; //--> r1
+ *stackPtr=reinterpret_cast<unsigned long >(pc); //--> r0
+
+ ctxsave[0]=reinterpret_cast<unsigned long>(stackPtr); //--> psp
+ //leaving the content of r4-r11 uninitialized
+}
+
+void IRQportableStartKernel()
+{
+ //Enable fault handlers
+ SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
+ | SCB_SHCSR_MEMFAULTENA_Msk;
+ //Enable traps for unaligned memory access and division by zero
+ SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk | SCB_CCR_UNALIGN_TRP_Msk;
+ NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting
+ NVIC_SetPriority(SVC_IRQn,3);//High priority for SVC (Max=0, min=15)
+ NVIC_SetPriority(SysTick_IRQn,3);//High priority for SysTick (Max=0, min=15)
+ SysTick->LOAD=SystemCoreClock/miosix::TICK_FREQ;
+ //Start SysTick, set to generate interrupts
+ SysTick->CTRL=SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_CLKSOURCE_Msk;
+
+ #ifdef SCHED_TYPE_CONTROL_BASED
+ AuxiliaryTimer::IRQinit();
+ #endif //SCHED_TYPE_CONTROL_BASED
+
+ //create a temporary space to save current registers. This data is useless
+ //since there's no way to stop the sheduler, but we need to save it anyway.
+ unsigned int s_ctxsave[miosix::CTXSAVE_SIZE];
+ ctxsave=s_ctxsave;//make global ctxsave point to it
+ //Note, we can't use enableInterrupts() now since the call is not mathced
+ //by a call to disableInterrupts()
+ __enable_fault_irq();
+ __enable_irq();
+ miosix::Thread::yield();
+ //Never reaches here
+}
+
+void sleepCpu()
+{
+ __WFI();
+}
+
+#ifdef SCHED_TYPE_CONTROL_BASED
+void AuxiliaryTimer::IRQinit()
+{
+ RCC->APB1ENR|=RCC_APB1ENR_TIM3EN;
+ DBGMCU->APB1FZ|=DBGMCU_APB1_FZ_DBG_TIM3_STOP; //Tim3 stops while debugging
+ TIM3->CR1=0; //Upcounter, not started, no special options
+ TIM3->CR2=0; //No special options
+ TIM3->SMCR=0; //No external trigger
+ TIM3->CNT=0; //Clear timer
+ //get timer frequency considering APB1 prescaler
+ //consider that timer clock is twice APB1 clock when the APB1 prescaler has
+ //a division factor greater than 2
+ int timerClock=SystemCoreClock;
+ int apb1prescaler=(RCC->CFGR>>10) & 7;
+ if(apb1prescaler>4) timerClock>>=(apb1prescaler-4);
+ TIM3->PSC=(timerClock/miosix::AUX_TIMER_CLOCK)-1;
+ TIM3->ARR=0xffff; //Count from zero to 0xffff
+ TIM3->DIER=TIM_DIER_CC1IE; //Enable interrupt on compare
+ TIM3->CCR1=0xffff; //This will be initialized later with setValue
+ NVIC_SetPriority(TIM3_IRQn,3);//High priority for TIM3 (Max=0, min=15)
+ NVIC_EnableIRQ(TIM3_IRQn);
+ TIM3->CR1=TIM_CR1_CEN; //Start timer
+ //This is very important: without this the prescaler shadow register may
+ //not be updated
+ TIM3->EGR=TIM_EGR_UG;
+}
+
+int AuxiliaryTimer::IRQgetValue()
+{
+ return static_cast<int>(TIM3->CNT);
+}
+
+void AuxiliaryTimer::IRQsetValue(int x)
+{
+ TIM3->CR1=0; //Stop timer since changing CNT or CCR1 while running fails
+ TIM3->CNT=0;
+ TIM3->CCR1=static_cast<unsigned short>(std::min(x,0xffff));
+ TIM3->CR1=TIM_CR1_CEN; //Start timer again
+ //The above instructions cause a spurious if not called within the
+ //timer 2 IRQ (This happens if called from an SVC).
+ //Clearing the pending bit prevents this spurious interrupt
+ TIM3->SR=0;
+ NVIC_ClearPendingIRQ(TIM3_IRQn);
+}
+#endif //SCHED_TYPE_CONTROL_BASED
+
+}; //namespace miosix_private
diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h
new file mode 100644
index 00000000..5fcc019b
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h
@@ -0,0 +1,141 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+//Miosix kernel
+
+#ifndef PORTABILITY_IMPL_H
+#define PORTABILITY_IMPL_H
+
+#include "interfaces/arch_registers.h"
+#include "config/miosix_settings.h"
+
+/**
+ * \addtogroup Drivers
+ * \{
+ */
+
+/*
+ * This pointer is used by the kernel, and should not be used by end users.
+ * this is a pointer to a location where to store the thread's registers during
+ * context switch. It requires C linkage to be used inside asm statement.
+ * Registers are saved in the following order:
+ * *ctxsave+32 --> r11
+ * *ctxsave+28 --> r10
+ * *ctxsave+24 --> r9
+ * *ctxsave+20 --> r8
+ * *ctxsave+16 --> r7
+ * *ctxsave+12 --> r6
+ * *ctxsave+8 --> r5
+ * *ctxsave+4 --> r4
+ * *ctxsave+0 --> psp
+ */
+extern "C" {
+extern volatile unsigned int *ctxsave;
+}
+
+/**
+ * \internal
+ * \def saveContext()
+ * Save context from an interrupt<br>
+ * Must be the first line of an IRQ where a context switch can happen.
+ * The IRQ must be "naked" to prevent the compiler from generating context save.
+ */
+#define saveContext() \
+{ \
+ asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \
+ "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \
+ "ldr r0, =ctxsave \n\t" /*get current context*/ \
+ "ldr r0, [r0] \n\t" \
+ "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \
+ ); \
+}
+
+/**
+ * \def restoreContext()
+ * Restore context in an IRQ where saveContext() is used. Must be the last line
+ * of an IRQ where a context switch can happen. The IRQ must be "naked" to
+ * prevent the compiler from generating context restore.
+ */
+#define restoreContext() \
+{ \
+ asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \
+ "ldr r0, [r0] \n\t" \
+ "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \
+ "msr psp, r1 \n\t" /*restore PROCESS sp*/ \
+ "ldmia sp!, {pc} \n\t" /*return*/ \
+ ); \
+}
+
+/**
+ * \}
+ */
+
+namespace miosix_private {
+
+/**
+ * \addtogroup Drivers
+ * \{
+ */
+
+inline void doYield()
+{
+ asm volatile("svc 0");
+}
+
+inline void doDisableInterrupts()
+{
+ // Documentation says __disable_irq() disables all interrupts with
+ // configurable priority, so also SysTick and SVC.
+ // No need to disable faults with __disable_fault_irq()
+ __disable_irq();
+ //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's
+ //the need for a memory barrier to avoid aggressive reordering
+ asm volatile("":::"memory");
+}
+
+inline void doEnableInterrupts()
+{
+ __enable_irq();
+ //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's
+ //the need for a memory barrier to avoid aggressive reordering
+ asm volatile("":::"memory");
+}
+
+inline bool checkAreInterruptsEnabled()
+{
+ register int i;
+ asm volatile("mrs %0, primask \n\t":"=r"(i));
+ if(i!=0) return false;
+ return true;
+}
+
+/**
+ * \}
+ */
+
+}; //namespace miosix_private
+
+#endif //PORTABILITY_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h
new file mode 100644
index 00000000..7b20669c
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h
@@ -0,0 +1,69 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef BOARD_SETTINGS_H
+#define BOARD_SETTINGS_H
+
+namespace miosix {
+
+/**
+ * \addtogroup Settings
+ * \{
+ */
+
+/// Size of stack for main().
+/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the
+/// STM32F151C8 has 10KB of RAM so use a small 1.5K stack.
+const unsigned int MAIN_STACK_SIZE=1536;
+
+/// Frequency of tick (in Hz). The frequency of the STM32F151C8 timer in the
+/// Miosix board can be divided by 1000. This allows to use a 1KHz tick and
+/// the minimun Thread::sleep value is 1ms
+/// For the priority scheduler this is also the context switch frequency
+const unsigned int TICK_FREQ=1000;
+
+///\internal Aux timer run @ 100KHz
+///Note that since the timer is only 16 bits this imposes a limit on the
+///burst measurement of 655ms. If due to a pause_kernel() or
+///disable_interrupts() section a thread runs for more than that time, a wrong
+///burst value will be measured
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
+
+///\def STDOUT_REDIRECTED_TO_DCC
+///If defined, stdout is redirected to the debug communication channel, and
+///will be printed if OpenOCD is connected. If not defined, stdout will be
+///redirected throug USART1, as usual.
+//#define STDOUT_REDIRECTED_TO_DCC
+
+/**
+ * \}
+ */
+
+} //namespace miosix
+
+#endif /* BOARD_SETTINGS_H */
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp
new file mode 100644
index 00000000..cc404ea5
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp
@@ -0,0 +1,315 @@
+
+#include "interfaces/arch_registers.h"
+#include "core/interrupts.h" //For the unexpected interrupt call
+#include <string.h>
+
+/*
+ * startup.cpp
+ * STM32 C++ startup.
+ * NOTE: for stm32l medium density devices ONLY.
+ * - supports interrupt handlers in C++ without extern "C"
+ * - global constructors are correctly called before main()
+ * Developed by Terraneo Federico, based on ST startup code.
+ * Additionally modified to boot Miosix.
+ */
+
+//Will be called at the end of stage 1 of boot, function is implemented in
+//stage_2_boot.cpp
+extern "C" void _init();
+
+/**
+ * Calls C++ global constructors
+ * \param start first function pointer to call
+ * \param end one past the last function pointer to call
+ * Declared "noinline" to optimize code size
+ */
+static void call_constructors(unsigned long *start, unsigned long *end) __attribute__((noinline));
+static void call_constructors(unsigned long *start, unsigned long *end)
+{
+ for(unsigned long *i=start; i<end; i++)
+ {
+ void (*funcptr)();
+ funcptr=reinterpret_cast<void (*)()>(*i);
+ funcptr();
+ }
+}
+
+/**
+ * Called by Reset_Handler, performs initialization and calls main.
+ * Never returns.
+ */
+void program_startup() __attribute__((noreturn));
+void program_startup()
+{
+ //Cortex M3 core appears to get out of reset with interrupts already enabled
+ __disable_irq();
+
+ //These are defined in the linker script
+ extern unsigned char _etext asm("_etext");
+ extern unsigned char _data asm("_data");
+ extern unsigned char _edata asm("_edata");
+ extern unsigned char _bss_start asm("_bss_start");
+ extern unsigned char _bss_end asm("_bss_end");
+ extern unsigned long __preinit_array_start asm("__preinit_array_start");
+ extern unsigned long __preinit_array_end asm("__preinit_array_end");
+ extern unsigned long __init_array_start asm("__init_array_start");
+ extern unsigned long __init_array_end asm("__init_array_end");
+ extern unsigned long _ctor_start asm("_ctor_start");
+ extern unsigned long _ctor_end asm("_ctor_end");
+
+ //Initialize .data section, clear .bss section
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other
+ //boards but in this case it is not, since the *_code_in_xram.ld linker
+ //script puts code in XRAM, but data in the internal one, so there's still
+ //the need to copy it in its final place
+ memcpy(data, etext, edata-data);
+ memset(bss_start, 0, bss_end-bss_start);
+
+ //Initialize C++ global constructors
+ call_constructors(&__preinit_array_start, &__preinit_array_end);
+ call_constructors(&__init_array_start, &__init_array_end);
+ call_constructors(&_ctor_start, &_ctor_end);
+
+ //Move on to stage 2
+ _init();
+
+ //If main returns, reboot
+ NVIC_SystemReset();
+ for(;;) ;
+}
+
+/**
+ * Reset handler, called by hardware immediately after reset
+ */
+void Reset_Handler() __attribute__((__interrupt__, noreturn));
+void Reset_Handler()
+{
+ /*
+ * SystemInit() is called *before* initializing .data and zeroing .bss
+ * Despite all startup files provided by ST do the opposite, there are three
+ * good reasons to do so:
+ * First, the CMSIS specifications say that SystemInit() must not access
+ * global variables, so it is actually possible to call it before
+ * Second, when running Miosix with the xram linker scripts .data and .bss
+ * are placed in the external RAM, so we *must* call SystemInit(), which
+ * enables xram, before touching .data and .bss
+ * Third, this is a performance improvement since the loops that initialize
+ * .data and zeros .bss now run with the CPU at full speed instead of 16MHz
+ * Note that it is called before switching stacks because the memory
+ * at _heap_end can be unavailable until the external RAM is initialized.
+ */
+ SystemInit();
+
+ /*
+ * Initialize process stack and switch to it.
+ * This is required for booting Miosix, a small portion of the top of the
+ * heap area will be used as stack until the first thread starts. After,
+ * this stack will be abandoned and the process stack will point to the
+ * current thread's stack.
+ */
+ asm volatile("ldr r0, =_heap_end \n\t"
+ "msr psp, r0 \n\t"
+ "movw r0, #2 \n\n" //Privileged, process stack
+ "msr control, r0 \n\t"
+ "isb \n\t":::"r0");
+
+ program_startup();
+}
+
+/**
+ * All unused interrupts call this function.
+ */
+extern "C" void Default_Handler()
+{
+ unexpectedInterrupt();
+}
+
+//System handlers
+void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
+void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
+void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
+void /*__attribute__((weak))*/ MemManage_Handler();
+void /*__attribute__((weak))*/ BusFault_Handler();
+void /*__attribute__((weak))*/ UsageFault_Handler();
+void /*__attribute__((weak))*/ SVC_Handler();
+void /*__attribute__((weak))*/ DebugMon_Handler();
+void /*__attribute__((weak))*/ PendSV_Handler();
+void /*__attribute__((weak))*/ SysTick_Handler();
+
+//Interrupt handlers
+void __attribute__((weak)) WWDG_IRQHandler();
+void __attribute__((weak)) PVD_IRQHandler();
+void __attribute__((weak)) TAMPER_STAMP_IRQHandler();
+void __attribute__((weak)) RTC_WKUP_IRQHandler();
+void __attribute__((weak)) FLASH_IRQHandler();
+void __attribute__((weak)) RCC_IRQHandler();
+void __attribute__((weak)) EXTI0_IRQHandler();
+void __attribute__((weak)) EXTI1_IRQHandler();
+void __attribute__((weak)) EXTI2_IRQHandler();
+void __attribute__((weak)) EXTI3_IRQHandler();
+void __attribute__((weak)) EXTI4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel1_IRQHandler();
+void __attribute__((weak)) DMA1_Channel2_IRQHandler();
+void __attribute__((weak)) DMA1_Channel3_IRQHandler();
+void __attribute__((weak)) DMA1_Channel4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel5_IRQHandler();
+void __attribute__((weak)) DMA1_Channel6_IRQHandler();
+void __attribute__((weak)) DMA1_Channel7_IRQHandler();
+void __attribute__((weak)) ADC1_IRQHandler();
+void __attribute__((weak)) USB_HP_IRQHandler();
+void __attribute__((weak)) USB_LP_IRQHandler();
+void __attribute__((weak)) DAC_IRQHandler();
+void __attribute__((weak)) COMP_IRQHandler();
+void __attribute__((weak)) EXTI9_5_IRQHandler();
+void __attribute__((weak)) LCD_IRQHandler ();
+void __attribute__((weak)) TIM9_IRQHandler();
+void __attribute__((weak)) TIM10_IRQHandler();
+void __attribute__((weak)) TIM11_IRQHandler();
+void __attribute__((weak)) TIM2_IRQHandler();
+void __attribute__((weak)) TIM3_IRQHandler();
+void __attribute__((weak)) TIM4_IRQHandler();
+void __attribute__((weak)) I2C1_EV_IRQHandler();
+void __attribute__((weak)) I2C1_ER_IRQHandler();
+void __attribute__((weak)) I2C2_EV_IRQHandler();
+void __attribute__((weak)) I2C2_ER_IRQHandler();
+void __attribute__((weak)) SPI1_IRQHandler();
+void __attribute__((weak)) SPI2_IRQHandler();
+void __attribute__((weak)) USART1_IRQHandler();
+void __attribute__((weak)) USART2_IRQHandler();
+void __attribute__((weak)) USART3_IRQHandler();
+void __attribute__((weak)) EXTI15_10_IRQHandler();
+void __attribute__((weak)) RTC_Alarm_IRQHandler();
+void __attribute__((weak)) USB_FS_WKUP_IRQHandler();
+void __attribute__((weak)) TIM6_IRQHandler();
+void __attribute__((weak)) TIM7_IRQHandler();
+
+//Stack top, defined in the linker script
+extern char _main_stack_top asm("_main_stack_top");
+
+//Interrupt vectors, must be placed @ address 0x00000000
+//The extern declaration is required otherwise g++ optimizes it out
+extern void (* const __Vectors[])();
+void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
+{
+ reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External Interrupts */
+ WWDG_IRQHandler,
+ PVD_IRQHandler,
+ TAMPER_STAMP_IRQHandler,
+ RTC_WKUP_IRQHandler,
+ FLASH_IRQHandler,
+ RCC_IRQHandler,
+ EXTI0_IRQHandler,
+ EXTI1_IRQHandler,
+ EXTI2_IRQHandler,
+ EXTI3_IRQHandler,
+ EXTI4_IRQHandler,
+ DMA1_Channel1_IRQHandler,
+ DMA1_Channel2_IRQHandler,
+ DMA1_Channel3_IRQHandler,
+ DMA1_Channel4_IRQHandler,
+ DMA1_Channel5_IRQHandler,
+ DMA1_Channel6_IRQHandler,
+ DMA1_Channel7_IRQHandler,
+ ADC1_IRQHandler,
+ USB_HP_IRQHandler,
+ USB_LP_IRQHandler,
+ DAC_IRQHandler,
+ COMP_IRQHandler,
+ EXTI9_5_IRQHandler,
+ LCD_IRQHandler ,
+ TIM9_IRQHandler,
+ TIM10_IRQHandler,
+ TIM11_IRQHandler,
+ TIM2_IRQHandler,
+ TIM3_IRQHandler,
+ TIM4_IRQHandler,
+ I2C1_EV_IRQHandler,
+ I2C1_ER_IRQHandler,
+ I2C2_EV_IRQHandler,
+ I2C2_ER_IRQHandler,
+ SPI1_IRQHandler,
+ SPI2_IRQHandler,
+ USART1_IRQHandler,
+ USART2_IRQHandler,
+ USART3_IRQHandler,
+ EXTI15_10_IRQHandler,
+ RTC_Alarm_IRQHandler,
+ USB_FS_WKUP_IRQHandler,
+ TIM6_IRQHandler,
+ TIM7_IRQHandler,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ reinterpret_cast<void (*)()>(0xF108F85F)
+ /* This is for boot in RAM mode for STM32L devices.*/
+};
+
+#pragma weak WWDG_IRQHandler = Default_Handler
+#pragma weak PVD_IRQHandler = Default_Handler
+#pragma weak TAMPER_STAMP_IRQHandler = Default_Handler
+#pragma weak RTC_WKUP_IRQHandler = Default_Handler
+#pragma weak FLASH_IRQHandler = Default_Handler
+#pragma weak RCC_IRQHandler = Default_Handler
+#pragma weak EXTI0_IRQHandler = Default_Handler
+#pragma weak EXTI1_IRQHandler = Default_Handler
+#pragma weak EXTI2_IRQHandler = Default_Handler
+#pragma weak EXTI3_IRQHandler = Default_Handler
+#pragma weak EXTI4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel1_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel2_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel3_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel5_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel6_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel7_IRQHandler = Default_Handler
+#pragma weak ADC1_IRQHandler = Default_Handler
+#pragma weak USB_HP_IRQHandler = Default_Handler
+#pragma weak USB_LP_IRQHandler = Default_Handler
+#pragma weak DAC_IRQHandler = Default_Handler
+#pragma weak COMP_IRQHandler = Default_Handler
+#pragma weak EXTI9_5_IRQHandler = Default_Handler
+#pragma weak LCD_IRQHandler = Default_Handler
+#pragma weak TIM9_IRQHandler = Default_Handler
+#pragma weak TIM10_IRQHandler = Default_Handler
+#pragma weak TIM11_IRQHandler = Default_Handler
+#pragma weak TIM2_IRQHandler = Default_Handler
+#pragma weak TIM3_IRQHandler = Default_Handler
+#pragma weak TIM4_IRQHandler = Default_Handler
+#pragma weak I2C1_EV_IRQHandler = Default_Handler
+#pragma weak I2C1_ER_IRQHandler = Default_Handler
+#pragma weak I2C2_EV_IRQHandler = Default_Handler
+#pragma weak I2C2_ER_IRQHandler = Default_Handler
+#pragma weak SPI1_IRQHandler = Default_Handler
+#pragma weak SPI2_IRQHandler = Default_Handler
+#pragma weak USART1_IRQHandler = Default_Handler
+#pragma weak USART2_IRQHandler = Default_Handler
+#pragma weak USART3_IRQHandler = Default_Handler
+#pragma weak EXTI15_10_IRQHandler = Default_Handler
+#pragma weak RTC_Alarm_IRQHandler = Default_Handler
+#pragma weak USB_FS_WKUP_IRQHandler = Default_Handler
+#pragma weak TIM6_IRQHandler = Default_Handler
+#pragma weak TIM7_IRQHandler = Default_Handler
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp
new file mode 100644
index 00000000..8298d3b8
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp
@@ -0,0 +1,134 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp.cpp Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+
+#include <cstdlib>
+#include <inttypes.h>
+#include "interfaces/bsp.h"
+#include "kernel/kernel.h"
+#include "kernel/sync.h"
+#include "interfaces/delays.h"
+#include "interfaces/portability.h"
+#include "interfaces/arch_registers.h"
+#include "config/miosix_settings.h"
+#include "kernel/logging.h"
+#include "console-impl.h"
+
+namespace miosix {
+
+//
+// Initialization
+//
+
+void IRQbspInit()
+{
+ //Enable all GPIOs
+ RCC->AHBENR |= RCC_AHBENR_GPIOAEN
+ | RCC_AHBENR_GPIOBEN
+ | RCC_AHBENR_GPIOCEN
+ | RCC_AHBENR_GPIOHEN;
+
+ //Port config (H=high, L=low, PU=pullup, PD=pulldown)
+ // | PORTA | PORTB | PORTC | PORTH |
+ //--+--------------+-------------+---------+---------+
+ // 0| IN | IN PD | - | IN PD |
+ // 1| IN PD | IN PD | - | IN PD |
+ // 2| IN | IN PD | - | - |
+ // 3| IN PD | IN PD | - | - |
+ // 4| OUT H 10MHz | IN PD | - | - |
+ // 5| AF5 10MHz | IN PD | - | - |
+ // 6| AF5 10MHz | IN PD | - | - |
+ // 7| AF5 10MHz | IN PD | - | - |
+ // 8| OUT L 10MHz | IN PD | - | - |
+ // 9| AF7 400KHz | IN PD | - | - |
+ //10| AF7PU 400KHz | IN PD | - | - |
+ //11| IN PD | OUT L 10MHz | - | - |
+ //12| IN PD | OUT L 10MHz | - | - |
+ //13| OUT L 400KHz | OUT L 10MHz | IN PD | - |
+ //14| OUT H 400KHz | OUT L 10MHz | AF0 | - |
+ //15| OUT L 400KHz | OUT L 10MHz | AF0 | - |
+
+ GPIOA->OSPEEDR=0x0002aa00;
+ GPIOB->OSPEEDR=0xaa800000;
+
+ GPIOA->MODER=0x5429a900;
+ GPIOB->MODER=0x55400000;
+ GPIOC->MODER=0xa0000000;
+ GPIOH->MODER=0x00000000;
+
+ GPIOA->PUPDR=0x02900088;
+ GPIOB->PUPDR=0x002aaaaa;
+ GPIOC->PUPDR=0x08000000;
+ GPIOH->PUPDR=0x0000000a;
+
+ GPIOA->ODR=0x00004010;
+ GPIOB->ODR=0x00000000;
+
+ GPIOA->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 5<<20 | 5<<24 | 5<<28;
+ GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28;
+ GPIOB->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28;
+ GPIOB->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28;
+ GPIOC->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28;
+ GPIOC->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28;
+
+ ledOn();
+ delayMs(100);
+ ledOff();
+
+ #ifndef STDOUT_REDIRECTED_TO_DCC
+ IRQstm32f2serialPortInit();
+ #endif //STDOUT_REDIRECTED_TO_DCC
+}
+
+void bspInit2()
+{
+ //Nothing to do
+}
+
+//
+// Shutdown and reboot
+//
+
+void shutdown()
+{
+ disableInterrupts();
+ for(;;) ;
+}
+
+void reboot()
+{
+ while(!Console::txComplete()) ;
+ disableInterrupts();
+ miosix_private::IRQsystemReboot();
+}
+
+};//namespace miosix
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h
new file mode 100644
index 00000000..3f19dcec
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h
@@ -0,0 +1,46 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp_impl.h Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+#ifndef BSP_IMPL_H
+#define BSP_IMPL_H
+
+#include "config/miosix_settings.h"
+#include "hwmapping.h"
+
+namespace miosix {
+
+inline void ledOn() { led::high(); }
+inline void ledOff() { led::low(); }
+
+}
+
+#endif //BSP_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console-impl.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console-impl.h
new file mode 100644
index 00000000..549cddb6
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console-impl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef CONSOLE_IMPL_H
+#define CONSOLE_IMPL_H
+
+namespace miosix {
+
+void IRQstm32f2serialPortInit();
+
+} //namespace miosix
+
+#endif //CONSOLE_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console.cpp b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console.cpp
new file mode 100644
index 00000000..f431e628
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/console.cpp
@@ -0,0 +1,229 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#include "interfaces/console.h"
+#include "console-impl.h"
+#include "kernel/sync.h"
+#include "kernel/scheduler/scheduler.h"
+#include "kernel/logging.h"
+#include "interfaces/arch_registers.h"
+#include "interfaces/portability.h"
+#include "interfaces/gpio.h"
+#include "board_settings.h"
+#include "drivers/dcc.h"
+#include "hwmapping.h"
+#include <cstring>
+
+#ifndef STDOUT_REDIRECTED_TO_DCC
+
+/**
+ * \internal
+ * serial port interrupt routine
+ * Since inside naked functions only assembler code is allowed, this function
+ * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls
+ * the implementation code in serial_irq_impl()
+ */
+void USART1_IRQHandler() __attribute__ ((naked));
+void USART1_IRQHandler()
+{
+ saveContext();
+ asm volatile("bl _ZN6miosix13serialIrqImplEv");
+ restoreContext();
+}
+
+namespace miosix {
+
+static Mutex rxMutex;///<\internal Mutex used to guard the rx queue
+static Mutex txMutex;///<\internal Mutex used to guard the tx queue
+const unsigned int SOFTWARE_RX_QUEUE=32;///<\internal Size of rx software queue
+static Queue<char,SOFTWARE_RX_QUEUE> rxQueue;///<\internal Rx software queue
+
+/**
+ * \internal
+ * Serial interrupt code. Declared noinline to avoid the compiler trying to
+ * inline it into the caller, which would violate the requirement on naked
+ * functions.
+ * Function is not static because otherwise the compiler optimizes it out...
+ */
+void serialIrqImpl() __attribute__((noinline));
+void serialIrqImpl()
+{
+ bool hppw=false;
+ unsigned int status=USART1->SR;
+ if(status & USART_SR_ORE) //Receiver overrun
+ {
+ char c=USART1->DR; //Always read data, since this clears interrupt flags
+ if((status & USART_SR_RXNE) && ((status & 0x7)==0))
+ rxQueue.IRQput(c,hppw);
+ } else if(status & USART_SR_RXNE) //Receiver data available
+ {
+ char c=USART1->DR; //Always read data, since this clears interrupt flags
+ if((status & 0x7)==0) //If no noise nor framing nor parity error
+ {
+ rxQueue.IRQput(c,hppw);
+ }
+ }
+ if(hppw) Scheduler::IRQfindNextThread();
+}
+
+void IRQstm32f2serialPortInit()
+{
+ rxQueue.IRQreset();
+ //Enable clock to GPIOA and USART1
+ RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
+ RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
+ //Enabled, 8 data bit, no parity, interrupt on character rx
+ USART1->CR1 = USART_CR1_UE | USART_CR1_RXNEIE;
+ USART1->CR2 = 0;//Disable lin mode and synchronous mode
+ USART1->CR3 = 0;//Disable irda and smartcard mode
+
+ #ifdef SYSCLK_FREQ_16MHz
+ //USART1 is connected to APB2 @ 16MHz
+ const unsigned int brr = (52<<4) | (1<<0); //BRR=195.3125 0.04% Error
+ #else
+ #warning "No serial baudrate for this clock frequency"
+ #endif
+ //baudrate=19200
+ USART1->BRR=brr;
+
+ //Now that serial port is active, configure I/Os
+ serial::tx::alternateFunction(7);
+ serial::tx::mode(Mode::ALTERNATE);
+ serial::rx::alternateFunction(7);
+ serial::rx::mode(Mode::ALTERNATE);
+ USART1->CR1 |= USART_CR1_TE | USART_CR1_RE;//Finally enable tx and rx
+ NVIC_SetPriority(USART1_IRQn,10);//Low priority for serial. (Max=0, min=15)
+ NVIC_EnableIRQ(USART1_IRQn);
+}
+
+static void serialWriteImpl(const char *str, unsigned int len)
+{
+ {
+ Lock<Mutex> l(txMutex);
+ for(unsigned int i=0;i<len;i++)
+ {
+ while((USART1->SR & USART_SR_TXE)==0) ;
+ USART1->DR=*str++;
+ }
+ }
+}
+
+void Console::write(const char *str)
+{
+ serialWriteImpl(str,std::strlen(str));
+}
+
+void Console::write(const char *data, int length)
+{
+ serialWriteImpl(data,length);
+}
+
+bool Console::txComplete()
+{
+ return (USART1->SR & USART_SR_TC)!=0;
+}
+
+void Console::IRQwrite(const char *str)
+{
+ while((*str)!='\0')
+ {
+ //Wait until the hardware fifo is ready to accept one char
+ while((USART1->SR & USART_SR_TXE)==0) ; //Wait until ready
+ USART1->DR=*str++;
+ }
+}
+
+bool Console::IRQtxComplete()
+{
+ return (USART1->SR & USART_SR_TC)!=0;
+}
+
+char Console::readChar()
+{
+ Lock<Mutex> l(rxMutex);
+ char result;
+ rxQueue.get(result);
+ return result;
+}
+
+bool Console::readCharNonBlocking(char& c)
+{
+ Lock<Mutex> l(rxMutex);
+ if(rxQueue.isEmpty()==false)
+ {
+ rxQueue.get(c);
+ return true;
+ }
+ return false;
+}
+
+} // namespace miosix
+
+#else //STDOUT_REDIRECTED_TO_DCC
+
+namespace miosix {
+
+void Console::write(const char *str)
+{
+ debugWrite(str,std::strlen(str));
+}
+
+void Console::write(const char *data, int length)
+{
+ debugWrite(data,length);
+}
+
+bool Console::txComplete()
+{
+ return true;
+}
+
+void Console::IRQwrite(const char *str)
+{
+ IRQdebugWrite(str);
+}
+
+bool Console::IRQtxComplete()
+{
+ return true;
+}
+
+char Console::readChar()
+{
+ errorLog("***stdin is not available in DCC");
+ for(;;) ;
+ return 0; //Only to avoid a compiler warning
+}
+
+bool Console::readCharNonBlocking(char& c)
+{
+ return false;
+}
+
+} //namespace miosix
+
+#endif //STDOUT_REDIRECTED_TO_DCC
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h
new file mode 100644
index 00000000..a269cdc2
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h
@@ -0,0 +1,66 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef HWMAPPING_H
+#define HWMAPPING_H
+
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+typedef Gpio<GPIOA_BASE,0> strig;
+typedef Gpio<GPIOA_BASE,2> button;
+typedef Gpio<GPIOA_BASE,13> led;
+typedef Gpio<GPIOA_BASE,14> hpled;
+typedef Gpio<GPIOA_BASE,15> sen;
+
+namespace nrf {
+typedef Gpio<GPIOA_BASE,1> irq;
+typedef Gpio<GPIOA_BASE,4> cs;
+typedef Gpio<GPIOA_BASE,5> sck;
+typedef Gpio<GPIOA_BASE,6> miso;
+typedef Gpio<GPIOA_BASE,7> mosi;
+typedef Gpio<GPIOA_BASE,8> ce;
+}
+
+namespace cam {
+typedef Gpio<GPIOA_BASE,3> irq;
+typedef Gpio<GPIOB_BASE,11> en;
+typedef Gpio<GPIOB_BASE,12> cs;
+typedef Gpio<GPIOB_BASE,13> sck;
+typedef Gpio<GPIOB_BASE,14> miso;
+typedef Gpio<GPIOB_BASE,15> mosi;
+}
+
+namespace serial {
+typedef Gpio<GPIOA_BASE,9> tx;
+typedef Gpio<GPIOA_BASE,10> rx;
+}
+
+} //namespace miosix
+
+#endif //HWMAPPING_H
diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld
new file mode 100644
index 00000000..fa6f822f
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld
@@ -0,0 +1,166 @@
+/*
+ * C++ enabled linker script for stm32 (64K FLASH, 10K RAM)
+ * Developed by TFT: Terraneo Federico Technologies
+ * Optimized for use with the Miosix kernel
+ */
+
+/*
+ * This linker script puts:
+ * - read only data and code (.text, .rodata, .eh_*) in flash
+ * - stacks, heap and sections .data and .bss in the internal ram
+ * - the external ram (if available) is not used.
+ */
+
+/*
+ * The main stack is used for interrupt handling by the kernel.
+ *
+ * *** Readme ***
+ * This linker script places the main stack (used by the kernel for interrupts)
+ * at the bottom of the ram, instead of the top. This is done for two reasons:
+ *
+ * - as an optimization for microcontrollers with little ram memory. In fact
+ * the implementation of malloc from newlib requests memory to the OS in 4KB
+ * block (except the first block that can be smaller). This is probably done
+ * for compatibility with OSes with an MMU and paged memory. To see why this
+ * is bad, consider a microcontroller with 8KB of ram: when malloc finishes
+ * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
+ * fail because the top part of the ram is used by the main stack. As a
+ * result, the top part of the memory will not be used by malloc, even if
+ * available (and it is nearly *half* the ram on an 8KB mcu). By placing the
+ * main stack at the bottom of the ram, the upper 4KB block will be entirely
+ * free and available as heap space.
+ *
+ * - In case of main stack overflow the cpu will fault because access to memory
+ * before the beginning of the ram faults. Instead with the default stack
+ * placement the main stack will silently collide with the heap.
+ * Note: if increasing the main stack size also increase the ORIGIN value in
+ * the MEMORY definitions below accordingly.
+ */
+_main_stack_size = 0x00000200; /* main stack = 512Bytes */
+_main_stack_top = 0x20000000 + _main_stack_size;
+ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
+
+/* end of the heap on 10KB microcontrollers */
+_heap_end = 0x20002800; /* end of available ram */
+
+/* identify the Entry Point */
+ENTRY(_Z13Reset_Handlerv)
+
+/* specify the memory areas */
+MEMORY
+{
+ flash(rx) : ORIGIN = 0, LENGTH = 64K
+
+ /*
+ * Note, the ram starts at 0x20000000 but it is necessary to add the size
+ * of the main stack, so it is 0x20000200.
+ */
+ ram(wx) : ORIGIN = 0x20000200, LENGTH = 10K-0x200
+}
+
+/* now define the output sections */
+SECTIONS
+{
+ . = 0;
+
+ /* .text section: code goes to flash */
+ .text :
+ {
+ /* Startup code must go at address 0 */
+ KEEP(*(.isr_vector))
+
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ /* these sections for thumb interwork? */
+ *(.glue_7)
+ *(.glue_7t)
+ /* these sections for C++? */
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.ARM.extab*)
+ *(.gnu.linkonce.armextab.*)
+
+ . = ALIGN(4);
+ /* .rodata: constant data */
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ /* C++ Static constructors/destructors (eabi) */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /* C++ Static constructors/destructors (elf) */
+ . = ALIGN(4);
+ _ctor_start = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ _ctor_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > flash
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ . = ALIGN(8);
+ _etext = .;
+
+ /* .data section: global variables go to ram, but also store a copy to
+ flash to initialize them */
+ .data : ALIGN(8)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ _edata = .;
+ } > ram AT > flash
+
+ /* .bss section: uninitialized global variables go to ram */
+ _bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ . = ALIGN(8);
+ } > ram
+ _bss_end = .;
+
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index d9a4e9b8..d3b28298 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -21,7 +21,8 @@
#OPT_BOARD := stm32f407vg_stm32f4discovery
#OPT_BOARD := stm32f207ig_stm3220g-eval
#OPT_BOARD := stm32f207zg_ethboard_v2
-OPT_BOARD := stm32f207ze_camboard
+#OPT_BOARD := stm32f207ze_als_camboard
+OPT_BOARD := stm32l151_als_mainboard
##
## Optimization flags, choose one.
@@ -236,8 +237,10 @@ else ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval)
ARCH := cortexM3_stm32f2
else ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2)
ARCH := cortexM3_stm32f2
-else ifeq ($(OPT_BOARD),stm32f207ze_camboard)
+else ifeq ($(OPT_BOARD),stm32f207ze_als_camboard)
ARCH := cortexM3_stm32f2
+else ifeq ($(OPT_BOARD),stm32l151_als_mainboard)
+ ARCH := cortexM3_stm32l1
else
$(error Error: no board specified in miosix/config/Makefile.inc)
endif
@@ -735,11 +738,11 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
endif
##-------------------------------------------------------------------------
- ## BOARD: stm32f207ze_camboard
+ ## BOARD: stm32f207ze_als_camboard
##
- else ifeq ($(OPT_BOARD),stm32f207ze_camboard)
+ else ifeq ($(OPT_BOARD),stm32f207ze_als_camboard)
## Base directory with header files for this board
- BOARD_INC := arch/cortexM3_stm32f2/stm32f207ze_camboard
+ BOARD_INC := arch/cortexM3_stm32f2/stm32f207ze_als_camboard
## Select linker script and boot file
## Their path must be relative to the miosix directory.
@@ -754,8 +757,8 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
$(BOARD_INC)/interfaces-impl/bsp.cpp
## Add a #define to allow querying board name
- CFLAGS_BASE += -D_BOARD_CAMBOARD
- CXXFLAGS_BASE += -D_BOARD_CAMBOARD
+ CFLAGS_BASE += -D_BOARD_ALS_CAMBOARD
+ CXXFLAGS_BASE += -D_BOARD_ALS_CAMBOARD
## Clock frequency
CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_120MHz=120000000
@@ -813,6 +816,88 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
$(ARCH_INC)/CMSIS/core_cm3.c \
$(ARCH_INC)/CMSIS/system_stm32f2xx.c
+##-----------------------------------------------------------------------------
+## ARCHITECTURE: cortexM3_stm32l1
+##
+else ifeq ($(ARCH),cortexM3_stm32l1)
+ ## Base directory with else header files for this board
+ ARCH_INC := arch/cortexM3_stm32l1/common
+
+ ##-------------------------------------------------------------------------
+ ## BOARD: stm32l151c8_als_mainboard
+ ##
+ ifeq ($(OPT_BOARD),stm32l151_als_mainboard)
+ ## Base directory with header files for this board
+ BOARD_INC := arch/cortexM3_stm32l1/stm32l151c8_als_mainboard
+
+ ## Select linker script and boot file
+ ## Their path must be relative to the miosix directory.
+ BOOT_FILE := $(BOARD_INC)/core/stage_1_boot.o
+ LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+10k_rom.ld
+
+ ## Select architecture specific files
+ ## These are the files in arch/<arch name>/<board name>
+ ARCH_SRC := \
+ $(BOARD_INC)/interfaces-impl/console.cpp \
+ $(BOARD_INC)/interfaces-impl/bsp.cpp
+
+ ## Add a #define to allow querying board name
+ CFLAGS_BASE += -D_BOARD_ALS_MAINBOARD
+ CXXFLAGS_BASE += -D_BOARD_ALS_MAINBOARD
+
+ ## Clock frequency
+ CLOCK_FREQ := -DSYSCLK_FREQ_16MHz=16000000
+
+ ## Select programmer command line
+ ## This is the program that is invoked when the user types
+ ## 'make program'
+ ## The command must provide a way to program the board, or print an
+ ## error message saying that 'make program' is not supported for that
+ ## board.
+ PROGRAM_CMDLINE := stm32flash -w main.bin -v /dev/ttyUSB1
+
+ ##-------------------------------------------------------------------------
+ ## End of board list
+ ##
+ endif
+
+ ## Select compiler
+ PREFIX=arm-miosix-eabi-
+
+ ## From compiler prefix form the name of the compiler and other tools
+ CC := $(PREFIX)gcc
+ CXX := $(PREFIX)g++
+ LD := $(PREFIX)ld
+ AR := $(PREFIX)ar
+ AS := $(PREFIX)as
+ CP := $(PREFIX)objcopy
+ OD := $(PREFIX)objdump
+ SZ := $(PREFIX)size
+
+ ## Select appropriate compiler flags for both ASM/C/C++/linker
+ AFLAGS_BASE := -mcpu=cortex-m3 -mthumb
+ CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32L1 $(CLOCK_FREQ) $(XRAM) \
+ -mcpu=cortex-m3 -mthumb -mfix-cortex-m3-ldrd \
+ $(OPT_OPTIMIZATION) -ffunction-sections -Wall -g -c
+ CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32L1 $(CLOCK_FREQ) $(XRAM) \
+ $(OPT_EXCEPT) -mcpu=cortex-m3 -mthumb \
+ -mfix-cortex-m3-ldrd $(OPT_OPTIMIZATION) \
+ -ffunction-sections -Wall -g -c
+ LFLAGS_BASE := -mcpu=cortex-m3 -mthumb -mfix-cortex-m3-ldrd \
+ -Wl,--gc-sections,-Map,main.map \
+ -Wl,-T./miosix/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
+ $(OPT_OPTIMIZATION) -nostdlib
+
+ ## Select architecture specific files
+ ## These are the files in arch/<arch name>/common
+ ARCH_SRC += \
+ arch/common/drivers/dcc.cpp \
+ $(ARCH_INC)/core/interrupts.cpp \
+ $(ARCH_INC)/interfaces-impl/portability.cpp \
+ $(ARCH_INC)/interfaces-impl/gpio_impl.cpp \
+ $(ARCH_INC)/interfaces-impl/delays.cpp \
+ $(ARCH_INC)/CMSIS/system_stm32l1xx.c
+
##-----------------------------------------------------------------------------
## end of architecture list
##
diff --git a/miosix_np_2/nbproject/Package-stm32f207ze_als_camboard.bash b/miosix_np_2/nbproject/Package-stm32f207ze_als_camboard.bash
new file mode 100644
index 00000000..ceeb8a24
--- /dev/null
+++ b/miosix_np_2/nbproject/Package-stm32f207ze_als_camboard.bash
@@ -0,0 +1,75 @@
+#!/bin/bash -x
+
+#
+# Generated - do not edit!
+#
+
+# Macros
+TOP=`pwd`
+CND_PLATFORM=ARM_MIOSIX_EABI-Linux-x86
+CND_CONF=stm32f207ze_als_camboard
+CND_DISTDIR=dist
+CND_BUILDDIR=build
+NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging
+TMPDIRNAME=tmp-packaging
+OUTPUT_PATH=MissingOutputInProject
+OUTPUT_BASENAME=MissingOutputInProject
+PACKAGE_TOP_DIR=miosixnp2/
+
+# Functions
+function checkReturnCode
+{
+ rc=$?
+ if [ $rc != 0 ]
+ then
+ exit $rc
+ fi
+}
+function makeDirectory
+# $1 directory path
+# $2 permission (optional)
+{
+ mkdir -p "$1"
+ checkReturnCode
+ if [ "$2" != "" ]
+ then
+ chmod $2 "$1"
+ checkReturnCode
+ fi
+}
+function copyFileToTmpDir
+# $1 from-file path
+# $2 to-file path
+# $3 permission
+{
+ cp "$1" "$2"
+ checkReturnCode
+ if [ "$3" != "" ]
+ then
+ chmod $3 "$2"
+ checkReturnCode
+ fi
+}
+
+# Setup
+cd "${TOP}"
+mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package
+rm -rf ${NBTMPDIR}
+mkdir -p ${NBTMPDIR}
+
+# Copy files and create directories and links
+cd "${TOP}"
+makeDirectory "${NBTMPDIR}/miosixnp2"
+copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755
+
+
+# Generate tar file
+cd "${TOP}"
+rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/miosixnp2.tar
+cd ${NBTMPDIR}
+tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/miosixnp2.tar *
+checkReturnCode
+
+# Cleanup
+cd "${TOP}"
+rm -rf ${NBTMPDIR}
diff --git a/miosix_np_2/nbproject/Package-stm32l151c8_als_mainboard.bash b/miosix_np_2/nbproject/Package-stm32l151c8_als_mainboard.bash
new file mode 100644
index 00000000..562d0e09
--- /dev/null
+++ b/miosix_np_2/nbproject/Package-stm32l151c8_als_mainboard.bash
@@ -0,0 +1,75 @@
+#!/bin/bash -x
+
+#
+# Generated - do not edit!
+#
+
+# Macros
+TOP=`pwd`
+CND_PLATFORM=ARM_MIOSIX_EABI-Linux-x86
+CND_CONF=stm32l151c8_als_mainboard
+CND_DISTDIR=dist
+CND_BUILDDIR=build
+NBTMPDIR=${CND_BUILDDIR}/${CND_CONF}/${CND_PLATFORM}/tmp-packaging
+TMPDIRNAME=tmp-packaging
+OUTPUT_PATH=MissingOutputInProject
+OUTPUT_BASENAME=MissingOutputInProject
+PACKAGE_TOP_DIR=miosixnp2/
+
+# Functions
+function checkReturnCode
+{
+ rc=$?
+ if [ $rc != 0 ]
+ then
+ exit $rc
+ fi
+}
+function makeDirectory
+# $1 directory path
+# $2 permission (optional)
+{
+ mkdir -p "$1"
+ checkReturnCode
+ if [ "$2" != "" ]
+ then
+ chmod $2 "$1"
+ checkReturnCode
+ fi
+}
+function copyFileToTmpDir
+# $1 from-file path
+# $2 to-file path
+# $3 permission
+{
+ cp "$1" "$2"
+ checkReturnCode
+ if [ "$3" != "" ]
+ then
+ chmod $3 "$2"
+ checkReturnCode
+ fi
+}
+
+# Setup
+cd "${TOP}"
+mkdir -p ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package
+rm -rf ${NBTMPDIR}
+mkdir -p ${NBTMPDIR}
+
+# Copy files and create directories and links
+cd "${TOP}"
+makeDirectory "${NBTMPDIR}/miosixnp2"
+copyFileToTmpDir "${OUTPUT_PATH}" "${NBTMPDIR}/${PACKAGE_TOP_DIR}bin/${OUTPUT_BASENAME}" 0755
+
+
+# Generate tar file
+cd "${TOP}"
+rm -f ${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/miosixnp2.tar
+cd ${NBTMPDIR}
+tar -vcf ../../../../${CND_DISTDIR}/${CND_CONF}/${CND_PLATFORM}/package/miosixnp2.tar *
+checkReturnCode
+
+# Cleanup
+cd "${TOP}"
+rm -rf ${NBTMPDIR}
diff --git a/miosix_np_2/nbproject/configurations.xml b/miosix_np_2/nbproject/configurations.xml
index 6a5d0dca..c81a4ef2 100644
--- a/miosix_np_2/nbproject/configurations.xml
+++ b/miosix_np_2/nbproject/configurations.xml
@@ -167,7 +167,7 @@
</df>
<in>board_settings.h</in>
</df>
- <df name="stm32f207ze_camboard">
+ <df name="stm32f207ze_als_camboard">
<df name="core">
<in>stage_1_boot.cpp</in>
</df>
@@ -196,6 +196,47 @@
<in>board_settings.h</in>
</df>
</df>
+ <df name="cortexM3_stm32l1">
+ <df name="common">
+ <df name="CMSIS">
+ <df name="Documentation">
+ </df>
+ <in>core_cm3.h</in>
+ <in>core_cmFunc.h</in>
+ <in>core_cmInstr.h</in>
+ <in>stm32l1xx.h</in>
+ <in>system_stm32l1xx.c</in>
+ <in>system_stm32l1xx.h</in>
+ </df>
+ <df name="core">
+ <in>interrupts.cpp</in>
+ <in>interrupts.h</in>
+ </df>
+ <df name="interfaces-impl">
+ <in>arch_registers_impl.h</in>
+ <in>delays.cpp</in>
+ <in>endianness_impl.h</in>
+ <in>gpio_impl.cpp</in>
+ <in>gpio_impl.h</in>
+ <in>portability.cpp</in>
+ <in>portability_impl.h</in>
+ </df>
+ <in>arch_settings.h</in>
+ </df>
+ <df name="stm32l151c8_als_mainboard">
+ <df name="core">
+ <in>stage_1_boot.cpp</in>
+ </df>
+ <df name="interfaces-impl">
+ <in>bsp.cpp</in>
+ <in>bsp_impl.h</in>
+ <in>console-impl.h</in>
+ <in>console.cpp</in>
+ <in>hwmapping.h</in>
+ </df>
+ <in>board_settings.h</in>
+ </df>
+ </df>
<df name="cortexM4_stm32f4">
<df name="common">
<df name="CMSIS">
@@ -338,8 +379,6 @@
<df name="miosix_np_2">
</df>
<in>main.cpp</in>
- <in>sha1.cpp</in>
- <in>sha1.h</in>
</df>
<logicalFolder name="ExternalFiles"
displayName="Important Files"
@@ -808,5 +847,93 @@
</makeTool>
</makefileType>
</conf>
+ <conf name="stm32f207ze_als_camboard" type="0">
+ <toolsSet>
+ <remote-sources-mode>LOCAL_SOURCES</remote-sources-mode>
+ <compilerSet>ARM_MIOSIX_EABI|GNU</compilerSet>
+ </toolsSet>
+ <makefileType>
+ <makeTool>
+ <buildCommandWorkingDir>..</buildCommandWorkingDir>
+ <buildCommand>${MAKE} -f Makefile</buildCommand>
+ <cleanCommand>${MAKE} -f Makefile clean</cleanCommand>
+ <executablePath></executablePath>
+ <cTool>
+ <incDir>
+ <pElem>..</pElem>
+ <pElem>../miosix</pElem>
+ <pElem>../miosix/arch/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32f2/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard </pElem>
+ </incDir>
+ <preprocessorList>
+ <Elem>_ARCH_CORTEXM3_STM32F2</Elem>
+ <Elem>_BOARD_ALS_CAMBOARD</Elem>
+ <Elem>_MIOSIX</Elem>
+ <Elem>_POSIX_THREADS</Elem>
+ </preprocessorList>
+ </cTool>
+ <ccTool>
+ <incDir>
+ <pElem>..</pElem>
+ <pElem>../miosix</pElem>
+ <pElem>../miosix/arch/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32f2/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard </pElem>
+ </incDir>
+ <preprocessorList>
+ <Elem>_ARCH_CORTEXM3_STM32F2</Elem>
+ <Elem>_BOARD_ALS_CAMBOARD</Elem>
+ <Elem>_MIOSIX</Elem>
+ <Elem>_POSIX_THREADS</Elem>
+ </preprocessorList>
+ </ccTool>
+ </makeTool>
+ </makefileType>
+ </conf>
+ <conf name="stm32l151c8_als_mainboard" type="0">
+ <toolsSet>
+ <remote-sources-mode>LOCAL_SOURCES</remote-sources-mode>
+ <compilerSet>ARM_MIOSIX_EABI|GNU</compilerSet>
+ </toolsSet>
+ <makefileType>
+ <makeTool>
+ <buildCommandWorkingDir>..</buildCommandWorkingDir>
+ <buildCommand>${MAKE} -f Makefile</buildCommand>
+ <cleanCommand>${MAKE} -f Makefile clean</cleanCommand>
+ <executablePath></executablePath>
+ <cTool>
+ <incDir>
+ <pElem>..</pElem>
+ <pElem>../miosix</pElem>
+ <pElem>../miosix/arch/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32l1/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard </pElem>
+ </incDir>
+ <preprocessorList>
+ <Elem>_ARCH_CORTEXM3_STM32L1</Elem>
+ <Elem>_BOARD_ALS_MAINBOARD</Elem>
+ <Elem>_MIOSIX</Elem>
+ <Elem>_POSIX_THREADS</Elem>
+ </preprocessorList>
+ </cTool>
+ <ccTool>
+ <incDir>
+ <pElem>..</pElem>
+ <pElem>../miosix</pElem>
+ <pElem>../miosix/arch/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32l1/common</pElem>
+ <pElem>../miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard </pElem>
+ </incDir>
+ <preprocessorList>
+ <Elem>_ARCH_CORTEXM3_STM32L1</Elem>
+ <Elem>_BOARD_ALS_MAINBOARD</Elem>
+ <Elem>_MIOSIX</Elem>
+ <Elem>_POSIX_THREADS</Elem>
+ </preprocessorList>
+ </ccTool>
+ </makeTool>
+ </makefileType>
+ </conf>
</confs>
</configurationDescriptor>
diff --git a/miosix_np_2/nbproject/private/configurations.xml b/miosix_np_2/nbproject/private/configurations.xml
index ad5c7713..feef40cf 100644
--- a/miosix_np_2/nbproject/private/configurations.xml
+++ b/miosix_np_2/nbproject/private/configurations.xml
@@ -332,5 +332,71 @@
</environment>
</runprofile>
</conf>
+ <conf name="stm32f207ze_als_camboard" type="0">
+ <toolsSet>
+ <developmentServer>localhost</developmentServer>
+ <platform>2</platform>
+ </toolsSet>
+ <dbx_gdbdebugger version="1">
+ <gdb_pathmaps>
+ </gdb_pathmaps>
+ <gdb_interceptlist>
+ <gdbinterceptoptions gdb_all="false" gdb_unhandled="true" gdb_unexpected="true"/>
+ </gdb_interceptlist>
+ <gdb_options>
+ <DebugOptions>
+ </DebugOptions>
+ </gdb_options>
+ <gdb_buildfirst gdb_buildfirst_overriden="false" gdb_buildfirst_old="false"/>
+ </dbx_gdbdebugger>
+ <nativedebugger version="1">
+ <engine>gdb</engine>
+ </nativedebugger>
+ <runprofile version="9">
+ <runcommandpicklist>
+ <runcommandpicklistitem>"${OUTPUT_PATH}"</runcommandpicklistitem>
+ </runcommandpicklist>
+ <runcommand>"${OUTPUT_PATH}"</runcommand>
+ <rundir></rundir>
+ <buildfirst>true</buildfirst>
+ <terminal-type>0</terminal-type>
+ <remove-instrumentation>0</remove-instrumentation>
+ <environment>
+ </environment>
+ </runprofile>
+ </conf>
+ <conf name="stm32l151c8_als_mainboard" type="0">
+ <toolsSet>
+ <developmentServer>localhost</developmentServer>
+ <platform>2</platform>
+ </toolsSet>
+ <dbx_gdbdebugger version="1">
+ <gdb_pathmaps>
+ </gdb_pathmaps>
+ <gdb_interceptlist>
+ <gdbinterceptoptions gdb_all="false" gdb_unhandled="true" gdb_unexpected="true"/>
+ </gdb_interceptlist>
+ <gdb_options>
+ <DebugOptions>
+ </DebugOptions>
+ </gdb_options>
+ <gdb_buildfirst gdb_buildfirst_overriden="false" gdb_buildfirst_old="false"/>
+ </dbx_gdbdebugger>
+ <nativedebugger version="1">
+ <engine>gdb</engine>
+ </nativedebugger>
+ <runprofile version="9">
+ <runcommandpicklist>
+ <runcommandpicklistitem>"${OUTPUT_PATH}"</runcommandpicklistitem>
+ </runcommandpicklist>
+ <runcommand>"${OUTPUT_PATH}"</runcommand>
+ <rundir></rundir>
+ <buildfirst>true</buildfirst>
+ <terminal-type>0</terminal-type>
+ <remove-instrumentation>0</remove-instrumentation>
+ <environment>
+ </environment>
+ </runprofile>
+ </conf>
</confs>
</configurationDescriptor>
diff --git a/miosix_np_2/nbproject/private/private.xml b/miosix_np_2/nbproject/private/private.xml
index e67bac43..42a20b90 100644
--- a/miosix_np_2/nbproject/private/private.xml
+++ b/miosix_np_2/nbproject/private/private.xml
@@ -5,7 +5,7 @@
</code-assistance-data>
<data xmlns="http://www.netbeans.org/ns/make-project-private/1">
<activeConfTypeElem>0</activeConfTypeElem>
- <activeConfIndexElem>9</activeConfIndexElem>
+ <activeConfIndexElem>11</activeConfIndexElem>
</data>
<editor-bookmarks xmlns="http://www.netbeans.org/ns/editor-bookmarks/1"/>
</project-private>
diff --git a/miosix_np_2/nbproject/project.xml b/miosix_np_2/nbproject/project.xml
index a277459d..d113a248 100644
--- a/miosix_np_2/nbproject/project.xml
+++ b/miosix_np_2/nbproject/project.xml
@@ -54,6 +54,14 @@
<name>stm32f207zg_ethboard_v2</name>
<type>0</type>
</confElem>
+ <confElem>
+ <name>stm32f207ze_als_camboard</name>
+ <type>0</type>
+ </confElem>
+ <confElem>
+ <name>stm32l151c8_als_mainboard</name>
+ <type>0</type>
+ </confElem>
</confList>
</data>
</configuration>
--
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