From 5193a4dedb5174ff7fdbfda3a6bc15e2ca704c9d Mon Sep 17 00:00:00 2001 From: Terraneo Federico <fede.tft@miosix.org> Date: Thu, 9 Jan 2025 18:50:57 +0100 Subject: [PATCH] Clear fault interrupt flags to fix the address causing the fault being stuck after the first fault, and remove wrong leftover IRQinvokeScheduler --- miosix/arch/cpu/common/cortexMx_interrupts.cpp | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/miosix/arch/cpu/common/cortexMx_interrupts.cpp b/miosix/arch/cpu/common/cortexMx_interrupts.cpp index 9de478f0..6d3ce34c 100644 --- a/miosix/arch/cpu/common/cortexMx_interrupts.cpp +++ b/miosix/arch/cpu/common/cortexMx_interrupts.cpp @@ -460,6 +460,8 @@ void MemManage_Handler() if(Thread::IRQreportFault(FaultData(id,getProgramCounter(),arg))) { SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit + //Clear MMARVALID, MLSPERR, MSTKERR, MUNSTKERR, DACCVIOL, IACCVIOL + SCB->CFSR = 0x000000bb; return; } #endif //WITH_PROCESSES @@ -506,7 +508,8 @@ void BusFault_Handler() if(Thread::IRQreportFault(FaultData(id,getProgramCounter(),arg))) { SCB->SHCSR &= ~(1<<14); //Clear BUSFAULTPENDED bit - IRQinvokeScheduler(); + //Clear BFARVALID, LSPERR, STKERR, UNSTKERR, IMPRECISERR, PRECISERR, IBUSERR + SCB->CFSR = 0x0000bf00; return; } #endif //WITH_PROCESSES @@ -560,6 +563,8 @@ void UsageFault_Handler() if(Thread::IRQreportFault(FaultData(id,getProgramCounter()))) { SCB->SHCSR &= ~(1<<12); //Clear USGFAULTPENDED bit + //Clear DIVBYZERO, UNALIGNED, UNDEFINSTR, INVSTATE, INVPC, NOCP + SCB->CFSR = 0x030f0000; return; } #endif //WITH_PROCESSES -- GitLab