diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c index e601b9c20f6ae7afa19cda4db23b21230da80429..5a61c6422801db2bb8b2745f6482696e6bc659e3 100644 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c +++ b/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c @@ -99,7 +99,11 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ +#ifdef SYSCLK_FREQ_32MHz +uint32_t SystemCoreClock = 32000000; +#else uint32_t SystemCoreClock = 8000000; +#endif const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; @@ -127,6 +131,22 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; */ void SystemInit(void) { + //TODO: support more clocking options + #ifdef SYSCLK_FREQ_32MHz + RCC->CR |= RCC_CR_HSION; + while((RCC->CR & RCC_CR_HSIRDY)==0) ; + RCC->CR &= ~RCC_CR_PLLON; + while(RCC->CR & RCC_CR_PLLRDY) ; + RCC->CFGR &= ~RCC_CFGR_SW; //Selects HSI + RCC->CFGR = RCC_CFGR_PLLMUL4 //4*8=32MHz + | RCC_CFGR_PLLSRC_HSI_PREDIV; + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY)==0) ; + FLASH->ACR &= ~FLASH_ACR_LATENCY; + FLASH->ACR |= 1; //1 wait state for freq > 24MHz + RCC->CFGR |= RCC_CFGR_SW_PLL; + #endif + /* NOTE :SystemInit(): This function is called at startup just after reset and before branch to main program. This call is made inside the "startup_stm32f0xx.s" file. diff --git a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp index d59faca190ba053718031219b3c5b52d407f6c3a..fb224836178e6867ce5b6055cdfe93ed837696d3 100644 --- a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp +++ b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp @@ -27,18 +27,14 @@ #include "interfaces/delays.h" +#warning "TODO Delays only coarsely calibrated" + namespace miosix { void delayMs(unsigned int mseconds) { - #ifdef SYSCLK_FREQ_48MHz - register const unsigned int count=9600; - #elif SYSCLK_FREQ_36MHz - register const unsigned int count=7200; - #elif SYSCLK_FREQ_24MHz - register const unsigned int count=6000; - #else - register const unsigned int count=2016; + #ifdef SYSCLK_FREQ_32MHz + register const unsigned int count=6400; #endif for(unsigned int i=0;i<mseconds;i++) @@ -58,16 +54,8 @@ void delayUs(unsigned int useconds) { // This delay has been calibrated to take x microseconds // It is written in assembler to be independent on compiler optimizations - #ifdef SYSCLK_FREQ_48MHz - #error "delayUs not implemented" - - #elif SYSCLK_FREQ_36MHz - #error "delayUs not implemented" - - #elif SYSCLK_FREQ_24MHz - #error "delayUs not implemented" - #else - asm volatile(" mov r1, #2 \n" + #ifdef SYSCLK_FREQ_32MHz + asm volatile(" mov r1, #3 \n" " mul r1, %0, r1 \n" " mov r2, #0 \n" "___loop_u: cmp r2, r1 \n" @@ -75,6 +63,8 @@ void delayUs(unsigned int useconds) " add r2, r2, #1 \n" " b ___loop_u \n" "__loop_u_exit: \n"::"r"(useconds):"r1","r2"); + #else + #error "delayUs not implemented" #endif } diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc index c591e9942d14a4d317a51dbce963532100be8e1e..3e9a51ed7aeda11ad9579744dc23ee4cab14dcd6 100644 --- a/miosix/config/Makefile.inc +++ b/miosix/config/Makefile.inc @@ -2530,7 +2530,7 @@ else ifeq ($(ARCH),cortexM0_stm32f0) CXXFLAGS_BASE += -D_BOARD_STM32F072RB_DISCO -DSTM32F072xB ## Select clock frequency - CLOCK_FREQ := -DHSI_VALUE=8000000 -DSYSCLK_FREQ_8MHz=8000000 + CLOCK_FREQ := -DSYSCLK_FREQ_32MHz=32000000 ## Select programmer command line ## This is the program that is invoked when the user types