From 54e1d3a073f00476a25821f55f6a817256d2d178 Mon Sep 17 00:00:00 2001
From: Terraneo Federico <fede.tft@miosix.org>
Date: Sun, 8 Sep 2019 15:59:44 +0200
Subject: [PATCH] Miosix makefile support for GCC 9.2.0, moved to C++14
---
Makefile | 5 ++--
miosix/Makefile | 4 ++-
miosix/config/Makefile.inc | 57 +++++++++++++++++++++-----------------
3 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/Makefile b/Makefile
index c7f35af5..976d2b3f 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,9 @@
##
## Makefile for Miosix embedded OS
##
-MAKEFILE_VERSION := 1.07
+MAKEFILE_VERSION := 1.08
+GCCMAJOR := $(shell arm-miosix-eabi-gcc --version | \
+ perl -e '$$_=<>;/\(GCC\) (\d+)/;print "$$1"')
## Path to kernel directory (edited by init_project_out_of_git_repo.pl)
KPATH := miosix
## Path to config directory (edited by init_project_out_of_git_repo.pl)
@@ -59,7 +61,6 @@ DFLAGS := -MMD -MP
## libmiosix.a is among stdlibs because needs to be within start/end group
STDLIBS := -lmiosix -lstdc++ -lc -lm -lgcc
-GCCMAJOR := $(shell $(CC) --version | perl -e '$$_=<>;/\(GCC\) (\d+)/;print "$$1"')
ifneq ($(GCCMAJOR),4)
STDLIBS += -latomic
endif
diff --git a/miosix/Makefile b/miosix/Makefile
index d0c7b0c3..b596e21d 100644
--- a/miosix/Makefile
+++ b/miosix/Makefile
@@ -2,7 +2,9 @@
## Makefile for Miosix embedded OS
## This makefile builds the whole kernel
##
-MAKEFILE_VERSION := 1.07
+MAKEFILE_VERSION := 1.08
+GCCMAJOR := $(shell arm-miosix-eabi-gcc --version | \
+ perl -e '$$_=<>;/\(GCC\) (\d+)/;print "$$1"')
## KPATH and CONFPATH are forwarded by the parent Makefile
include $(CONFPATH)/config/Makefile.inc
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index a449009e..dbaf00d0 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -539,7 +539,7 @@ endif
## a new board or porting Miosix to a new architecture ##
############################################################################
-ifneq ($(MAKEFILE_VERSION),1.07)
+ifneq ($(MAKEFILE_VERSION),1.08)
$(info You are using an incompatible makefile. Make sure it matches \
the one distributed with the current version of the kernel)
$(error Error)
@@ -625,10 +625,15 @@ endif
##
## Then, initialize C/C++ flags
##
-CFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" \
- -ffunction-sections -Wno-unused-but-set-variable -Wall -g
-CXXFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" -std=gnu++11 \
- -ffunction-sections -Wno-unused-but-set-variable -Wall -g
+ifneq ($(GCCMAJOR),4)
+ CXXSTD := -std=c++14
+else
+ CXXSTD := -std=gnu++11
+endif
+CFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" -D_DEFAULT_SOURCE \
+ -ffunction-sections -Wall -g
+CXXFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" -D_DEFAULT_SOURCE \
+ $(CXXSTD) -ffunction-sections -Wall -g
##
## Now two big switch-like constructs nested. The first lists all possible
@@ -1920,7 +1925,7 @@ else ifeq ($(ARCH),cortexM3_efm32gg)
## Add a #define to allow querying board name
CFLAGS_BASE += -DEFM32GG332F1024 -D_BOARD_WANDSTEM
- CXXFLAGS_BASE += $(CFLAGS_BASE)
+ CXXFLAGS_BASE += -DEFM32GG332F1024 -D_BOARD_WANDSTEM
## Clock frequency
CLOCK_FREQ := -DEFM32_HFXO_FREQ=48000000 -DEFM32_LFXO_FREQ=32768
@@ -2031,18 +2036,18 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
SZ := $(PREFIX)size
## Select appropriate compiler flags for both ASM/C/C++/linker
- ## TODO: when upgrading compiler, add native cortex M7 support.
- ## For now we'll fallback to M4 which is compatible, but does not support
- ## double precision HW floating point
- AFLAGS_BASE := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ ifneq ($(GCCMAJOR),4)
+ ARCHOPTS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16
+ else
+ ## Fallback to cortex M4 and single precision fp, which is compatible
+ ARCHOPTS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ endif
+ AFLAGS_BASE := $(ARCHOPTS)
CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- $(OPT_OPTIMIZATION) -c
+ $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
- LFLAGS_BASE := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- -Wl,--gc-sections,-Map,main.map \
+ $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
+ LFLAGS_BASE := $(ARCHOPTS) -Wl,--gc-sections,-Map,main.map \
-Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
$(OPT_OPTIMIZATION) -nostdlib
@@ -2119,18 +2124,18 @@ else ifeq ($(ARCH),cortexM7_stm32h7)
SZ := $(PREFIX)size
## Select appropriate compiler flags for both ASM/C/C++/linker
- ## TODO: when upgrading compiler, add native cortex M7 support.
- ## For now we'll fallback to M4 which is compatible, but does not support
- ## double precision HW floating point
- AFLAGS_BASE := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ ifneq ($(GCCMAJOR),4)
+ ARCHOPTS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16
+ else
+ ## Fallback to cortex M4 and single precision fp, which is compatible
+ ARCHOPTS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16
+ endif
+ AFLAGS_BASE := $(ARCHOPTS)
CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32H7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- $(OPT_OPTIMIZATION) -c
+ $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32H7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
- LFLAGS_BASE := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 \
- -Wl,--gc-sections,-Map,main.map \
+ $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
+ LFLAGS_BASE := $(ARCHOPTS) -Wl,--gc-sections,-Map,main.map \
-Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
$(OPT_OPTIMIZATION) -nostdlib
--
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