From 5c8abdd1ab17b3f80061f51957b03ebd2725cbd8 Mon Sep 17 00:00:00 2001
From: Matteo Franceschini <teo.franceschini@gmail.com>
Date: Fri, 5 Oct 2018 01:14:29 +0200
Subject: [PATCH] [ADD]Aggiunto BSP Alderaan Board Skyward
Signed-off-by: Matteo Franceschini <teo.franceschini@gmail.com>
---
.../core/stage_1_boot.cpp | 268 ++++++++++++++++++
.../interfaces-impl/bsp.cpp | 158 +++++++++++
.../interfaces-impl/bsp_impl.h | 82 ++++++
.../interfaces-impl/hwmapping.h | 77 +++++
.../stm32_64k+20k_rom.ld | 170 +++++++++++
.../stm32vldiscovery.cfg | 27 ++
miosix/config/Makefile.inc | 54 ++++
.../board_settings.h | 86 ++++++
8 files changed, 922 insertions(+)
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/core/stage_1_boot.cpp
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp.cpp
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp_impl.h
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/hwmapping.h
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_64k+20k_rom.ld
create mode 100644 miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32vldiscovery.cfg
create mode 100644 miosix/config/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/board_settings.h
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/core/stage_1_boot.cpp
new file mode 100644
index 00000000..4729a585
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/core/stage_1_boot.cpp
@@ -0,0 +1,268 @@
+
+#include "interfaces/arch_registers.h"
+#include "core/interrupts.h" //For the unexpected interrupt call
+#include <string.h>
+
+/*
+ * startup.cpp
+ * STM32 C++ startup.
+ * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices).
+ * Supports interrupt handlers in C++ without extern "C"
+ * Developed by Terraneo Federico, based on ST startup code.
+ * Additionally modified to boot Miosix.
+ */
+
+//Will be called at the end of stage 1 of boot, function is implemented in
+//stage_2_boot.cpp
+extern "C" void _init();
+
+/**
+ * Called by Reset_Handler, performs initialization and calls main.
+ * Never returns.
+ */
+void program_startup() __attribute__((noreturn));
+void program_startup()
+{
+ //Cortex M3 core appears to get out of reset with interrupts already enabled
+ __disable_irq();
+
+ //SystemInit() is called *before* initializing .data and zeroing .bss
+ //Despite all startup files provided by ST do the opposite, there are three
+ //good reasons to do so:
+ //First, the CMSIS specifications say that SystemInit() must not access
+ //global variables, so it is actually possible to call it before
+ //Second, when running Miosix with the xram linker scripts .data and .bss
+ //are placed in the external RAM, so we *must* call SystemInit(), which
+ //enables xram, before touching .data and .bss
+ //Third, this is a performance improvement since the loops that initialize
+ //.data and zeros .bss now run with the CPU at full speed instead of 8MHz
+ SystemInit();
+
+ //These are defined in the linker script
+ extern unsigned char _etext asm("_etext");
+ extern unsigned char _data asm("_data");
+ extern unsigned char _edata asm("_edata");
+ extern unsigned char _bss_start asm("_bss_start");
+ extern unsigned char _bss_end asm("_bss_end");
+
+ //Initialize .data section, clear .bss section
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ memcpy(data, etext, edata-data);
+ memset(bss_start, 0, bss_end-bss_start);
+
+ //Move on to stage 2
+ _init();
+
+ //If main returns, reboot
+ NVIC_SystemReset();
+ for(;;) ;
+}
+
+/**
+ * Reset handler, called by hardware immediately after reset
+ */
+void Reset_Handler() __attribute__((__interrupt__, noreturn));
+void Reset_Handler()
+{
+ /*
+ * Initialize process stack and switch to it.
+ * This is required for booting Miosix, a small portion of the top of the
+ * heap area will be used as stack until the first thread starts. After,
+ * this stack will be abandoned and the process stack will point to the
+ * current thread's stack.
+ */
+ asm volatile("ldr r0, =_heap_end \n\t"
+ "msr psp, r0 \n\t"
+ "movw r0, #2 \n\n" //Privileged, process stack
+ "msr control, r0 \n\t"
+ "isb \n\t":::"r0");
+
+ program_startup();
+}
+
+/**
+ * All unused interrupts call this function.
+ */
+extern "C" void Default_Handler()
+{
+ unexpectedInterrupt();
+}
+
+//System handlers
+void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
+void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
+void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
+void /*__attribute__((weak))*/ MemManage_Handler();
+void /*__attribute__((weak))*/ BusFault_Handler();
+void /*__attribute__((weak))*/ UsageFault_Handler();
+void /*__attribute__((weak))*/ SVC_Handler();
+void /*__attribute__((weak))*/ DebugMon_Handler();
+void /*__attribute__((weak))*/ PendSV_Handler();
+void /*__attribute__((weak))*/ SysTick_Handler();
+
+//Interrupt handlers
+void __attribute__((weak)) WWDG_IRQHandler();
+void __attribute__((weak)) PVD_IRQHandler();
+void __attribute__((weak)) TAMPER_IRQHandler();
+void __attribute__((weak)) RTC_IRQHandler();
+void __attribute__((weak)) FLASH_IRQHandler();
+void __attribute__((weak)) RCC_IRQHandler();
+void __attribute__((weak)) EXTI0_IRQHandler();
+void __attribute__((weak)) EXTI1_IRQHandler();
+void __attribute__((weak)) EXTI2_IRQHandler();
+void __attribute__((weak)) EXTI3_IRQHandler();
+void __attribute__((weak)) EXTI4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel1_IRQHandler();
+void __attribute__((weak)) DMA1_Channel2_IRQHandler();
+void __attribute__((weak)) DMA1_Channel3_IRQHandler();
+void __attribute__((weak)) DMA1_Channel4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel5_IRQHandler();
+void __attribute__((weak)) DMA1_Channel6_IRQHandler();
+void __attribute__((weak)) DMA1_Channel7_IRQHandler();
+void __attribute__((weak)) ADC1_2_IRQHandler();
+void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler();
+void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler();
+void __attribute__((weak)) CAN1_RX1_IRQHandler();
+void __attribute__((weak)) CAN1_SCE_IRQHandler();
+void __attribute__((weak)) EXTI9_5_IRQHandler();
+void __attribute__((weak)) TIM1_BRK_IRQHandler();
+void __attribute__((weak)) TIM1_UP_IRQHandler();
+void __attribute__((weak)) TIM1_TRG_COM_IRQHandler();
+void __attribute__((weak)) TIM1_CC_IRQHandler();
+void __attribute__((weak)) TIM2_IRQHandler();
+void __attribute__((weak)) TIM3_IRQHandler();
+void __attribute__((weak)) TIM4_IRQHandler();
+void __attribute__((weak)) I2C1_EV_IRQHandler();
+void __attribute__((weak)) I2C1_ER_IRQHandler();
+void __attribute__((weak)) I2C2_EV_IRQHandler();
+void __attribute__((weak)) I2C2_ER_IRQHandler();
+void __attribute__((weak)) SPI1_IRQHandler();
+void __attribute__((weak)) SPI2_IRQHandler();
+void __attribute__((weak)) USART1_IRQHandler();
+void __attribute__((weak)) USART2_IRQHandler();
+void __attribute__((weak)) USART3_IRQHandler();
+void __attribute__((weak)) EXTI15_10_IRQHandler();
+void __attribute__((weak)) RTC_Alarm_IRQHandler();
+void __attribute__((weak)) USBWakeUp_IRQHandler();
+
+//Stack top, defined in the linker script
+extern char _main_stack_top asm("_main_stack_top");
+
+//Interrupt vectors, must be placed @ address 0x00000000
+//The extern declaration is required otherwise g++ optimizes it out
+extern void (* const __Vectors[])();
+void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
+{
+ reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External Interrupts */
+ WWDG_IRQHandler,
+ PVD_IRQHandler,
+ TAMPER_IRQHandler,
+ RTC_IRQHandler,
+ FLASH_IRQHandler,
+ RCC_IRQHandler,
+ EXTI0_IRQHandler,
+ EXTI1_IRQHandler,
+ EXTI2_IRQHandler,
+ EXTI3_IRQHandler,
+ EXTI4_IRQHandler,
+ DMA1_Channel1_IRQHandler,
+ DMA1_Channel2_IRQHandler,
+ DMA1_Channel3_IRQHandler,
+ DMA1_Channel4_IRQHandler,
+ DMA1_Channel5_IRQHandler,
+ DMA1_Channel6_IRQHandler,
+ DMA1_Channel7_IRQHandler,
+ ADC1_2_IRQHandler,
+ USB_HP_CAN1_TX_IRQHandler,
+ USB_LP_CAN1_RX0_IRQHandler,
+ CAN1_RX1_IRQHandler,
+ CAN1_SCE_IRQHandler,
+ EXTI9_5_IRQHandler,
+ TIM1_BRK_IRQHandler,
+ TIM1_UP_IRQHandler,
+ TIM1_TRG_COM_IRQHandler,
+ TIM1_CC_IRQHandler,
+ TIM2_IRQHandler,
+ TIM3_IRQHandler,
+ TIM4_IRQHandler,
+ I2C1_EV_IRQHandler,
+ I2C1_ER_IRQHandler,
+ I2C2_EV_IRQHandler,
+ I2C2_ER_IRQHandler,
+ SPI1_IRQHandler,
+ SPI2_IRQHandler,
+ USART1_IRQHandler,
+ USART2_IRQHandler,
+ USART3_IRQHandler,
+ EXTI15_10_IRQHandler,
+ RTC_Alarm_IRQHandler,
+ USBWakeUp_IRQHandler,
+ 0,0,0,0,0,0,0,
+ reinterpret_cast<void (*)()>(0xF108F85F) /* @0x1E0. This is for boot in RAM mode for
+ STM32F10x Medium Value Line Density devices.*/
+};
+
+#pragma weak WWDG_IRQHandler = Default_Handler
+#pragma weak PVD_IRQHandler = Default_Handler
+#pragma weak TAMPER_IRQHandler = Default_Handler
+#pragma weak RTC_IRQHandler = Default_Handler
+#pragma weak FLASH_IRQHandler = Default_Handler
+#pragma weak RCC_IRQHandler = Default_Handler
+#pragma weak EXTI0_IRQHandler = Default_Handler
+#pragma weak EXTI1_IRQHandler = Default_Handler
+#pragma weak EXTI2_IRQHandler = Default_Handler
+#pragma weak EXTI3_IRQHandler = Default_Handler
+#pragma weak EXTI4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel1_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel2_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel3_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel5_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel6_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel7_IRQHandler = Default_Handler
+#pragma weak ADC1_2_IRQHandler = Default_Handler
+#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler
+#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler
+#pragma weak CAN1_RX1_IRQHandler = Default_Handler
+#pragma weak CAN1_SCE_IRQHandler = Default_Handler
+#pragma weak EXTI9_5_IRQHandler = Default_Handler
+#pragma weak TIM1_BRK_IRQHandler = Default_Handler
+#pragma weak TIM1_UP_IRQHandler = Default_Handler
+#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler
+#pragma weak TIM1_CC_IRQHandler = Default_Handler
+#pragma weak TIM2_IRQHandler = Default_Handler
+#pragma weak TIM3_IRQHandler = Default_Handler
+#pragma weak TIM4_IRQHandler = Default_Handler
+#pragma weak I2C1_EV_IRQHandler = Default_Handler
+#pragma weak I2C1_ER_IRQHandler = Default_Handler
+#pragma weak I2C2_EV_IRQHandler = Default_Handler
+#pragma weak I2C2_ER_IRQHandler = Default_Handler
+#pragma weak SPI1_IRQHandler = Default_Handler
+#pragma weak SPI2_IRQHandler = Default_Handler
+#pragma weak USART1_IRQHandler = Default_Handler
+#pragma weak USART2_IRQHandler = Default_Handler
+#pragma weak USART3_IRQHandler = Default_Handler
+#pragma weak EXTI15_10_IRQHandler = Default_Handler
+#pragma weak RTC_Alarm_IRQHandler = Default_Handler
+#pragma weak USBWakeUp_IRQHandler = Default_Handler
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp.cpp
new file mode 100644
index 00000000..865416f5
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp.cpp
@@ -0,0 +1,158 @@
+/***************************************************************************
+ * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp.cpp Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+#include <cstdlib>
+#include <inttypes.h>
+#include <sys/ioctl.h>
+#include "interfaces/bsp.h"
+#include "kernel/kernel.h"
+#include "kernel/sync.h"
+#include "interfaces/delays.h"
+#include "interfaces/portability.h"
+#include "interfaces/arch_registers.h"
+#include "config/miosix_settings.h"
+#include "kernel/logging.h"
+#include "filesystem/file_access.h"
+#include "filesystem/console/console_device.h"
+#include "drivers/serial.h"
+#include "drivers/dcc.h"
+#include "board_settings.h"
+#include "hwmapping.h"
+
+namespace miosix {
+
+//
+// Initialization
+//
+
+void IRQbspInit()
+{
+ //Enable all gpios
+ RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN |
+ RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN |
+ RCC_APB2ENR_AFIOEN;
+ RCC_SYNC();
+
+
+ //PORT INITIALIZATION
+ using namespace interfaces;
+ spi1::sck::mode(Mode::OUTPUT);
+ spi1::miso::mode(Mode::INPUT);
+ spi1::mosi::mode(Mode::OUTPUT);
+
+ uart1::tx::mode(Mode::OUTPUT);
+ uart1::rx::mode(Mode::INPUT);
+
+ can::rx::mode(Mode::INPUT);
+ can::tx::mode(Mode::OUTPUT);
+
+ using namespace actuators;
+ abort1::mode(Mode::OUTPUT);
+ ignition1::mode(Mode::OUTPUT);
+ spare::mode(Mode::OUTPUT); //non sicuro se input o output
+
+#warning RICORDARSI DI TOGLIERE IL LED IN BOOT!!
+ _led::mode(Mode::OUTPUT_2MHz);
+ ledOn();
+ delayMs(100);
+ ledOff();
+ DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>(
+ #ifndef STDOUT_REDIRECTED_TO_DCC
+ new STM32Serial(defaultSerial,defaultSerialSpeed,
+ defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL)));
+ #else //STDOUT_REDIRECTED_TO_DCC
+ new ARMDCC();
+ #endif //STDOUT_REDIRECTED_TO_DCC
+}
+
+void bspInit2()
+{
+// #ifdef WITH_FILESYSTEM
+// basicFilesystemSetup();
+// #endif //WITH_FILESYSTEM
+}
+
+//
+// Shutdown and reboot
+//
+
+/**
+This function disables filesystem (if enabled), serial port (if enabled) and
+puts the processor in deep sleep mode.<br>
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens.
+<br>This function does not return.<br>
+WARNING: close all files before using this function, since it unmounts the
+filesystem.<br>
+When in shutdown mode, power consumption of the miosix board is reduced to ~
+5uA??, however, true power consumption depends on what is connected to the GPIO
+pins. The user is responsible to put the devices connected to the GPIO pin in the
+minimal power consumption mode before calling shutdown(). Please note that to
+minimize power consumption all unused GPIO must not be left floating.
+*/
+void shutdown()
+{
+ ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
+
+ #ifdef WITH_FILESYSTEM
+ FilesystemManager::instance().umountAll();
+ #endif //WITH_FILESYSTEM
+
+ disableInterrupts();
+
+ /*
+ Removed because low power mode causes issues with SWD programming
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating...
+ RCC_SYNC();
+ PWR->CR |= PWR_CR_PDDS; //Select standby mode
+ PWR->CR |= PWR_CR_CWUF;
+ PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source
+
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+ __WFE();
+ NVIC_SystemReset();
+ */
+ for(;;) ;
+}
+
+void reboot()
+{
+ ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
+
+ #ifdef WITH_FILESYSTEM
+ FilesystemManager::instance().umountAll();
+ #endif //WITH_FILESYSTEM
+
+ disableInterrupts();
+ miosix_private::IRQsystemReboot();
+}
+
+} //namespace miosix
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp_impl.h
new file mode 100644
index 00000000..d5b877cc
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/bsp_impl.h
@@ -0,0 +1,82 @@
+/***************************************************************************
+ * Copyright (C) 2011 by Terraneo Federico *
+ * Copyright (C) 2016 by Silvano Seva *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp_impl.h Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+#ifndef BSP_IMPL_H
+#define BSP_IMPL_H
+
+#include "config/miosix_settings.h"
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+/**
+\addtogroup Hardware
+\{
+*/
+
+/**
+ * \internal
+ * used by the ledOn() and ledOff() implementation
+ */
+typedef Gpio<GPIOA_BASE,1> _led;
+
+inline void ledOn()
+{
+ _led::high();
+}
+
+inline void ledOff()
+{
+ _led::low();
+}
+
+///\internal Pin connected to SD card detect
+//TODO: no filesystem typedef Gpio<GPIOA_BASE,8> sdCardDetect;
+
+/**
+ * Polls the SD card sense GPIO
+ * \return true if there is an uSD card in the socket.
+ */
+/*TODO: no filesystem
+inline bool sdCardSense()
+{
+ return sdCardDetect::value()==0;
+}*/
+
+/**
+\}
+*/
+
+} //namespace miosix
+
+#endif //BSP_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/hwmapping.h
new file mode 100644
index 00000000..00ae4a06
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/interfaces-impl/hwmapping.h
@@ -0,0 +1,77 @@
+/***************************************************************************
+ * Copyright (C) 2018 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef HWMAPPING_H
+#define HWMAPPING_H
+
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+namespace interfaces
+{
+
+ namespace spi1 {
+ using sck = Gpio<GPIOA_BASE, 5>;
+ using miso = Gpio<GPIOA_BASE, 6>;
+ using mosi = Gpio<GPIOA_BASE, 7>;
+ } //namespace spi1
+
+ namespace spi2 {
+ using sck = Gpio<GPIOB_BASE, 13>;
+ using miso = Gpio<GPIOB_BASE, 14>;
+ using mosi = Gpio<GPIOB_BASE, 15>;
+ } //namespace spi2 [non usato]
+
+ namespace i2c {
+ using scl = Gpio<GPIOB_BASE, 8>;
+ using sda = Gpio<GPIOB_BASE, 9>;
+ } //namespace i2c [non usato]
+
+ namespace uart1 {
+ using tx = Gpio<GPIOA_BASE, 9>;
+ using rx = Gpio<GPIOA_BASE, 10>;
+ } //namespace uart1
+
+ namespace can {
+ using rx = Gpio<GPIOB_BASE, 8>;
+ using tx = Gpio<GPIOB_BASE, 9>;
+ } // namespace can
+} //namespace interfaces
+
+
+namespace actuators
+{
+
+ using abort1 = Gpio<GPIOA_BASE, 1>;
+ using ignition1 = Gpio<GPIOA_BASE, 2>;
+ using spare = Gpio<GPIOA_BASE, 3>;
+
+} //namespace actuators
+
+} //namespace miosix
+#endif //HWMAPPING_H
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_64k+20k_rom.ld b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_64k+20k_rom.ld
new file mode 100644
index 00000000..3affd0a0
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_64k+20k_rom.ld
@@ -0,0 +1,170 @@
+/*
+ * C++ enabled linker script for stm32 (64K FLASH, 20K RAM)
+ * Developed by TFT: Terraneo Federico Technologies
+ * Optimized for use with the Miosix kernel
+ */
+
+/*
+ * This linker script puts:
+ * - read only data and code (.text, .rodata, .eh_*) in flash
+ * - stacks, heap and sections .data and .bss in the internal ram
+ * - the external ram (if available) is not used.
+ */
+
+/*
+ * The main stack is used for interrupt handling by the kernel.
+ *
+ * *** Readme ***
+ * This linker script places the main stack (used by the kernel for interrupts)
+ * at the bottom of the ram, instead of the top. This is done for two reasons:
+ *
+ * - as an optimization for microcontrollers with little ram memory. In fact
+ * the implementation of malloc from newlib requests memory to the OS in 4KB
+ * block (except the first block that can be smaller). This is probably done
+ * for compatibility with OSes with an MMU and paged memory. To see why this
+ * is bad, consider a microcontroller with 8KB of ram: when malloc finishes
+ * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
+ * fail because the top part of the ram is used by the main stack. As a
+ * result, the top part of the memory will not be used by malloc, even if
+ * available (and it is nearly *half* the ram on an 8KB mcu). By placing the
+ * main stack at the bottom of the ram, the upper 4KB block will be entirely
+ * free and available as heap space.
+ *
+ * - In case of main stack overflow the cpu will fault because access to memory
+ * before the beginning of the ram faults. Instead with the default stack
+ * placement the main stack will silently collide with the heap.
+ * Note: if increasing the main stack size also increase the ORIGIN value in
+ * the MEMORY definitions below accordingly.
+ */
+_main_stack_size = 0x00000200; /* main stack = 512Bytes */
+_main_stack_top = 0x20000000 + _main_stack_size;
+ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
+
+/* end of the heap on 20KB microcontrollers */
+_heap_end = 0x20005000; /* end of available ram */
+
+/* identify the Entry Point */
+ENTRY(_Z13Reset_Handlerv)
+
+/* specify the memory areas */
+MEMORY
+{
+ flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K
+
+ /*
+ * Note, the ram starts at 0x20000000 but it is necessary to add the size
+ * of the main stack, so it is 0x20000200.
+ */
+ ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200
+}
+
+/* now define the output sections */
+SECTIONS
+{
+ . = 0;
+
+ /* .text section: code goes to flash */
+ .text :
+ {
+ /* Startup code must go at address 0 */
+ KEEP(*(.isr_vector))
+
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ /* these sections for thumb interwork? */
+ *(.glue_7)
+ *(.glue_7t)
+ /* these sections for C++? */
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.ARM.extab*)
+ *(.gnu.linkonce.armextab.*)
+
+ . = ALIGN(4);
+ /* .rodata: constant data */
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ /* C++ Static constructors/destructors (eabi) */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __miosix_init_array_start = .;
+ KEEP (*(SORT(.miosix_init_array.*)))
+ KEEP (*(.miosix_init_array))
+ __miosix_init_array_end = .;
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /* C++ Static constructors/destructors (elf) */
+ . = ALIGN(4);
+ _ctor_start = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ _ctor_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > flash
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ /* .data section: global variables go to ram, but also store a copy to
+ flash to initialize them */
+ .data : ALIGN(8)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ _edata = .;
+ } > ram AT > flash
+ _etext = LOADADDR(.data);
+
+ /* .bss section: uninitialized global variables go to ram */
+ _bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ . = ALIGN(8);
+ } > ram
+ _bss_end = .;
+
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32vldiscovery.cfg b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32vldiscovery.cfg
new file mode 100644
index 00000000..23046cf8
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32vldiscovery.cfg
@@ -0,0 +1,27 @@
+#
+# OpenOCD configuration file for in-circuit debugging the stm32vldiscovery
+# loaded with the versaloon firmware.
+# To start debugging issue those commands:
+# arm-miosix-eabi-gdb main.elf
+# target remote :3333
+# monitor reset halt
+# monitor target_request debugmsgs enable
+# monitor trace point 1
+# The last two commands are required to redirect printf inside the MCU
+# through SWD, and make the output appear inside gdb
+#
+
+# Daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+# Interface (using versaloon)
+interface vsllink
+transport select swd
+swd_mode 2
+swd_delay 2
+
+# This is a board with an STM32F100RBT6
+# Use 2 kB instead of the default 16 kB
+set WORKAREASIZE 0x800
+source [find target/stm32.cfg]
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index 958d6375..27d51a85 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -39,6 +39,7 @@
#OPT_BOARD := stm32f469ni_stm32f469i-disco
#OPT_BOARD := stm32f429zi_skyward_homeone
#OPT_BOARD := stm32f429zi_skyward_rogallina
+#OPT_BOARD := stm32f103c8_skyward_alderaan
#OPT_BOARD := stm32f401re_nucleo
#OPT_BOARD := stm32f746zg_nucleo
#OPT_BOARD := stm32h753xi_eval
@@ -396,6 +397,25 @@ ifeq ($(OPT_BOARD),stm32f103c8_breakout)
endif
+##---------------------------------------------------------------------------
+## stm32f103c8_skyward_alderaan
+##
+ifeq ($(OPT_BOARD),stm32f103c8_skyward_alderaan)
+
+ ## Linker script type, there are two options
+ ## 1) Code in FLASH, stack + heap in RAM
+ ## 2) Code in FLASH, stack + heap in RAM flashing with bootloader
+
+ #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_64k+20k_bootloader.ld
+
+ ## Select clock frequency
+ CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000
+ #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000
+ #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000
+ #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000
+ #CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000
+
+endif
##---------------------------------------------------------------------------
## stm32f100c8_microboard
##
@@ -603,6 +623,8 @@ else ifeq ($(OPT_BOARD),stm32f401vc_stm32f4discovery)
ARCH := cortexM4_stm32f4
else ifeq ($(OPT_BOARD),stm32f103c8_breakout)
ARCH := cortexM3_stm32
+else ifeq ($(OPT_BOARD),stm32f103c8_skyward_alderaan)
+ ARCH := cortexM3_stm32
else ifeq ($(OPT_BOARD),stm32f100c8_microboard)
ARCH := cortexM3_stm32
else ifeq ($(OPT_BOARD),stm32f469ni_stm32f469i-disco)
@@ -1034,6 +1056,38 @@ else ifeq ($(ARCH),cortexM3_stm32)
## board.
#PROGRAM_CMDLINE := sudo vsprog -cstm32_vl -ms -I main.hex -oe -owf -ovf
PROGRAM_CMDLINE := stm32flash -w main.hex -v /dev/ttyUSB1
+
+ ##-------------------------------------------------------------------------
+ ## BOARD: stm32f103c8_skyward_alderaan
+ ##
+ else ifeq ($(OPT_BOARD),stm32f103c8_skyward_alderaan)
+
+ ## Base directory with header files for this board
+ BOARD_INC := arch/cortexM3_stm32/stm32f103c8_skyward_alderaan
+
+ ## Select linker script and boot file
+ ## Their path must be relative to the miosix directory.
+ BOOT_FILE := $(BOARD_INC)/core/stage_1_boot.o
+ LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+20k_rom.ld
+
+ ## Select architecture specific files
+ ## These are the files in arch/<arch name>/<board name>
+ ARCH_SRC := \
+ $(BOARD_INC)/interfaces-impl/bsp.cpp \
+ $(BOARD_INC)/interfaces-impl/hw_mapping.h \
+
+ ## Add a #define to allow querying board name
+ CFLAGS_BASE += -D_BOARD_STM32F103C8_SKYWARD_ALDERAAN -DSTM32F10X_MD
+ CXXFLAGS_BASE += -D_BOARD_STM32F103C8_SKYWARD_ALDERAAN -DSTM32F10X_MD
+
+ ## Select programmer command line
+ ## This is the program that is invoked when the user types
+ ## 'make program'
+ ## The command must provide a way to program the board, or print an
+ ## error message saying that 'make program' is not supported for that
+ ## board.
+ #PROGRAM_CMDLINE := sudo vsprog -cstm32_vl -ms -I main.hex -oe -owf -ovf
+ PROGRAM_CMDLINE := stm32flash -w test-alderaan.hex -v /dev/ttyUSB1
##-------------------------------------------------------------------------
## BOARD: stm32f100c8_microboard
diff --git a/miosix/config/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/board_settings.h b/miosix/config/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/board_settings.h
new file mode 100644
index 00000000..4f97600b
--- /dev/null
+++ b/miosix/config/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/board_settings.h
@@ -0,0 +1,86 @@
+/***************************************************************************
+ * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico *
+ * Copyright (C) 2016 by Silvano Seva *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef BOARD_SETTINGS_H
+#define BOARD_SETTINGS_H
+
+#include "util/version.h"
+
+/**
+ * \internal
+ * Versioning for board_settings.h for out of git tree projects
+ */
+#define BOARD_SETTINGS_VERSION 100
+
+namespace miosix {
+
+/**
+ * \addtogroup Settings
+ * \{
+ */
+
+/// Size of stack for main().
+/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the
+/// STM32F103C8 has 20KB of RAM so there is room for a big 4K stack.
+const unsigned int MAIN_STACK_SIZE=4*1024;
+
+/// Frequency of tick (in Hz). The frequency of the STM32F100RB timer in the
+/// stm32vldiscovery board can be divided by 1000. This allows to use a 1KHz
+/// tick and the minimun Thread::sleep value is 1ms
+/// For the priority scheduler this is also the context switch frequency
+const unsigned int TICK_FREQ=1000;
+
+///\internal Aux timer run @ 100KHz
+///Note that since the timer is only 16 bits this imposes a limit on the
+///burst measurement of 655ms. If due to a pause_kernel() or
+///disable_interrupts() section a thread runs for more than that time, a wrong
+///burst value will be measured
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
+
+/// Serial port
+const unsigned int defaultSerial=1;
+const unsigned int defaultSerialSpeed=19200;
+const bool defaultSerialFlowctrl=false;
+#define SERIAL_1_DMA
+//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA
+//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA
+
+///\def STDOUT_REDIRECTED_TO_DCC
+///If defined, stdout is redirected to the debug communication channel, and
+///will be printed if OpenOCD is connected. If not defined, stdout will be
+///redirected throug USART1, as usual.
+//#define STDOUT_REDIRECTED_TO_DCC
+
+/**
+ * \}
+ */
+
+} //namespace miosix
+
+#endif /* BOARD_SETTINGS_H */
--
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