diff --git a/miosix/arch/common/core/interrupts.h b/miosix/arch/common/core/interrupts.h
index 118ac862fb1ece79dfa4acad864d041baa930f70..cb8afb230b60a6dafe6ab5068111a12446f6c460 100644
--- a/miosix/arch/common/core/interrupts.h
+++ b/miosix/arch/common/core/interrupts.h
@@ -3,7 +3,7 @@
#ifdef _ARCH_ARM7_LPC2000
#include "interrupts_arm7.h"
-#elif defined(_ARCH_CORTEXM0_STM32) || defined(_ARCH_CORTEXM3_STM32) \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
|| defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
|| defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
|| defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \
@@ -18,6 +18,6 @@
// compilation issues a flag is defined to disable code that accesses to
// registers not present in these families
-#if defined(_ARCH_CORTEXM0_STM32)
+#if defined(_ARCH_CORTEXM0_STM32F0)
#define _ARCH_CORTEXM0
#endif
diff --git a/miosix/arch/common/core/stm32f0_f3_os_timer.cpp b/miosix/arch/common/core/stm32f0_f3_os_timer.cpp
index f9e8c59ab223314feff59471460b25c62b21386b..6ec98156e7cd4a1e9c55e8e5bd2aaa0298dab041 100644
--- a/miosix/arch/common/core/stm32f0_f3_os_timer.cpp
+++ b/miosix/arch/common/core/stm32f0_f3_os_timer.cpp
@@ -64,7 +64,7 @@ public:
// factor of two or greater, the timer is clocked at twice the bus
// interface. After this, the freq variable contains the frequency in Hz
// at which the timer prescaler is clocked.
- #if _ARCH_CORTEXM0_STM32
+ #if _ARCH_CORTEXM0_STM32F0
if(RCC->CFGR & RCC_CFGR_PPRE_2) result/=1<<((RCC->CFGR>>8) & 0x3);
#else
if(RCC->CFGR & RCC_CFGR_PPRE1_2) result/=1<<((RCC->CFGR>>8) & 0x3);
diff --git a/miosix/arch/common/drivers/serial.h b/miosix/arch/common/drivers/serial.h
index 1ccb3d3ba6b2691b8b68f7d8fb498813968358ec..8539b50bf28e63c316bc7f58f96b2cf280f9ac4c 100644
--- a/miosix/arch/common/drivers/serial.h
+++ b/miosix/arch/common/drivers/serial.h
@@ -3,7 +3,7 @@
#ifdef _ARCH_ARM7_LPC2000
#include "serial_lpc2000.h"
-#elif defined(_ARCH_CORTEXM0_STM32) || defined(_ARCH_CORTEXM3_STM32) \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
|| defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
|| defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
|| defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM4_STM32F3) \
diff --git a/miosix/arch/common/drivers/serial_stm32.cpp b/miosix/arch/common/drivers/serial_stm32.cpp
index ab67af2250d72815f3229f21479b0c6fad773ff5..798d66b7164a85172f5c5a82fba251089127e59a 100644
--- a/miosix/arch/common/drivers/serial_stm32.cpp
+++ b/miosix/arch/common/drivers/serial_stm32.cpp
@@ -137,7 +137,7 @@ void __attribute__((naked)) USART3_4_IRQHandler()
*/
void __attribute__((noinline)) usart1txDmaImpl()
{
- #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
DMA1->IFCR=DMA_IFCR_CGIF4;
DMA1_Channel4->CCR=0; //Disable DMA
@@ -158,7 +158,7 @@ void __attribute__((noinline)) usart1rxDmaImpl()
if(ports[0]) ports[0]->IRQhandleDMArx();
}
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
/**
* \internal DMA1 Channel 4 IRQ (configured as USART1 TX)
@@ -211,7 +211,7 @@ void __attribute__((naked)) DMA2_Stream5_IRQHandler()
*/
void __attribute__((noinline)) usart2txDmaImpl()
{
- #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
DMA1->IFCR=DMA_IFCR_CGIF7;
DMA1_Channel7->CCR=0; //Disable DMA
@@ -232,7 +232,7 @@ void __attribute__((noinline)) usart2rxDmaImpl()
if(ports[1]) ports[1]->IRQhandleDMArx();
}
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
/**
* \internal DMA1 Channel 7 IRQ (configured as USART2 TX)
@@ -285,7 +285,7 @@ void __attribute__((naked)) DMA1_Stream5_IRQHandler()
*/
void __attribute__((noinline)) usart3txDmaImpl()
{
- #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
DMA1->IFCR=DMA_IFCR_CGIF2;
DMA1_Channel2->CCR=0; //Disable DMA
@@ -306,7 +306,7 @@ void __attribute__((noinline)) usart3rxDmaImpl()
if(ports[2]) ports[2]->IRQhandleDMArx();
}
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
/**
* \internal DMA1 Channel 2 IRQ (configured as USART3 TX)
@@ -385,14 +385,14 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
: Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500),
flowControl(flowControl==RTSCTS), portId(id)
{
- #if !defined(_ARCH_CORTEXM3_STM32)
+ #if !defined(_ARCH_CORTEXM3_STM32F1)
//stm32f2, f4, l4, l1, f7, h7 require alternate function mapping
//stm32f0 family has different alternate function mapping
//with respect to the other families
switch(id)
{
case 1:
- #if !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM0_STM32F0)
u1tx::alternateFunction(7);
u1rx::alternateFunction(7);
if(flowControl)
@@ -400,7 +400,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u1rts::alternateFunction(7);
u1cts::alternateFunction(7);
}
- #else //!defined(_ARCH_CORTEXM0_STM32)
+ #else //!defined(_ARCH_CORTEXM0_STM32F0)
u1tx::alternateFunction(1);
u1rx::alternateFunction(1);
if(flowControl)
@@ -408,10 +408,10 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u1rts::alternateFunction(1);
u1cts::alternateFunction(1);
}
- #endif //!defined(_ARCH_CORTEXM0_STM32)
+ #endif //!defined(_ARCH_CORTEXM0_STM32F0)
break;
case 2:
- #if !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM0_STM32F0)
u2tx::alternateFunction(7);
u2rx::alternateFunction(7);
if(flowControl)
@@ -419,7 +419,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u2rts::alternateFunction(7);
u2cts::alternateFunction(7);
}
- #else //!defined(_ARCH_CORTEXM0_STM32)
+ #else //!defined(_ARCH_CORTEXM0_STM32F0)
u2tx::alternateFunction(1);
u2rx::alternateFunction(1);
if(flowControl)
@@ -427,10 +427,10 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u2rts::alternateFunction(1);
u2cts::alternateFunction(1);
}
- #endif //!defined(_ARCH_CORTEXM0_STM32)
+ #endif //!defined(_ARCH_CORTEXM0_STM32F0)
break;
case 3:
- #if !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM0_STM32F0)
u3tx::alternateFunction(7);
u3rx::alternateFunction(7);
if(flowControl)
@@ -438,7 +438,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u3rts::alternateFunction(7);
u3cts::alternateFunction(7);
}
- #else //!defined(_ARCH_CORTEXM0_STM32)
+ #else //!defined(_ARCH_CORTEXM0_STM32F0)
u3tx::alternateFunction(4);
u3rx::alternateFunction(4);
if(flowControl)
@@ -446,7 +446,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
u3rts::alternateFunction(4);
u3cts::alternateFunction(4);
}
- #endif //!defined(_ARCH_CORTEXM0_STM32)
+ #endif //!defined(_ARCH_CORTEXM0_STM32F0)
break;
}
#endif //_ARCH_CORTEXM3_STM32
@@ -499,11 +499,11 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
//Quirk the position of the PPRE1 and PPRE2 bitfields in RCC->CFGR changes
//STM32F0 does not have ppre1 and ppre2, in this case the variables are not
//defined in order to avoid "unused variable" warning
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM3_STM32L1) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM3_STM32L1) \
|| defined(_ARCH_CORTEXM4_STM32F3) || defined(_ARCH_CORTEXM4_STM32L4)
const unsigned int ppre1=8;
const unsigned int ppre2=11;
- #elif !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+ #elif !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
const unsigned int ppre1=10;
const unsigned int ppre2=13;
#endif
@@ -514,7 +514,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
RCC_SYNC();
#ifdef SERIAL_1_DMA
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
#ifdef _ARCH_CORTEXM4_STM32L4
RCC->AHB1ENR |= RCC_AHBENR_DMA1EN;
@@ -548,9 +548,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
#endif //SERIAL_1_DMA
NVIC_SetPriority(USART1_IRQn,15);//Lowest priority for serial
NVIC_EnableIRQ(USART1_IRQn);
- #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
if(RCC->CFGR & RCC_CFGR_PPRE2_2) freq/=1<<(((RCC->CFGR>>ppre2) & 0x3)+1);
- #elif defined(_ARCH_CORTEXM0_STM32)
+ #elif defined(_ARCH_CORTEXM0_STM32F0)
// STM32F0 family has only PPRE2 register
if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
#else
@@ -579,7 +579,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
#endif //_ARCH_CORTEXM7_STM32H7
RCC_SYNC();
#ifdef SERIAL_2_DMA
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
#ifdef _ARCH_CORTEXM4_STM32L4
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
@@ -613,9 +613,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
#endif //SERIAL_2_DMA
NVIC_SetPriority(USART2_IRQn,15);//Lowest priority for serial
NVIC_EnableIRQ(USART2_IRQn);
- #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>ppre1) & 0x3)+1);
- #elif defined(_ARCH_CORTEXM0_STM32)
+ #elif defined(_ARCH_CORTEXM0_STM32F0)
// STM32F0 family has only PPRE2 register
if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
#else //_ARCH_CORTEXM7_STM32H7
@@ -643,7 +643,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
#endif //_ARCH_CORTEXM7_STM32H7
RCC_SYNC();
#ifdef SERIAL_3_DMA
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
#ifdef _ARCH_CORTEXM4_STM32L4
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
@@ -682,9 +682,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
NVIC_SetPriority(USART3_4_IRQn,15);
NVIC_EnableIRQ(USART3_4_IRQn);
#endif //STM32F072xB
- #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+ #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>ppre1) & 0x3)+1);
- #elif defined(_ARCH_CORTEXM0_STM32)
+ #elif defined(_ARCH_CORTEXM0_STM32F0)
// STM32F0 family has only PPRE2 register
if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
#else //_ARCH_CORTEXM7_STM32H7
@@ -808,7 +808,7 @@ ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where)
for(size_t i=0;i<size;i++)
{
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
while((port->SR & USART_SR_TXE)==0) ;
port->DR=*buf++;
@@ -829,7 +829,7 @@ void STM32Serial::IRQwrite(const char *str)
#ifdef SERIAL_DMA
if(dmaTx)
{
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
//If no DMA transfer is in progress bit EN is zero. Otherwise wait until
//DMA xfer ends, by waiting for the TC (or TE) interrupt flag
@@ -853,7 +853,7 @@ void STM32Serial::IRQwrite(const char *str)
while(*str)
{
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
while((port->SR & USART_SR_TXE)==0) ;
port->DR=*str++;
@@ -895,7 +895,7 @@ int STM32Serial::ioctl(int cmd, void* arg)
void STM32Serial::IRQhandleInterrupt()
{
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
unsigned int status=port->SR;
#else //_ARCH_CORTEXM7_STM32F7/H7
@@ -913,7 +913,7 @@ void STM32Serial::IRQhandleInterrupt()
{
//Always read data, since this clears interrupt flags
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
c=port->DR;
#else //_ARCH_CORTEXM7_STM32F7/H7
@@ -927,7 +927,7 @@ void STM32Serial::IRQhandleInterrupt()
if(status & USART_SR_IDLE)
{
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
c=port->DR; //clears interrupt flags
#else //_ARCH_CORTEXM7_STM32F7/H7
@@ -988,7 +988,7 @@ STM32Serial::~STM32Serial()
case 1:
#ifdef SERIAL_1_DMA
IRQdmaReadStop();
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
NVIC_DisableIRQ(DMA1_Channel4_IRQn);
NVIC_ClearPendingIRQ(DMA1_Channel4_IRQn);
@@ -1010,7 +1010,7 @@ STM32Serial::~STM32Serial()
case 2:
#ifdef SERIAL_2_DMA
IRQdmaReadStop();
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
NVIC_DisableIRQ(DMA1_Channel7_IRQn);
NVIC_ClearPendingIRQ(DMA1_Channel7_IRQn);
@@ -1039,7 +1039,7 @@ STM32Serial::~STM32Serial()
case 3:
#ifdef SERIAL_3_DMA
IRQdmaReadStop();
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
NVIC_DisableIRQ(DMA1_Channel2_IRQn);
NVIC_ClearPendingIRQ(DMA1_Channel2_IRQn);
@@ -1109,7 +1109,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
//writes to DR and completes the TC clear sequence.
DeepSleepLock dpLock;
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
while((port->SR & USART_SR_TXE)==0) ;
#else //_ARCH_CORTEXM7_STM32F7/H7
@@ -1117,7 +1117,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
#endif //_ARCH_CORTEXM7_STM32F7/H7
dmaTxInProgress=true;
- #if defined(_ARCH_CORTEXM3_STM32)
+ #if defined(_ARCH_CORTEXM3_STM32F1)
dmaTx->CPAR=reinterpret_cast<unsigned int>(&port->DR);
dmaTx->CMAR=reinterpret_cast<unsigned int>(buffer);
dmaTx->CNDTR=size;
@@ -1138,7 +1138,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
| DMA_CCR_EN; //Start DMA
#else //_ARCH_CORTEXM4_STM32F3
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32)
+ && !defined(_ARCH_CORTEXM0_STM32F0)
dmaTx->PAR=reinterpret_cast<unsigned int>(&port->DR);
#else //_ARCH_CORTEXM7_STM32F7/H7
dmaTx->PAR=reinterpret_cast<unsigned int>(&port->TDR);
@@ -1172,7 +1172,7 @@ void STM32Serial::IRQreadDma()
void STM32Serial::IRQdmaReadStart()
{
- #if defined(_ARCH_CORTEXM3_STM32)
+ #if defined(_ARCH_CORTEXM3_STM32F1)
dmaRx->CPAR=reinterpret_cast<unsigned int>(&port->DR);
dmaRx->CMAR=reinterpret_cast<unsigned int>(rxBuffer);
dmaRx->CNDTR=rxQueueMin;
@@ -1193,7 +1193,7 @@ void STM32Serial::IRQdmaReadStart()
| DMA_CCR_EN; //Start DMA
#else //_ARCH_CORTEXM4_STM32F3
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32)
+ && !defined(_ARCH_CORTEXM0_STM32F0)
dmaRx->PAR=reinterpret_cast<unsigned int>(&port->DR);
#else //_ARCH_CORTEXM7_STM32F7/H7
dmaRx->PAR=reinterpret_cast<unsigned int>(&port->RDR);
@@ -1213,7 +1213,7 @@ void STM32Serial::IRQdmaReadStart()
int STM32Serial::IRQdmaReadStop()
{
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
dmaRx->CCR=0;
static const unsigned int irqMask[]=
diff --git a/miosix/arch/common/drivers/serial_stm32.h b/miosix/arch/common/drivers/serial_stm32.h
index 95ad8d04b21500ea7e9a03a12fd3dab1cca4c97f..0a7fd194ba8e66d214a68a827f015655de1869f0 100644
--- a/miosix/arch/common/drivers/serial_stm32.h
+++ b/miosix/arch/common/drivers/serial_stm32.h
@@ -34,7 +34,7 @@
#include "interfaces/gpio.h"
#include "board_settings.h"
-#if defined(_ARCH_CORTEXM3_STM32) && defined(__ENABLE_XRAM)
+#if defined(_ARCH_CORTEXM3_STM32F1) && defined(__ENABLE_XRAM)
//Quirk: concurrent access to the FSMC from both core and DMA is broken in
//the stm32f1, so disable DMA mode if XRAM is enabled.
#undef SERIAL_1_DMA
@@ -46,7 +46,7 @@
#define SERIAL_DMA
#endif
-#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32)
+#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32F0)
#undef SERIAL_1_DMA
#undef SERIAL_2_DMA
#undef SERIAL_3_DMA
@@ -248,7 +248,7 @@ private:
void waitSerialTxFifoEmpty()
{
#if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
- && !defined(_ARCH_CORTEXM0_STM32) && !defined(_ARCH_CORTEXM4_STM32F3) \
+ && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \
&& !defined(_ARCH_CORTEXM4_STM32L4)
while((port->SR & USART_SR_TC)==0) ;
#else //_ARCH_CORTEXM7_STM32F7/H7
@@ -265,14 +265,14 @@ private:
USART_TypeDef *port; ///< Pointer to USART peripheral
#ifdef SERIAL_DMA
- #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+ #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4)
DMA_Channel_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral
DMA_Channel_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral
- #else //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+ #else //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
DMA_Stream_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral
DMA_Stream_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral
- #endif //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+ #endif //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
Thread *txWaiting; ///< Thread waiting for tx, or 0
static const unsigned int txBufferSize=16; ///< Size of tx buffer, for tx speedup
/// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the
diff --git a/miosix/arch/common/drivers/servo_stm32.cpp b/miosix/arch/common/drivers/servo_stm32.cpp
index 518d4a8bfcd85a2da19b9b2b6f63fd2dee242612..c4023f6ffc6e2a81aee25c8dedde41c23c9d9d0f 100644
--- a/miosix/arch/common/drivers/servo_stm32.cpp
+++ b/miosix/arch/common/drivers/servo_stm32.cpp
@@ -96,7 +96,7 @@ void SynchronizedServo::enable(int channel)
case 0:
TIM4->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
TIM4->CCER |= TIM_CCER_CC1E;
- #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+ #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
servo1out::alternateFunction(2);
#endif //_ARCH_CORTEXM3_STM32
servo1out::mode(Mode::ALTERNATE);
@@ -104,7 +104,7 @@ void SynchronizedServo::enable(int channel)
case 1:
TIM4->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
TIM4->CCER |= TIM_CCER_CC2E;
- #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+ #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
servo2out::alternateFunction(2);
#endif //_ARCH_CORTEXM3_STM32
servo2out::mode(Mode::ALTERNATE);
@@ -112,7 +112,7 @@ void SynchronizedServo::enable(int channel)
case 2:
TIM4->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE;
TIM4->CCER |= TIM_CCER_CC3E;
- #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+ #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
servo3out::alternateFunction(2);
#endif //_ARCH_CORTEXM3_STM32
servo3out::mode(Mode::ALTERNATE);
@@ -120,7 +120,7 @@ void SynchronizedServo::enable(int channel)
case 3:
TIM4->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE;
TIM4->CCER |= TIM_CCER_CC4E;
- #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+ #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
servo4out::alternateFunction(2);
#endif //_ARCH_CORTEXM3_STM32
servo4out::mode(Mode::ALTERNATE);
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index c054cacf879d822072568b759046d63191b9e7fa..093c83ba37f5558a8bb6cb7a4e87f926b6ca310d 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -1307,9 +1307,9 @@ else ifeq ($(ARCH),cortexM3_stm32f1)
## Select appropriate compiler flags for both ASM/C/C++/linker
AFLAGS_BASE := -mcpu=cortex-m3 -mthumb
- CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32 $(CLOCK_FREQ) $(XRAM) \
+ CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F1 $(CLOCK_FREQ) $(XRAM) \
-mcpu=cortex-m3 -mthumb $(OPT_OPTIMIZATION) -c
- CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32 $(CLOCK_FREQ) $(XRAM) \
+ CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F1 $(CLOCK_FREQ) $(XRAM) \
$(OPT_EXCEPT) -mcpu=cortex-m3 -mthumb \
$(OPT_OPTIMIZATION) -c
LFLAGS_BASE := -mcpu=cortex-m3 -mthumb -Wl,--gc-sections,-Map,main.map \
@@ -2514,9 +2514,9 @@ else ifeq ($(ARCH),cortexM0_stm32f0)
## Select appropriate compiler flags for both ASM/C/C++/linker
AFLAGS_BASE := -mcpu=cortex-m0 -mthumb
- CFLAGS_BASE += -D_ARCH_CORTEXM0_STM32 $(CLOCK_FREQ) -mcpu=cortex-m0 \
+ CFLAGS_BASE += -D_ARCH_CORTEXM0_STM32F0 $(CLOCK_FREQ) -mcpu=cortex-m0 \
-mthumb $(OPT_OPTIMIZATION) -c
- CXXFLAGS_BASE += -D_ARCH_CORTEXM0_STM32 $(CLOCK_FREQ) -mcpu=cortex-m0 \
+ CXXFLAGS_BASE += -D_ARCH_CORTEXM0_STM32F0 $(CLOCK_FREQ) -mcpu=cortex-m0 \
-mthumb $(OPT_OPTIMIZATION) -c
LFLAGS_BASE := -mcpu=cortex-m0 -mthumb -Wl,--gc-sections,-Map,main.map \
-Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
diff --git a/miosix/interfaces/atomic_ops.h b/miosix/interfaces/atomic_ops.h
index cfa3b7efdd8354db67b29cd7a61599eca6e8c4ec..c5f3c96c1119433118d1c1fa4d62f31b99531431 100644
--- a/miosix/interfaces/atomic_ops.h
+++ b/miosix/interfaces/atomic_ops.h
@@ -156,13 +156,13 @@ inline void *atomicFetchAndIncrement(void * const volatile * p, int offset,
#ifdef _ARCH_ARM7_LPC2000
#include "core/atomic_ops_impl_arm7.h"
-#elif defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM3_STM32F2) \
+#elif defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM3_STM32F2) \
|| defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32L1) \
|| defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) \
|| defined(_ARCH_CORTEXM3_EFM32GG) || defined(_ARCH_CORTEXM4_STM32F3) \
|| defined(_ARCH_CORTEXM4_STM32L4) || defined(_ARCH_CORTEXM4_ATSAM4L)
#include "core/atomic_ops_impl_cortexMx.h"
-#elif defined(_ARCH_CORTEXM0_STM32)
+#elif defined(_ARCH_CORTEXM0_STM32F0)
#include "core/atomic_ops_impl_cortexM0.h"
#else
#error "No atomic ops for this architecture"
diff --git a/miosix/interfaces/endianness.h b/miosix/interfaces/endianness.h
index 94bd8e4b4091ead55c0b78a322491b14e5c3f065..a545bdff25a792cbc2b69b387948aa8fbe725bb8 100644
--- a/miosix/interfaces/endianness.h
+++ b/miosix/interfaces/endianness.h
@@ -29,7 +29,7 @@
#ifdef _ARCH_ARM7_LPC2000
#include "core/endianness_impl_arm7.h"
-#elif defined(_ARCH_CORTEXM0_STM32) || defined(_ARCH_CORTEXM3_STM32) \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
|| defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
|| defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
|| defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \
diff --git a/miosix_np_2/nbproject/configurations.xml b/miosix_np_2/nbproject/configurations.xml
index f50602507530fb6ef0e7fe587ed26ffd4733dc7e..f61e43bfcfba036454f9c0b93e5519a2aac7c040 100644
--- a/miosix_np_2/nbproject/configurations.xml
+++ b/miosix_np_2/nbproject/configurations.xml
@@ -1775,7 +1775,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STM3210E_EVAL</Elem>
</preprocessorList>
</cTool>
@@ -1785,7 +1785,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STM3210E_EVAL</Elem>
</preprocessorList>
</ccTool>
@@ -2392,7 +2392,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_MP3V2</Elem>
</preprocessorList>
</cTool>
@@ -2402,7 +2402,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_MP3V2</Elem>
</preprocessorList>
</ccTool>
@@ -3011,7 +3011,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD_VL</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STM32VLDISCOVERY</Elem>
</preprocessorList>
</cTool>
@@ -3021,7 +3021,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD_VL</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STM32VLDISCOVERY</Elem>
</preprocessorList>
</ccTool>
@@ -3480,7 +3480,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STRIVE_MINI</Elem>
</preprocessorList>
</cTool>
@@ -3490,7 +3490,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_STRIVE_MINI</Elem>
</preprocessorList>
</ccTool>
@@ -4100,7 +4100,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_REDBULL_V2</Elem>
</preprocessorList>
</cTool>
@@ -4110,7 +4110,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_HD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_REDBULL_V2</Elem>
</preprocessorList>
</ccTool>
@@ -9359,7 +9359,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_ALS_MAINBOARD_REV2</Elem>
</preprocessorList>
</cTool>
@@ -9369,7 +9369,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_ALS_MAINBOARD_REV2</Elem>
</preprocessorList>
</ccTool>
@@ -9848,7 +9848,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD_VL</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_TEMPSENSOR</Elem>
</preprocessorList>
</cTool>
@@ -9858,7 +9858,7 @@
<Elem>COMPILING_MIOSIX</Elem>
<Elem>PARSING_FROM_IDE</Elem>
<Elem>STM32F10X_MD_VL</Elem>
- <Elem>_ARCH_CORTEXM3_STM32</Elem>
+ <Elem>_ARCH_CORTEXM3_STM32F1</Elem>
<Elem>_BOARD_TEMPSENSOR</Elem>
</preprocessorList>
</ccTool>