From 67ca8746e9422a2de739d6335ea1253ad44cb188 Mon Sep 17 00:00:00 2001
From: Terraneo Federico <fede.tft@miosix.org>
Date: Thu, 9 Jan 2025 14:58:54 +0100
Subject: [PATCH] Enable the MPU also in high priority interrupt handlers, as
 it also defines the cacheability of regions

---
 miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h
index b0fcfcd8..1bb1dcdb 100644
--- a/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h
+++ b/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h
@@ -136,7 +136,9 @@ inline void MPUConfiguration::IRQdisable()
 inline void IRQenableMPUatBoot()
 {
     #if __MPU_PRESENT==1
-    MPU->CTRL=MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
+    MPU->CTRL = MPU_CTRL_HFNMIENA_Msk
+              | MPU_CTRL_PRIVDEFENA_Msk
+              | MPU_CTRL_ENABLE_Msk;
     #endif //__MPU_PRESENT==1
 }
 
-- 
GitLab