diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
index 45809a977006dc74e21597bbc9970f3e9be1363e..028ca42ac98be6df34bb19b73361400fa773673a 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
@@ -63,9 +63,10 @@ static void sdramCommandWait()
         if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return;
 }
 
-
-
-void configureSdram()
+/**
+ * Configure GPIOs at boot
+ */
+static void configureGpio()
 {
     //Enable all gpios
     RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
@@ -73,9 +74,6 @@ void configureSdram()
                     RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
                     RCC_AHB1ENR_GPIOGEN;
     RCC_SYNC();
-    
-    //To access the SDRAM we need to configure its GPIO, but since
-    //we're at it, we'll configure all the GPIOS
 
     //Port config (H=high, L=low, PU=pullup, PD=pulldown)
     //  |  PORTA  |  PORTB  |  PORTC  |  PORTD  |  PORTE  |  PORTF  |  PORTG  |
@@ -143,6 +141,13 @@ void configureSdram()
     display::vregEn::low();
     display::reset::low();
     display::cs::high();
+}
+
+void configureSdram()
+{
+    //To access the SDRAM we need to configure its GPIO, but since
+    //we're at it, we'll configure all the GPIOs
+    configureGpio();
     
     //Second, actually start the SDRAM controller
     RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN;
@@ -222,6 +227,11 @@ void configureSdram()
 
 void IRQbspInit()
 {
+    //If using SDRAM GPIOs are configured by configureSdram(), else configure them here
+    #ifndef __ENABLE_XRAM
+    configureGpio();
+    #endif //__ENABLE_XRAM
+
     ledOn();
     delayMs(100);
     ledOff();
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
index 8e19a0cc5addb5a57ae6548c1946ab29680f01f8..09f64b1f48d04c3101df1004b11f8bab6638e450 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
@@ -63,8 +63,6 @@ static void sdramCommandWait()
         if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return;
 }
 
-
-
 void configureSdram()
 {
     //Enable all gpios
@@ -184,6 +182,15 @@ void configureSdram()
 
 void IRQbspInit()
 {
+    //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here
+    #ifndef __ENABLE_XRAM
+    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
+                    RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
+                    RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
+                    RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN;
+    RCC_SYNC();
+    #endif //__ENABLE_XRAM
+    
     _led::mode(Mode::OUTPUT);
     ledOn();
     delayMs(100);