diff --git a/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_128k+20k_rom.ld b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_128k+20k_rom.ld new file mode 100644 index 0000000000000000000000000000000000000000..8aa39250b2e7caa64509404edca9650712e2c4aa --- /dev/null +++ b/miosix/arch/cortexM3_stm32/stm32f103c8_skyward_alderaan/stm32_128k+20k_rom.ld @@ -0,0 +1,177 @@ +/* + * C++ enabled linker script for stm32 (64K FLASH, 20K RAM) + * Developed by TFT: Terraneo Federico Technologies + * Optimized for use with the Miosix kernel + */ + +/* + * This linker script puts: + * - read only data and code (.text, .rodata, .eh_*) in flash + * - stacks, heap and sections .data and .bss in the internal ram + * - the external ram (if available) is not used. + */ + +/* + * The main stack is used for interrupt handling by the kernel. + * + * *** Readme *** + * This linker script places the main stack (used by the kernel for interrupts) + * at the bottom of the ram, instead of the top. This is done for two reasons: + * + * - as an optimization for microcontrollers with little ram memory. In fact + * the implementation of malloc from newlib requests memory to the OS in 4KB + * block (except the first block that can be smaller). This is probably done + * for compatibility with OSes with an MMU and paged memory. To see why this + * is bad, consider a microcontroller with 8KB of ram: when malloc finishes + * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will + * fail because the top part of the ram is used by the main stack. As a + * result, the top part of the memory will not be used by malloc, even if + * available (and it is nearly *half* the ram on an 8KB mcu). By placing the + * main stack at the bottom of the ram, the upper 4KB block will be entirely + * free and available as heap space. + * + * - In case of main stack overflow the cpu will fault because access to memory + * before the beginning of the ram faults. Instead with the default stack + * placement the main stack will silently collide with the heap. + * Note: if increasing the main stack size also increase the ORIGIN value in + * the MEMORY definitions below accordingly. + */ +_main_stack_size = 0x00000200; /* main stack = 512Bytes */ +_main_stack_top = 0x20000000 + _main_stack_size; +ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); + +/* end of the heap on 20KB microcontrollers */ +_heap_end = 0x20005000; /* end of available ram */ + +/* identify the Entry Point */ +ENTRY(_Z13Reset_Handlerv) + +/* specify the memory areas */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + + /* + * Note, the ram starts at 0x20000000 but it is necessary to add the size + * of the main stack, so it is 0x20000200. + */ + ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200 +} + +/* now define the output sections */ +SECTIONS +{ + . = 0; + + /* .text section: code goes to flash */ + .text : + { + /* Startup code must go at address 0 */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++? */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* .data section: global variables go to ram, but also store a copy to + flash to initialize them */ + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram AT > flash + _etext = LOADADDR(.data); + + /* .bss section: uninitialized global variables go to ram */ + _bss_start = .; + .bss : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram + _bss_end = .; + + /* .crc section: flash crc goes in here + .crc_section 0x801FFFB : + { + KEEP(*(.crc_section)) + } > flash + */ + + _end = .; + PROVIDE(end = .); +} diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc index 89861740b947cb50207bf7081a01b8fd0b84076c..f94d84d6a3c9d327a9ebdbb307eda4971c5ec189 100644 --- a/miosix/config/Makefile.inc +++ b/miosix/config/Makefile.inc @@ -412,11 +412,11 @@ ifeq ($(OPT_BOARD),stm32f103c8_skyward_alderaan) #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_64k+20k_rom.ld ## Select clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 + #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 + CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 endif ##--------------------------------------------------------------------------- @@ -1131,7 +1131,7 @@ else ifeq ($(ARCH),cortexM3_stm32) ## Select linker script and boot file ## Their path must be relative to the miosix directory. BOOT_FILE := $(BOARD_INC)/core/stage_1_boot.o - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+20k_rom.ld + LINKER_SCRIPT := $(BOARD_INC)/stm32_128k+20k_rom.ld ## Select architecture specific files ## These are the files in arch/<arch name>/<board name>