diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld
deleted file mode 100644
index 314cb3474c3dc3ef8d15bccc8ade764df257d5f4..0000000000000000000000000000000000000000
--- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * C++ enabled linker script for stm32 (1M FLASH, 192K RAM)
- * Developed by TFT: Terraneo Federico Technologies
- * Optimized for use with the Miosix kernel
- */
-
-/*
- * This linker script puts:
- * - all (code, .data, .bss, stacks, heap) in the internal ram.
- * It is most useful for debugging, since powercycling the board will erase code
- */
-
-/*
- * This chip has an unusual quirk that the RAM is divided in two block mapped
- * at two non contiguous memory addresses. I don't know why they've done that,
- * probably doing the obvious thing would have made writing code too easy...
- * Anyway, since hardware can't be changed, we've got to live with that and
- * try to make use of both RAMs.
- * 
- * Given the constraints above, this linker script puts:
- * - .text, .data and .bss in the "large" 128KB RAM
- * - stacks and heap in the "small" 64KB RAM.
- */
-
-/*
- * The main stack is used for interrupt handling by the kernel.
- * In this linker script the main stack is placed at the top of the ram since:
- * - the interrupt vectors are forwarded at the bottom of the ram
- */
-_main_stack_size = 0x00000200;                    /* main stack = 512Bytes */
-ASSERT(_main_stack_size   % 8 == 0, "MAIN stack size error");
-
-/* end of the stack */
-_main_stack_top = 0x10010000;                     /* placed at the top of ram */
-_end = 0x10000000;
-_heap_end = _main_stack_top - _main_stack_size;
-
-/* identify the Entry Point  */
-ENTRY(_ZN6miosix13Reset_HandlerEv)
-
-/* specify the memory areas  */
-MEMORY
-{
-    largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K
-    smallram(wx) : ORIGIN = 0x10000000, LENGTH =  64K
-}
-
-/* now define the output sections  */
-SECTIONS
-{
-    . = 0;
-    
-    /* .text section: code goes to flash */
-    .text :
-    {
-        /* Startup code must go at address 0 */
-        KEEP(*(.isr_vector))
-        
-        *(.text)
-        *(.text.*)
-        *(.gnu.linkonce.t.*)
-        /* these sections for thumb interwork? */
-        *(.glue_7)
-        *(.glue_7t)
-        /* these sections for C++? */
-        *(.gcc_except_table)
-        *(.gcc_except_table.*)
-        *(.ARM.extab*)
-        *(.gnu.linkonce.armextab.*)
-
-        . = ALIGN(4);
-        /* .rodata: constant data */
-        *(.rodata)
-        *(.rodata.*)
-        *(.gnu.linkonce.r.*)
-
-        /* C++ Static constructors/destructors (eabi) */
-        . = ALIGN(4);
-        KEEP(*(.init))
-        
-        . = ALIGN(4);
-        __miosix_init_array_start = .;
-        KEEP (*(SORT(.miosix_init_array.*)))
-        KEEP (*(.miosix_init_array))
-        __miosix_init_array_end = .;
-
-        . = ALIGN(4);
-        __preinit_array_start = .;
-        KEEP (*(.preinit_array))
-        __preinit_array_end = .;
-
-        . = ALIGN(4);
-        __init_array_start = .;
-        KEEP (*(SORT(.init_array.*)))
-        KEEP (*(.init_array))
-        __init_array_end = .;
-
-        . = ALIGN(4);
-        KEEP(*(.fini))
-
-        . = ALIGN(4);
-        __fini_array_start = .;
-        KEEP (*(.fini_array))
-        KEEP (*(SORT(.fini_array.*)))
-        __fini_array_end = .;
-
-        /* C++ Static constructors/destructors (elf)  */
-        . = ALIGN(4);
-        _ctor_start = .;
-        KEEP (*crtbegin.o(.ctors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
-        KEEP (*(SORT(.ctors.*)))
-        KEEP (*crtend.o(.ctors))
-        _ctor_end = .;
-
-        . = ALIGN(4);
-        KEEP (*crtbegin.o(.dtors))
-        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
-        KEEP (*(SORT(.dtors.*)))
-        KEEP (*crtend.o(.dtors))
-    } > largeram
-
-    /* .ARM.exidx is sorted, so has to go in its own output section.  */
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > largeram
-    __exidx_end = .;
-
-	/* .data section: global variables go to ram */
-    .data : ALIGN(8)
-    {
-        _data = .;
-        *(.data)
-        *(.data.*)
-        *(.gnu.linkonce.d.*)
-        . = ALIGN(8);
-        _edata = .;
-    } > largeram
-    _etext = LOADADDR(.data);
-
-    /* .bss section: uninitialized global variables go to ram */
-    _bss_start = .;
-    .bss :
-    {
-        *(.bss)
-        *(.bss.*)
-        *(.gnu.linkonce.b.*)
-        . = ALIGN(8);
-    } > largeram
-    _bss_end = .;
-
-    /*_end = .;*/
-    /*PROVIDE(end = .);*/
-}
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index 8106b53c2419d13dd8a3c276dfb9db65adfe7422..1d233de48b65e64bea978d0367e59ff2297d31bd 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -182,7 +182,6 @@ ifeq ($(OPT_BOARD),stm32f407vg_stm32f4discovery)
     ##    to configure the kernel with "#define WITH_PROCESSES"
     LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/
     LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_rom.ld
-    #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_ram.ld
     #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_rom_processes.ld
 
     ## Select clock frequency (HSE_VALUE is the xtal on board, fixed)