diff --git a/miosix/arch/common/drivers/sd_stm32f2_f4.cpp b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
similarity index 89%
rename from miosix/arch/common/drivers/sd_stm32f2_f4.cpp
rename to miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
index da9e577e267720308c95f5532217127cbc66b195..45e90770417d3cda5bce8c8c6b2d2699314e73a7 100644
--- a/miosix/arch/common/drivers/sd_stm32f2_f4.cpp
+++ b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
@@ -25,7 +25,7 @@
  *   along with this program; if not, see <http://www.gnu.org/licenses/>   *
  ***************************************************************************/
 
-#include "sd_stm32f2_f4.h"
+#include "sd_stm32f2_f4_f7.h"
 #include "interfaces/bsp.h"
 #include "interfaces/arch_registers.h"
 #include "core/cache_cortexMx.h"
@@ -52,9 +52,17 @@
  */
 #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if defined(__SDMMC1)
 #define SDIO                 SDMMC1
 #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC1EN
 #define SDIO_IRQn            SDMMC1_IRQn
+#elif defined(__SDMMC2)
+#define SDIO                 SDMMC2
+#define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC2EN
+#define SDIO_IRQn            SDMMC2_IRQn
+#else
+#warning This error is a reminder that you have not selected between SDMMC1 and SDMMC2 in Makefile.inc
+#endif
 
 #define SDIO_STA_STBITERR    0 //This bit has been removed
 #define SDIO_STA_RXOVERR     SDMMC_STA_RXOVERR
@@ -76,6 +84,7 @@
 #define SDIO_CLKCR_CLKEN     SDMMC_CLKCR_CLKEN
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
+#define SDIO_CLKCR_WIDBUS_0  SDMMC_CLKCR_WIDBUS_0
 
 #define SDIO_MASK_STBITERRIE 0 //This bit has been removed
 #define SDIO_MASK_RXOVERRIE  SDMMC_MASK_RXOVERRIE
@@ -93,14 +102,24 @@
 
 #endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+#define DMA_Stream           DMA2_Stream0
+#else
+#define DMA_Stream           DMA2_Stream3
+#endif
+
 /**
  * \internal
- * DMA2 Stream3 interrupt handler
+ * DMA2 Stream interrupt handler
  */
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+void __attribute__((naked)) DMA2_Stream0_IRQHandler()
+#else
 void __attribute__((naked)) DMA2_Stream3_IRQHandler()
+#endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix18DMA2stream3irqImplEv");
+    asm volatile("bl _ZN6miosix12SDDMAirqImplEv");
     restoreContext();
 }
 
@@ -108,14 +127,16 @@ void __attribute__((naked)) DMA2_Stream3_IRQHandler()
  * \internal
  * SDIO interrupt handler
  */
-#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC1)
 void __attribute__((naked)) SDMMC1_IRQHandler()
+#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+void __attribute__((naked)) SDMMC2_IRQHandler()
 #else //stm32f2 and stm32f4
 void __attribute__((naked)) SDIO_IRQHandler()
 #endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix11SDIOirqImplEv");
+    asm volatile("bl _ZN6miosix9SDirqImplEv");
     restoreContext();
 }
 
@@ -130,16 +151,26 @@ static unsigned int sdioFlags;      ///< \internal SDIO status flags
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) DMA2stream3irqImpl()
+void __attribute__((used)) SDDMAirqImpl()
 {
     dmaFlags=DMA2->LISR;
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
+        transferError=true;
+
+    DMA2->LIFCR = DMA_LIFCR_CTCIF0
+                | DMA_LIFCR_CTEIF0
+                | DMA_LIFCR_CDMEIF0
+                | DMA_LIFCR_CFEIF0;
+    #else
     if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
         transferError=true;
-    
-    DMA2->LIFCR=DMA_LIFCR_CTCIF3  |
-                DMA_LIFCR_CTEIF3  |
-                DMA_LIFCR_CDMEIF3 |
-                DMA_LIFCR_CFEIF3;
+
+    DMA2->LIFCR = DMA_LIFCR_CTCIF3
+                | DMA_LIFCR_CTEIF3
+                | DMA_LIFCR_CDMEIF3
+                | DMA_LIFCR_CFEIF3;
+    #endif
     
     if(!waiting) return;
     waiting->IRQwakeup();
@@ -152,7 +183,7 @@ void __attribute__((used)) DMA2stream3irqImpl()
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) SDIOirqImpl()
+void __attribute__((used)) SDirqImpl()
 {
     sdioFlags=SDIO->STA;
     if(sdioFlags & (SDIO_STA_STBITERR | SDIO_STA_RXOVERR  |
@@ -193,12 +224,22 @@ enum CardType
 static CardType cardType=Invalid;
 
 //SD card GPIOs
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+typedef Gpio<GPIOG_BASE,9>  sdD0;
+typedef Gpio<GPIOG_BASE,10> sdD1;
+typedef Gpio<GPIOB_BASE,3>  sdD2;
+typedef Gpio<GPIOB_BASE,4>  sdD3;
+typedef Gpio<GPIOD_BASE,6>  sdCLK;
+typedef Gpio<GPIOD_BASE,7>  sdCMD;
+#else
 typedef Gpio<GPIOC_BASE,8>  sdD0;
 typedef Gpio<GPIOC_BASE,9>  sdD1;
 typedef Gpio<GPIOC_BASE,10> sdD2;
 typedef Gpio<GPIOC_BASE,11> sdD3;
 typedef Gpio<GPIOC_BASE,12> sdCLK;
 typedef Gpio<GPIOD_BASE,2>  sdCMD;
+#endif
+
 
 //
 // Class BufferConverter
@@ -884,12 +925,9 @@ static void displayBlockTransferError()
 static unsigned int dmaTransferCommonSetup(const unsigned char *buffer)
 {
     //Clear both SDIO and DMA interrupt flags
-    SDIO->ICR=0x7ff;
-    DMA2->LIFCR=DMA_LIFCR_CTCIF3  |
-                DMA_LIFCR_CTEIF3  |
-                DMA_LIFCR_CDMEIF3 |
-                DMA_LIFCR_CFEIF3;
-    
+    SDIO->ICR=0x4005ff;
+    DMA2->LIFCR=0xffffffff;
+
     transferError=false;
     dmaFlags=sdioFlags=0;
     waiting=Thread::getCurrentThread();
@@ -937,24 +975,28 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
-    DMA2_Stream3->FCR=DMA_SxFCR_FEIE    | //Interrupt on fifo error
-                      DMA_SxFCR_DMDIS   | //Fifo enabled
-                      DMA_SxFCR_FTH_0;    //Take action if fifo half full
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
-                     DMA_SxCR_PBURST_0  | //4-beat bursts read from SDIO
-                     DMA_SxCR_PL_0      | //Medium priority DMA stream
-                     memoryTransferSize | //RAM data size depends on alignment
-					 DMA_SxCR_PSIZE_1   | //Read 32bit at a time from SDIO
-				     DMA_SxCR_MINC      | //Increment RAM pointer
-			         0                  | //Peripheral to memory direction
-                     DMA_SxCR_PFCTRL    | //Peripheral is flow controller
-			         DMA_SxCR_TCIE      | //Interrupt on transfer complete
-                     DMA_SxCR_TEIE      | //Interrupt on transfer error
-                     DMA_SxCR_DMEIE     | //Interrupt on direct mode error
-			  	     DMA_SxCR_EN;         //Start the DMA
+    DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+    DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+    //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
+    DMA_Stream->FCR = DMA_SxFCR_FEIE   //Interrupt on fifo error
+                    | DMA_SxFCR_DMDIS  //Fifo enabled
+                    | DMA_SxFCR_FTH_0; //Take action if fifo half full
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO)
+    #else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2   //Channel 4 (SDIO)
+    #endif
+                   | DMA_SxCR_PBURST_0  //4-beat bursts read from SDIO
+                   | DMA_SxCR_PL_0      //Medium priority DMA stream
+                   | memoryTransferSize //RAM data size depends on alignment
+                   | DMA_SxCR_PSIZE_1   //Read 32bit at a time from SDIO
+                   | DMA_SxCR_MINC      //Increment RAM pointer
+                   | 0                  //Peripheral to memory direction
+                   | DMA_SxCR_PFCTRL    //Peripheral is flow controller
+                   | DMA_SxCR_TCIE      //Interrupt on transfer complete
+                   | DMA_SxCR_TEIE      //Interrupt on transfer error
+                   | DMA_SxCR_DMEIE     //Interrupt on direct mode error
+                   | DMA_SxCR_EN;       //Start the DMA
     
     SDIO->DLEN=nblk*512;
     if(waiting==0)
@@ -977,8 +1019,8 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1040,26 +1082,30 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
+    DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+    DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+    //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
     //Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate
     //a spurious fifo error. The code was tested and the transfer completes
     //successfully even in the presence of this fifo error
-    DMA2_Stream3->FCR=DMA_SxFCR_DMDIS   | //Fifo enabled
-                      DMA_SxFCR_FTH_1   | //Take action if fifo full
-                      DMA_SxFCR_FTH_0;
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
-                     DMA_SxCR_PBURST_0  | //4-beat bursts write to SDIO
-                     DMA_SxCR_PL_0      | //Medium priority DMA stream
-                     memoryTransferSize | //RAM data size depends on alignment
-					 DMA_SxCR_PSIZE_1   | //Write 32bit at a time to SDIO
-				     DMA_SxCR_MINC      | //Increment RAM pointer
-			         DMA_SxCR_DIR_0     | //Memory to peripheral direction
-                     DMA_SxCR_PFCTRL    | //Peripheral is flow controller
-                     DMA_SxCR_TEIE      | //Interrupt on transfer error
-                     DMA_SxCR_DMEIE     | //Interrupt on direct mode error
-			  	     DMA_SxCR_EN;         //Start the DMA
+    DMA_Stream->FCR = DMA_SxFCR_DMDIS  //Fifo enabled
+                    | DMA_SxFCR_FTH_1  //Take action if fifo full
+                    | DMA_SxFCR_FTH_0;
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO)
+#else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2     // Channel 4 (SDIO)
+#endif
+                   | DMA_SxCR_PBURST_0  //4-beat bursts write to SDIO
+                   | DMA_SxCR_PL_0      //Medium priority DMA stream
+                   | memoryTransferSize //RAM data size depends on alignment
+                   | DMA_SxCR_PSIZE_1   //Write 32bit at a time to SDIO
+                   | DMA_SxCR_MINC      //Increment RAM pointer
+                   | DMA_SxCR_DIR_0     //Memory to peripheral direction
+                   | DMA_SxCR_PFCTRL    //Peripheral is flow controller
+                   | DMA_SxCR_TEIE      //Interrupt on transfer error
+                   | DMA_SxCR_DMEIE     //Interrupt on direct mode error
+                   | DMA_SxCR_EN;       //Start the DMA
     
     SDIO->DLEN=nblk*512;
     if(waiting==0)
@@ -1082,8 +1128,8 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1161,6 +1207,22 @@ static void initSDIOPeripheral()
         RCC_SYNC();
         RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
         RCC_SYNC();
+        #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+        sdD0::mode(Mode::ALTERNATE);
+        sdD0::alternateFunction(11);
+        #ifndef SD_ONE_BIT_DATABUS
+        sdD1::mode(Mode::ALTERNATE);
+        sdD1::alternateFunction(11);
+        sdD2::mode(Mode::ALTERNATE);
+        sdD2::alternateFunction(10);
+        sdD3::mode(Mode::ALTERNATE);
+        sdD3::alternateFunction(10);
+        #endif // SD_ONE_BIT_DATABUS
+        sdCLK::mode(Mode::ALTERNATE);
+        sdCLK::alternateFunction(11);
+        sdCMD::mode(Mode::ALTERNATE);
+        sdCMD::alternateFunction(11);
+        #else
         sdD0::mode(Mode::ALTERNATE);
         sdD0::alternateFunction(12);
         #ifndef SD_ONE_BIT_DATABUS
@@ -1170,14 +1232,21 @@ static void initSDIOPeripheral()
         sdD2::alternateFunction(12);
         sdD3::mode(Mode::ALTERNATE);
         sdD3::alternateFunction(12);
-        #endif //SD_ONE_BIT_DATABUS
+        #endif // SD_ONE_BIT_DATABUS
         sdCLK::mode(Mode::ALTERNATE);
         sdCLK::alternateFunction(12);
         sdCMD::mode(Mode::ALTERNATE);
         sdCMD::alternateFunction(12);
+        #endif
     }
+
+    #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA
+    NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+    #else
     NVIC_SetPriority(DMA2_Stream3_IRQn,15);//Low priority for DMA
     NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+    #endif
     NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO
     NVIC_EnableIRQ(SDIO_IRQn);
     
diff --git a/miosix/arch/common/drivers/sd_stm32f2_f4.h b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.h
similarity index 100%
rename from miosix/arch/common/drivers/sd_stm32f2_f4.h
rename to miosix/arch/common/drivers/sd_stm32f2_f4_f7.h
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp
index d5a5be65ab88ba8474d811f26a1e90cd793fc3b7..ecf45f5954192316fbaed44a184563c057e4ac9b 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "drivers/dcc.h"
 #include "board_settings.h"
 
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp
index 85bafd95fd130c5ee43e344c96645b18c9cb5e92..c3f154d430275c24ca726a925a4052c3c23d44ea 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp
@@ -45,7 +45,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 using namespace std;
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp
index 375b99538347ae3eaeb66225c1911e97ac5385b5..b421278a788ae8d4bd511dfa1df260a385ee69ef 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "drivers/dcc.h"
 #include "board_settings.h"
 
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
index 0c804db31ec296a5e95c304e718251bc9c753819..08b143b58af2163518bd40a0bd5d5d10bdf32c53 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
@@ -45,7 +45,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "drivers/dcc.h"
 #include "board_settings.h"
 
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp
index 73c3d9deef72d4fc14d50ea828c62c12a70875ae..d5ceb67150afe3d460d9649f8cc29358157a73e4 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp
index 5c9a0963e389994f13faa3928be632bdcfc71208..a6d093305091edb24d7adb386bbde70b5d9489a6 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp
index 517187ec3004b0eef216fcca62a07c57f99d7693..09568c801bd124b286e0916f4f80fafc25595fa9 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp
index 00bd3b64d28ba5203f62f1752951f8d4a2ad8a09..06938eb4f033d85bf19cea5468f0ca8e11d71e0d 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp
index 0befcc8244460a314050173650e6d6d8edf7ca5d..6015c0f780590da3b0debbd5f9e073b67909d4a4 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp
index 73c3d9deef72d4fc14d50ea828c62c12a70875ae..d5ceb67150afe3d460d9649f8cc29358157a73e4 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp
index 73c3d9deef72d4fc14d50ea828c62c12a70875ae..d5ceb67150afe3d460d9649f8cc29358157a73e4 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
index 028ca42ac98be6df34bb19b73361400fa773673a..de45214050ebb4b78cc97ec5d59f1da01fe6dee1 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp
index c8d03fce31b871534252bd63b4ae10f1acca7666..83e7da7ba21ef83d432ca6f0914b8c0fc4057942 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "drivers/stm32_sgm.h"
 #include "board_settings.h"
 
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp
index 39b2e2b1e4175aef462f852ebc4157cabe8e2f2f..55d1fe33dfb97c6ddedfa644b07155fd905250fa 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 #include "hwmapping.h"
 
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
index 71b05b127bc65cc8650e6220479bc252fb3509ea..c6104c4037dd7363499efcf2cd56c626f1d2b02c 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 // #include "kernel/IRQDisplayPrint.h"
 
diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp
index 2039114f546116f941842cc362f6ac72ab586ac3..91e068ad8c5a7593294f0212603a6ae553321ba5 100644
--- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 // #include "kernel/IRQDisplayPrint.h"
 
diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp
index 73b3badc2e0805648b6c1cd517512bbe5e5ddf07..830d5e5ef62ded56cbaaace0e711308198b3641d 100644
--- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp
index 75ab0b6e710d7311465323868c0aa63e7b53caca..be7177b4044b45fe9ae7114c65ae539665662051 100644
--- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp
index 24bb3571ff11ec9fb8fde08c1a1604d675379e6a..f51613564a3d99cd602de08a52cfb0720fd01ed4 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp
@@ -23,29 +23,32 @@
  *                                                                         *
  *   You should have received a copy of the GNU General Public License     *
  *   along with this program; if not, see <http://www.gnu.org/licenses/>   *
- ***************************************************************************/ 
+ ***************************************************************************/
 
 /***********************************************************************
-* bsp.cpp Part of the Miosix Embedded OS.
-* Board support package, this file initializes hardware.
-************************************************************************/
+ * bsp.cpp Part of the Miosix Embedded OS.
+ * Board support package, this file initializes hardware.
+ ************************************************************************/
+
+#include "interfaces/bsp.h"
 
-#include <cstdlib>
 #include <inttypes.h>
 #include <sys/ioctl.h>
-#include "interfaces/bsp.h"
-#include "kernel/kernel.h"
-#include "kernel/sync.h"
+
+#include <cstdlib>
+
+#include "board_settings.h"
+#include "config/miosix_settings.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
+#include "drivers/serial.h"
+#include "filesystem/console/console_device.h"
+#include "filesystem/file_access.h"
+#include "interfaces/arch_registers.h"
 #include "interfaces/delays.h"
 #include "interfaces/portability.h"
-#include "interfaces/arch_registers.h"
-#include "config/miosix_settings.h"
+#include "kernel/kernel.h"
 #include "kernel/logging.h"
-#include "filesystem/file_access.h"
-#include "filesystem/console/console_device.h"
-#include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
-#include "board_settings.h"
+#include "kernel/sync.h"
 
 namespace miosix {
 
@@ -68,7 +71,12 @@ void IRQbspInit()
     GPIOE->OSPEEDR=0xaaaaaaaa;
     GPIOF->OSPEEDR=0xaaaaaaaa;
     GPIOH->OSPEEDR=0xaaaaaaaa;
-    _led::mode(Mode::OUTPUT);
+
+    userLed1::mode(Mode::OUTPUT);
+    userLed2::mode(Mode::OUTPUT);
+    userLed3::mode(Mode::OUTPUT);
+    userBtn::mode(Mode::INPUT);
+
     ledOn();
     delayMs(100);
     ledOff();
@@ -104,7 +112,7 @@ void shutdown()
 void reboot()
 {
     ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
-    
+
     #ifdef WITH_FILESYSTEM
     FilesystemManager::instance().umountAll();
     #endif //WITH_FILESYSTEM
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h
index 6dcfe5b9575c98c5d30afca377077cc5cb2e7056..42e9f5968ebf8726339a321832f72f8691738b80 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h
+++ b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h
@@ -45,20 +45,39 @@ namespace miosix {
 
 /**
  * \internal
- * used by the ledOn() and ledOff() implementation
+ * Board pin definition
  */
-typedef Gpio<GPIOB_BASE,14> _led;
+typedef Gpio<GPIOB_BASE,0> userLed1;
+typedef Gpio<GPIOB_BASE,7> userLed2;
+typedef Gpio<GPIOB_BASE,14> userLed3;
+typedef Gpio<GPIOC_BASE,13> userBtn;
 
 inline void ledOn()
 {
-    _led::high();
+    userLed1::high();
+    userLed2::high();
+    userLed3::high();
 }
 
 inline void ledOff()
 {
-    _led::low();
+    userLed1::low();
+    userLed2::low();
+    userLed3::low();
 }
 
+inline void led1On() { userLed1::high(); }
+
+inline void led1Off() { userLed1::low(); }
+
+inline void led2On() { userLed2::high(); }
+
+inline void led2Off() { userLed2::low(); }
+
+inline void led3On() { userLed3::high(); }
+
+inline void led3Off() { userLed3::low(); }
+
 /**
  * Polls the SD card sense GPIO.
  * 
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1024k+256k_rom.ld b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld
similarity index 73%
rename from miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1024k+256k_rom.ld
rename to miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld
index ed31c59f885b96464028ceafac21eb6a254efb0f..1f81bdcc8c5aa7ce380d9141337a405a7297d5bd 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1024k+256k_rom.ld
+++ b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld
@@ -1,14 +1,14 @@
 /*
- * C++ enabled linker script for stm32 (1M FLASH, 256K RAM)
+ * C++ enabled linker script for stm32f746zg (1M FLASH, 256K RAM)
  * Developed by TFT: Terraneo Federico Technologies
  * Optimized for use with the Miosix kernel
  */
 
 /*
  * This linker script puts:
- * - read only data and code (.text, .rodata, .eh_*) in flash
- * - stacks, heap and sections .data and .bss in the internal ram
- * - the external ram (if available) is not used.
+ * - read only data and code (.text, .rodata, .eh_*) in FLASH
+ * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 64KB RAM
+ * - .data, .bss, stacks and heap in the internal RAM.
  */
 
 /*
@@ -36,33 +36,35 @@
  * Note: if increasing the main stack size also increase the ORIGIN value in
  * the MEMORY definitions below accordingly.
  */
-_main_stack_size = 0x00000200;                     /* main stack = 512Bytes */
+
+_main_stack_size = 512;                             /* main stack = 512Bytes */
 _main_stack_top  = 0x20000000 + _main_stack_size;
 ASSERT(_main_stack_size   % 8 == 0, "MAIN stack size error");
 
-/* end of the heap on 320KB microcontrollers */
-_heap_end = 0x20050000;                            /* end of available ram  */
+/* Mapping the heap to the end of SRAM2 */
+_heap_end = 0x20000000 + 320K;                       /* end of available ram */
 
-/* identify the Entry Point  */
+/* Identify the Entry Point  */
 ENTRY(_Z13Reset_Handlerv)
 
-/* specify the memory areas  */
+/*
+ * Specify the memory areas
+ *
+ * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled
+ * Memory). Technically, we could use this as normal RAM as there's a way for
+ * the DMA to access it, but the datasheet is unclear about performance
+ * penalties for doing so. To avoid nonuniform DMA memory access latencies,
+ * we leave this 64KB DTCM unused except for the first 512Bytes which are for
+ * the interrupt stack. This leaves us with 384KB of RAM
+ */
 MEMORY
 {
-    flash(rx)   : ORIGIN = 0x08000000, LENGTH = 1M
-
-    /*
-     * NOTE: starting at 0x20000000 there's 64KB of DTCM. Technically, we could
-     * use this as normal RAM as there's a way the DMA can access it, but the
-     * datasheet is unclear about performance penalties for doing so.
-     * To avoid nonuniform DMA memory access latencies, we leve this 64KB DTCM
-     * unused except for the first 512Bytes which are for the interrupt stack.
-     * This leaves us with 256KB of RAM
-     */
-    ram(wx)     : ORIGIN = 0x20010000, LENGTH =  256K
+    sram(wx)  : ORIGIN = 0x20010000, LENGTH = 256K
+    dtcm(wx)  : ORIGIN = 0x20000000, LENGTH = 64K     /* Used for main stack */
+    flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M
 }
 
-/* now define the output sections  */
+/* Now define the output sections  */
 SECTIONS
 {
     . = 0;
@@ -76,10 +78,10 @@ SECTIONS
         *(.text)
         *(.text.*)
         *(.gnu.linkonce.t.*)
-        /* these sections for thumb interwork? */
+        /* These sections for thumb interwork? */
         *(.glue_7)
         *(.glue_7t)
-        /* these sections for C++? */
+        /* These sections for C++? */
         *(.gcc_except_table)
         *(.gcc_except_table.*)
         *(.ARM.extab*)
@@ -145,8 +147,10 @@ SECTIONS
     } > flash
     __exidx_end = .;
 
-	/* .data section: global variables go to ram, but also store a copy to
-       flash to initialize them */
+	/*
+     * .data section: global variables go to sram, but also store a copy to
+     * flash to initialize them
+     */
     .data : ALIGN(8)
     {
         _data = .;
@@ -155,10 +159,10 @@ SECTIONS
         *(.gnu.linkonce.d.*)
         . = ALIGN(8);
         _edata = .;
-    } > ram AT > flash
+    } > sram AT > flash
     _etext = LOADADDR(.data);
 
-    /* .bss section: uninitialized global variables go to ram */
+    /* .bss section: uninitialized global variables go to sram */
     _bss_start = .;
     .bss :
     {
@@ -166,7 +170,7 @@ SECTIONS
         *(.bss.*)
         *(.gnu.linkonce.b.*)
         . = ALIGN(8);
-    } > ram
+    } > sram
     _bss_end = .;
 
     _end = .;
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
index bed5fa4ca14bbb3b78e72f7aa829ebd245b2b85b..af0ba546e2535096cb2e382afdebf0e78985b9b9 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
@@ -41,6 +41,7 @@
 #include "config/miosix_settings.h"
 #include "drivers/serial.h"
 #include "drivers/serial_stm32.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "filesystem/console/console_device.h"
 #include "filesystem/file_access.h"
 #include "interfaces/arch_registers.h"
@@ -49,7 +50,6 @@
 #include "kernel/kernel.h"
 #include "kernel/logging.h"
 #include "kernel/sync.h"
-#include "drivers/sd_stm32f2_f4.h"
 
 namespace miosix {
 
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld
index 5047a8347f5460309b4c009d637985ba56e840ee..ba3da77bb0be5c7bd8f0ae9d06eaecd21882fab3 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld
@@ -37,7 +37,7 @@
  * the MEMORY definitions below accordingly.
  */
 
-_main_stack_size = 0x00000200;                     /* main stack = 512Bytes */
+_main_stack_size = 512;                             /* main stack = 512Bytes */
 _main_stack_top  = 0x20000000 + _main_stack_size;
 ASSERT(_main_stack_size   % 8 == 0, "MAIN stack size error");
 
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
index b1d2b2ba794694ba5d8b516b85c59932b967c8a2..ae2ecdedb2cb1c9ce2a669e280547ccd8a8b2824 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
@@ -27,7 +27,7 @@ void program_startup()
     // enabled
     __disable_irq();
 
-    miosix::IRQconfigureCache();
+    miosix::IRQconfigureCache((const unsigned int*)0xc0000000, 16 * 1024 * 1024);
 
     // These are defined in the linker script
     extern unsigned char _etext asm("_etext");
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
index f53112d374c4ab62baa57ebaead176f527bf317b..51fe420bade283f539eb6ced7031b0226ff1e282 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
@@ -41,6 +41,7 @@
 #include "config/miosix_settings.h"
 #include "drivers/serial.h"
 #include "drivers/serial_stm32.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "filesystem/console/console_device.h"
 #include "filesystem/file_access.h"
 #include "interfaces/arch_registers.h"
@@ -266,7 +267,9 @@ void IRQbspInit()
 
 void bspInit2()
 {
-    // Nothing to do
+    #ifdef WITH_FILESYSTEM
+    basicFilesystemSetup(SDIODriver::instance());
+    #endif  // WITH_FILESYSTEM
 }
 
 //
@@ -277,6 +280,10 @@ void shutdown()
 {
     ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
 
+    #ifdef WITH_FILESYSTEM
+    FilesystemManager::instance().umountAll();
+    #endif  // WITH_FILESYSTEM
+
     disableInterrupts();
     for(;;) ;
 }
@@ -285,6 +292,10 @@ void reboot()
 {
     ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
 
+    #ifdef WITH_FILESYSTEM
+    FilesystemManager::instance().umountAll();
+    #endif  // WITH_FILESYSTEM
+
     disableInterrupts();
     miosix_private::IRQsystemReboot();
 }
diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp
index 9dbc25d762aea61e8c8a743a7ba782ee17443604..5217db4cf3fe1b72305e4582e2bf7b68eb1a01a9 100644
--- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp
@@ -44,7 +44,7 @@
 #include "filesystem/file_access.h"
 #include "filesystem/console/console_device.h"
 #include "drivers/serial.h"
-#include "drivers/sd_stm32f2_f4.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
 #include "board_settings.h"
 
 namespace miosix {
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index 9a79a522de313d8e3734c162f57d52e932239d46..d30bc47dd1c5346a400e15a44b07d47422dc98de 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -1768,7 +1768,7 @@ else ifeq ($(ARCH),cortexM4_stm32f4)
     $(ARCH_INC)/interfaces-impl/portability.cpp              \
     $(ARCH_INC)/interfaces-impl/delays.cpp                   \
     $(ARCH_INC)/interfaces-impl/gpio_impl.cpp                \
-    arch/common/drivers/sd_stm32f2_f4.cpp                    \
+    arch/common/drivers/sd_stm32f2_f4_f7.cpp                 \
     arch/common/core/stm32f2_f4_l4_f7_h7_os_timer.cpp        \
     arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
 
@@ -1794,7 +1794,7 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
         ## Select architecture specific files
         ## These are the files in arch/<arch name>/<board name>
         ARCH_SRC :=                                  \
-        arch/common/drivers/sd_stm32f2_f4.cpp        \
+        arch/common/drivers/sd_stm32f2_f4_f7.cpp     \
         $(BOARD_INC)/interfaces-impl/delays.cpp      \
         $(BOARD_INC)/interfaces-impl/bsp.cpp
 
@@ -1833,7 +1833,7 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
         ## Select architecture specific files
         ## These are the files in arch/<arch name>/<board name>
         ARCH_SRC :=                                  \
-        arch/common/drivers/sd_stm32f2_f4.cpp        \
+        arch/common/drivers/sd_stm32f2_f4_f7.cpp     \
         $(BOARD_INC)/interfaces-impl/delays.cpp      \
         $(BOARD_INC)/interfaces-impl/bsp.cpp
 
@@ -1975,7 +1975,7 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
         ## Select architecture specific files
         ## These are the files in arch/<arch name>/<board name>
         ARCH_SRC :=                                  \
-        arch/common/drivers/sd_stm32f2_f4.cpp        \
+        arch/common/drivers/sd_stm32f2_f4_f7.cpp     \
         arch/common/drivers/stm32f2_f4_i2c.cpp       \
         arch/common/drivers/servo_stm32.cpp          \
         $(BOARD_INC)/interfaces-impl/delays.cpp      \
@@ -2230,19 +2230,22 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
         ## Select linker script and boot file
         ## Their path must be relative to the miosix directory.
         BOOT_FILE := $(BOARD_INC)/core/stage_1_boot.o
-        LINKER_SCRIPT := $(BOARD_INC)/stm32_1024k+256k_rom.ld
+        LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+256k_rom.ld
 
         ## Select architecture specific files
         ## These are the files in arch/<arch name>/<board name>
         ARCH_SRC :=                                  \
         arch/common/drivers/stm32_hardware_rng.cpp   \
-        arch/common/drivers/sd_stm32f2_f4.cpp        \
         $(BOARD_INC)/interfaces-impl/bsp.cpp
 
         ## Add a #define to allow querying board name
         CFLAGS_BASE   += -D_BOARD_STM32F746ZG_NUCLEO
         CXXFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO
 
+        ## Select the SDMMC peripheral to use for the filesystem
+        SD := -D__SDMMC1
+        # SD := -D__SDMMC2
+
         ## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
         CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
 
@@ -2273,13 +2276,16 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
         ## Select architecture specific files
         ## These are the files in arch/<arch name>/<board name>
         ARCH_SRC :=                           \
-        arch/common/drivers/sd_stm32f2_f4.cpp \
         $(BOARD_INC)/interfaces-impl/bsp.cpp
 
         ## Add a #define to allow querying board name
         CFLAGS_BASE   += -D_BOARD_STM32F767ZI_NUCLEO
         CXXFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO
 
+        ## Select the SDMMC peripheral to use for the filesystem
+        SD := -D__SDMMC1
+        # SD := -D__SDMMC2
+
         ## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
         CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
 
@@ -2319,6 +2325,10 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
         ## Enables the initialization of the external 16MB SDRAM memory
         XRAM := -D__ENABLE_XRAM
 
+        ## Select the SDMMC peripheral to use for the filesystem
+        # SD := -D__SDMMC1
+        SD := -D__SDMMC2
+
         ## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
         CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_216MHz=216000000
 
@@ -2350,9 +2360,9 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
 
     AFLAGS_BASE   := $(ARCHOPTS)
     CFLAGS_BASE   += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
-                     $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
+                     $(SD) $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
     CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
-                     $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
+                     $(SD) $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
     LFLAGS_BASE   := $(ARCHOPTS) -Wl,--gc-sections,-Map,main.map                \
                      -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT)              \
                      $(OPT_OPTIMIZATION) -nostdlib
@@ -2364,13 +2374,14 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
     arch/common/core/mpu_cortexMx.cpp                        \
     arch/common/core/cache_cortexMx.cpp                      \
     arch/common/drivers/serial_stm32.cpp                     \
+    arch/common/drivers/sd_stm32f2_f4_f7.cpp                 \
     arch/common/drivers/dcc.cpp                              \
     $(ARCH_INC)/interfaces-impl/portability.cpp              \
     $(ARCH_INC)/interfaces-impl/delays.cpp                   \
     $(ARCH_INC)/interfaces-impl/gpio_impl.cpp                \
     arch/common/core/stm32f2_f4_l4_f7_h7_os_timer.cpp        \
     arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
-    
+
 ##-----------------------------------------------------------------------------
 ## ARCHITECTURE: cortexM7_stm32h7
 ##
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
index f6149c754c646f87dcc9c33a689c9b2927543fd8..1efee096f0212350fa935f4d6d9d8d0f82a5c80c 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
@@ -41,11 +41,10 @@ namespace miosix {
  */
 
 /// Size of stack for main().
-/// The C standard library is stack-heavy (iprintf requires 1KB) 
+/// The C standard library is stack-heavy (iprintf requires 1KB)
 const unsigned int MAIN_STACK_SIZE=4*1024;
 
 /// Serial port
-//This board only exposes USART3, without flow control, connected to an UART/USB
 const unsigned int defaultSerialSpeed=115200;
 // #define SERIAL_1_DMA
 // #define SERIAL_2_DMA
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
index bc4f4676f22096e2a6cd567c7ccada3d6a2a2360..ba0551e10d606131e371473d748f7f91099106d6 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
@@ -45,7 +45,6 @@ namespace miosix {
 const unsigned int MAIN_STACK_SIZE=4*1024;
 
 /// Serial port
-// This board only exposes USART3, without flow control
 const unsigned int defaultSerialSpeed=115200;
 // #define SERIAL_1_DMA
 // #define SERIAL_2_DMA
@@ -53,7 +52,7 @@ const unsigned int defaultSerialSpeed=115200;
 
 //SD card driver
 static const unsigned char sdVoltage=33; //Board powered @ 3.3V
-#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus
+// #define SD_ONE_BIT_DATABUS
 
 /**
  * \}
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
index e230178f64a8a681bf984b752715b442c700d908..775f7850c336180913980c224b599a697c782027 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
@@ -47,12 +47,13 @@ const unsigned int MAIN_STACK_SIZE=4*1024;
 /// Serial port
 const unsigned int defaultSerial=1;
 const unsigned int defaultSerialSpeed=115200;
-// #define SERIAL_1_DMA
+#define SERIAL_1_DMA
 // #define SERIAL_2_DMA
 // #define SERIAL_3_DMA
 
 // SD card driver
 static const unsigned char sdVoltage=33; //Board powered @ 3.3V
+// #define SD_ONE_BIT_DATABUS
 
 /**
  * \}
diff --git a/miosix_np_2/nbproject/configurations.xml b/miosix_np_2/nbproject/configurations.xml
index 259cd5e0e53e6347f0f15f2e44c9f6c4c29b52b6..1f7805cc54c0e2abd35cf8f7364f197cb723b29b 100644
--- a/miosix_np_2/nbproject/configurations.xml
+++ b/miosix_np_2/nbproject/configurations.xml
@@ -82,7 +82,7 @@
               <in>sd_stm32f1.cpp</in>
               <in>sd_stm32f1.h</in>
               <in>sd_stm32f2_f4.cpp</in>
-              <in>sd_stm32f2_f4.h</in>
+              <in>sd_stm32f2_f4_f7.h</in>
               <in>serial_efm32.cpp</in>
               <in>serial_lpc2000.cpp</in>
               <in>serial_stm32.cpp</in>
@@ -603,7 +603,7 @@
             tool="3"
             flavor2="0">
       </item>
-      <item path="../miosix/arch/common/drivers/sd_stm32f2_f4.h"
+      <item path="../miosix/arch/common/drivers/sd_stm32f2_f4_f7.h"
             ex="false"
             tool="3"
             flavor2="0">
diff --git a/miosix_np_2/nbproject/private/configurations.xml b/miosix_np_2/nbproject/private/configurations.xml
index f63d12e98889bdce40c13597e4a35bd128a54599..d0f4669ee0edd8300904fe12204f9bb16b019aa6 100644
--- a/miosix_np_2/nbproject/private/configurations.xml
+++ b/miosix_np_2/nbproject/private/configurations.xml
@@ -204,7 +204,7 @@
               <in>sd_stm32f1.cpp</in>
               <in>sd_stm32f1.h</in>
               <in>sd_stm32f2_f4.cpp</in>
-              <in>sd_stm32f2_f4.h</in>
+              <in>sd_stm32f2_f4_f7.h</in>
               <in>serial.h</in>
               <in>serial_efm32.cpp</in>
               <in>serial_efm32.h</in>