diff --git a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c index 750fe1af2c6e75b6dd5af876b508141c3d378644..e9395fc315c57f76ad9d832df39502a323b8e454 100644 --- a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c +++ b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c @@ -402,7 +402,7 @@ static void SetSysClock(void) FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; #else //_BOARD_SONY_NEWMAN //By TFT: Three wait states seem to make it unstable (crashing) when CPU load is high - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_4WS; + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_7WS; #endif //_BOARD_SONY_NEWMAN /* Select the main PLL as system clock source */ diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp index c1d8e15d8b76241b8e16559f22341288c753afc7..3d5a8f96263efba31cb84ad31098cbc78a37c1a6 100644 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp +++ b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp @@ -564,7 +564,7 @@ void PowerManagement::IRQsetPrescalers() FLASH->ACR=FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_4WS; + | FLASH_ACR_LATENCY_7WS; break; case FREQ_26MHz: RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK @@ -574,7 +574,7 @@ void PowerManagement::IRQsetPrescalers() FLASH->ACR=FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_0WS; + | FLASH_ACR_LATENCY_1WS; break; } }