From 8f19fd78abbcfdc37c0b1913f0362b407cd7c2fd Mon Sep 17 00:00:00 2001 From: Terraneo Federico <fede.tft@hotmail.it> Date: Thu, 2 Jan 2014 20:28:04 +0000 Subject: [PATCH] Wait states fix for sony-newman bsp --- miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c | 2 +- .../stm32f205rg_sony-newman/interfaces-impl/bsp.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c index 750fe1af..e9395fc3 100644 --- a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c +++ b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c @@ -402,7 +402,7 @@ static void SetSysClock(void) FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; #else //_BOARD_SONY_NEWMAN //By TFT: Three wait states seem to make it unstable (crashing) when CPU load is high - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_4WS; + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_7WS; #endif //_BOARD_SONY_NEWMAN /* Select the main PLL as system clock source */ diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp index c1d8e15d..3d5a8f96 100644 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp +++ b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp @@ -564,7 +564,7 @@ void PowerManagement::IRQsetPrescalers() FLASH->ACR=FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_4WS; + | FLASH_ACR_LATENCY_7WS; break; case FREQ_26MHz: RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK @@ -574,7 +574,7 @@ void PowerManagement::IRQsetPrescalers() FLASH->ACR=FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_0WS; + | FLASH_ACR_LATENCY_1WS; break; } } -- GitLab