From 8f5d36a4da9910cb65c8ef1dc3910e6357e2cc62 Mon Sep 17 00:00:00 2001
From: Davide Mor <tazdevil971@gmail.com>
Date: Sun, 4 Feb 2024 00:29:44 +0100
Subject: [PATCH] [compute_unit_v2] Tried to enable 32MB XRAM

---
 .../stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp   | 2 +-
 .../{stm32_2m+16m_xram.ld => stm32_2m+32m_xram.ld}        | 8 ++++----
 miosix/config/options.cmake                               | 4 ++--
 3 files changed, 7 insertions(+), 7 deletions(-)
 rename miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/{stm32_2m+16m_xram.ld => stm32_2m+32m_xram.ld} (95%)

diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
index 8c6ffafe..12d926fa 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp
@@ -168,7 +168,7 @@ void configureSdram() {
                          | FMC_SDCR2_NB        // 4 internal banks
                          | FMC_SDCR2_MWID_0    // 16 bit data bus
                          | FMC_SDCR2_NR_1      // 13 bit row address
-                         | 0;                  // 8 bit column address
+                         | FMC_SDCR2_NC_1;     // 9 bit column address
 
     // 2. Memory device timings
     #ifdef SYSCLK_FREQ_216MHz
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+16m_xram.ld b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+32m_xram.ld
similarity index 95%
rename from miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+16m_xram.ld
rename to miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+32m_xram.ld
index 5b3545ab..044ba1c6 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+16m_xram.ld
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/stm32_2m+32m_xram.ld
@@ -1,5 +1,5 @@
 /*
- * C++ enabled linker script for stm32f769ni (2M FLASH, 512K RAM, 16MB XRAM)
+ * C++ enabled linker script for stm32f767zi (2M FLASH, 512K RAM, 32MB XRAM)
  * Developed by TFT: Terraneo Federico Technologies
  * Optimized for use with the Miosix kernel
  */
@@ -8,7 +8,7 @@
  * This linker script puts:
  * - read only data and code (.text, .rodata, .eh_*) in FLASH
  * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM
- * - .data, .bss, stacks and heap in the external 16MB SDRAM.
+ * - .data, .bss, stacks and heap in the external 32MB SDRAM.
  */
 
 /*
@@ -42,7 +42,7 @@ _main_stack_top  = 0x20000000 + _main_stack_size;
 ASSERT(_main_stack_size   % 8 == 0, "MAIN stack size error");
 
 /* Mapping the heap into XRAM */
-_heap_end = 0xd0000000 + 16M;                        /* end of available ram */
+_heap_end = 0xd0000000 + 32M;                        /* end of available ram */
 
 /* Identify the Entry Point  */
 ENTRY(_Z13Reset_Handlerv)
@@ -59,7 +59,7 @@ ENTRY(_Z13Reset_Handlerv)
  */
 MEMORY
 {
-    xram(wx)  : ORIGIN = 0xd0000000, LENGTH =  16M
+    xram(wx)  : ORIGIN = 0xd0000000, LENGTH =  32M
     sram(wx)  : ORIGIN = 0x20020000, LENGTH = 384K
     dtcm(wx)  : ORIGIN = 0x20000000, LENGTH = 128K    /* Used for main stack */
     bram(rw)  : ORIGIN = 0x40024000, LENGTH =   4K    /* Bakup SRAM */
diff --git a/miosix/config/options.cmake b/miosix/config/options.cmake
index 28a3c926..2753b8dc 100644
--- a/miosix/config/options.cmake
+++ b/miosix/config/options.cmake
@@ -3231,7 +3231,7 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
         ## Their path must be relative to the miosix directory.
         set(BOOT_FILE ${KPATH}/${BOARD_INC}/core/stage_1_boot.cpp)
         # set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+384k_ram.ld)
-        set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+16m_xram.ld)
+        set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+32m_xram.ld)
 
         ## Enables the initialization of the external SDRAM memory
         set(XRAM -D__ENABLE_XRAM)
@@ -3275,7 +3275,7 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
         ## Their path must be relative to the miosix directory.
         set(BOOT_FILE ${KPATH}/${BOARD_INC}/core/stage_1_boot.cpp)
         set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+384k_ram.ld)
-        # set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+16m_xram.ld)
+        # set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+32m_xram.ld)
 
         ## Enables the initialization of the external SDRAM memory
         set(XRAM -D__ENABLE_XRAM)
-- 
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