diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_all_in_xram.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_all_in_xram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..94dfa62fb943573fa997793ac55a9051099bd3db
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_all_in_xram.ld
@@ -0,0 +1,144 @@
+/*
+ * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram
+ * Developed by TFT: Terraneo Federico Technologies
+ * Optimized for use with the Miosix kernel
+ */
+
+/*
+ * This linker script puts:
+ * - all (code, .data, .bss, stacks, heap) in the external ram.
+ * It is most useful for debugging, since powercycling the board will erase code
+ */
+
+/*
+ * The main stack is used for interrupt handling by the kernel.
+ * In this linker script the main stack is placed at the top of the ram since:
+ * - having 2MB of ram makes the "stack at bottom of ram" optimization useless
+ * - the interrupt vectors are forwarded at the bottom of the ram
+ */
+_main_stack_size = 0x00000200; /* main stack size = 512Bytes */
+ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
+
+/* end of the stack */
+_main_stack_top = 0x60080000; /* placed at the top of ram */
+_heap_end = _main_stack_top - _main_stack_size;
+
+/* identify the Entry Point */
+ENTRY(_ZN6miosix13Reset_HandlerEv)
+
+/* specify the memory areas */
+MEMORY
+{
+ ram(wx) : ORIGIN = 0x60000000, LENGTH = 512K
+}
+
+/* now define the output sections */
+SECTIONS
+{
+ . = 0;
+
+ /* .text section: code goes to flash */
+ .text :
+ {
+ /* Startup code must go at address 0 */
+ KEEP(*(.isr_vector))
+
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ /* these sections for thumb interwork? */
+ *(.glue_7)
+ *(.glue_7t)
+ /* these sections for C++? */
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.ARM.extab*)
+ *(.gnu.linkonce.armextab.*)
+
+ . = ALIGN(4);
+ /* .rodata: constant data */
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ /* C++ Static constructors/destructors (eabi) */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __miosix_init_array_start = .;
+ KEEP (*(SORT(.miosix_init_array.*)))
+ KEEP (*(.miosix_init_array))
+ __miosix_init_array_end = .;
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /* C++ Static constructors/destructors (elf) */
+ . = ALIGN(4);
+ _ctor_start = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ _ctor_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > ram
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > ram
+ __exidx_end = .;
+
+ /* .data section: global variables go to ram, but also store a copy to
+ flash to initialize them */
+ .data : ALIGN(8)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ _edata = .;
+ } > ram
+ _etext = LOADADDR(.data);
+
+ /* .bss section: uninitialized global variables go to ram */
+ _bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ . = ALIGN(8);
+ } > ram
+ _bss_end = .;
+
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram.ld
similarity index 92%
rename from miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld
rename to miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram.ld
index cf07f04081c69941e7737afc4dbf4ef62675678e..4b70fa6f0dce12096c9d583a3849efbde67b3dd6 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram.ld
@@ -1,5 +1,5 @@
/*
- * C++ enabled linker script for stm32 (1M FLASH, 128K RAM)
+ * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram
* Developed by TFT: Terraneo Federico Technologies
* Optimized for use with the Miosix kernel
*/
@@ -7,8 +7,8 @@
/*
* This linker script puts:
* - read only data and code (.text, .rodata, .eh_*) in flash
- * - stacks, heap and sections .data and .bss in the internal ram
- * - the external ram (if available) is not used.
+ * - stack for interrupt handling, sections .data and .bss in the internal ram
+ * - heap and stack of threads in the external ram
*/
/*
@@ -40,8 +40,9 @@ _main_stack_size = 0x00000200; /* main stack = 512Bytes */
_main_stack_top = 0x20000000 + _main_stack_size;
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
-/* end of the heap on 128KB microcontrollers */
-_heap_end = 0x20020000; /* end of available ram */
+/* Mapping the heap into external RAM (512KB) */
+_end = 0x60000000;
+_heap_end = 0x60080000;
/* identify the Entry Point */
ENTRY(_ZN6miosix13Reset_HandlerEv)
@@ -49,7 +50,7 @@ ENTRY(_ZN6miosix13Reset_HandlerEv)
/* specify the memory areas */
MEMORY
{
- flash(rx) : ORIGIN = 0, LENGTH = 1M
+ flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M
/*
* Note, the ram starts at 0x20000000 but it is necessary to add the size
@@ -165,6 +166,6 @@ SECTIONS
} > ram
_bss_end = .;
- _end = .;
- PROVIDE(end = .);
+ /*_end = .;*/
+ /*PROVIDE(end = .);*/
}
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram_processes.ld
similarity index 62%
rename from miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld
rename to miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram_processes.ld
index 7658faf0bc69b166ab345724c8c86f67cdf7459a..99cbddd44c0f3a76b20e712b3f19887753722353 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_xram_processes.ld
@@ -1,47 +1,28 @@
/*
- * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 512KB XRAM
+ * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 512KB xram
* Developed by TFT: Terraneo Federico Technologies
* Optimized for use with the Miosix kernel
*/
/*
* This linker script puts:
- * - read only data and code (.text, .rodata, .eh_*) in xram
- * - stacks, heap and sections .data and .bss in the internal ram
- * It is most useful for debugging, since powercycling the board will erase code
+ * - read only data and code (.text, .rodata, .eh_*) in Flash
+ * - process pool in Flash
+ * - stack for interrupt handling, sections .data and .bss in the internal RAM
+ * - kernel pool in internal RAM
+ * - process pool in external RAM
*/
-/*
- * The main stack is used for interrupt handling by the kernel.
- *
- * *** Readme ***
- * This linker script places the main stack (used by the kernel for interrupts)
- * at the bottom of the ram, instead of the top. This is done for two reasons:
- *
- * - as an optimization for microcontrollers with little ram memory. In fact
- * the implementation of malloc from newlib requests memory to the OS in 4KB
- * block (except the first block that can be smaller). This is probably done
- * for compatibility with OSes with an MMU and paged memory. To see why this
- * is bad, consider a microcontroller with 8KB of ram: when malloc finishes
- * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
- * fail because the top part of the ram is used by the main stack. As a
- * result, the top part of the memory will not be used by malloc, even if
- * available (and it is nearly *half* the ram on an 8KB mcu). By placing the
- * main stack at the bottom of the ram, the upper 4KB block will be entirely
- * free and available as heap space.
- *
- * - In case of main stack overflow the cpu will fault because access to memory
- * before the beginning of the ram faults. Instead with the default stack
- * placement the main stack will silently collide with the heap.
- * Note: if increasing the main stack size also increase the ORIGIN value in
- * the MEMORY definitions below accordingly.
- */
_main_stack_size = 0x00000200; /* main stack = 512Bytes */
_main_stack_top = 0x20000000 + _main_stack_size;
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
-/* end of the heap on 128KB microcontrollers */
-_heap_end = 0x20020000; /* end of available ram */
+/* Mapping the kernel heap into internal RAM */
+_heap_end = 0x20000000+128*1024;
+
+/* Mapping the process pool into external RAM */
+_process_pool_start = 0x60000000;
+_process_pool_end = 0x60080000;
/* identify the Entry Point */
ENTRY(_ZN6miosix13Reset_HandlerEv)
@@ -49,13 +30,13 @@ ENTRY(_ZN6miosix13Reset_HandlerEv)
/* specify the memory areas */
MEMORY
{
- xram(rx) : ORIGIN = 0x60000000, LENGTH = 512K
+ flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M
/*
* Note, the ram starts at 0x20000000 but it is necessary to add the size
* of the main stack, so it is 0x20000200.
*/
- ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200
+ ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200
}
/* now define the output sections */
@@ -131,14 +112,14 @@ SECTIONS
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
- } > xram
+ } > flash
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > xram
+ } > flash
__exidx_end = .;
/* .data section: global variables go to ram, but also store a copy to
@@ -151,7 +132,7 @@ SECTIONS
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_edata = .;
- } > ram AT > xram
+ } > ram AT > flash
_etext = LOADADDR(.data);
/* .bss section: uninitialized global variables go to ram */
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index 39f9b080bd97ef2f2f952bd3b4b8aa4c2e17e043..8106b53c2419d13dd8a3c276dfb9db65adfe7422 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -241,24 +241,27 @@ endif
##
ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2)
- ## Linker script type, there are two options
- ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld)
- ## the most common choice, available for all microcontrollers
- ## 2) Code in external RAM, stack + heap in internal RAM
- ## (file *_code_in_xram.ld) useful for debugging. Code runs
- ## *very* slow compared to FLASH. Works only with a booloader that
- ## forwards interrrupts @ 0x60000000 (see miosix/_tools/bootloaders for
- ## one).
- ## You must -D__CODE_IN_XRAM below.
+ ## Linker script type
+ ## 1) Code in FLASH, all kernel data in internal RAM, external RAM reserved
+ ## for the process pool (file *_xram_processes.ld) to configure the
+ ## kernel with "#define WITH_PROCESSES"
+ ## 2) Code in FLASH .data .bss and interrupt stack in internal RAM, heap in
+ ## external RAM (file *_xram.ld). Kernel runs slower but has more RAM
+ ## 3) Code + stack + heap in external RAM, (file *_all_in_xram.ld)
+ ## useful for debugging code. Code runs *very* slow compared to FLASH.
+ ## Works only with a booloader that forwards interrrupts @ 0x6000000
+ ## (see miosix/_tools/bootloaders for one). The microcontroller must have
+ ## an external memory interface. You must -D__CODE_IN_XRAM below.
LINKER_SCRIPT_PATH := arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/
- #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_rom.ld
- LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_code_in_xram.ld
+ LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_xram_processes.ld
+ #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_xram.ld
+ #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_all_in_xram.ld
- ## XRAM is always enabled on this board, even if the _rom linker script
- ## does not make explicit use of it.
+ ## XRAM is always enabled on this board, if you don't want the kernel to
+ ## use it select the xram_processes linker script
## Uncommenting __CODE_IN_XRAM (with an appropriate linker script selected
## above) allows to run code from external RAM, useful for debugging
- XRAM := -D__CODE_IN_XRAM
+ #XRAM := -D__CODE_IN_XRAM
endif
@@ -2068,7 +2071,7 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
## The command must provide a way to program the board, or print an
## error message saying that 'make program' is not supported for that
## board.
- ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_1m+128k_code_in_xram.ld)
+ ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_1m+128k_all_in_xram.ld)
PROG ?= $(KPATH)/_tools/bootloaders/stm32/pc_loader/pc_loader \
/dev/ttyUSB0 main.bin
else