From b4f76e5c8e8666cd9b6c5e75ba59840956ea74ab Mon Sep 17 00:00:00 2001
From: Terraneo Federico <fede.tft@miosix.org>
Date: Sun, 25 Jun 2023 20:23:06 +0200
Subject: [PATCH] Fix Cortex M0 atomic ops missing memory barrier, that caused
the testsuite to fail
---
miosix/_tools/testsuite/testsuite.cpp | 5 +++++
miosix/arch/common/core/atomic_ops_impl_cortexM0.h | 8 +++++---
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/miosix/_tools/testsuite/testsuite.cpp b/miosix/_tools/testsuite/testsuite.cpp
index eae23111..9cfeb7fa 100644
--- a/miosix/_tools/testsuite/testsuite.cpp
+++ b/miosix/_tools/testsuite/testsuite.cpp
@@ -3401,7 +3401,12 @@ static void test_22()
bool error=false;
Thread *t2=Thread::create(t22_t2,STACK_MIN,0,0,Thread::JOINABLE);
{
+ #if __CORTEX_M != 0x00
FastInterruptDisableLock dLock;
+ #else
+ //Cortex M0 does not have atomic ops, they are emulated by disabling IRQ
+ InterruptDisableLock dLock;
+ #endif
t22_v5=false;
int x=10;
diff --git a/miosix/arch/common/core/atomic_ops_impl_cortexM0.h b/miosix/arch/common/core/atomic_ops_impl_cortexM0.h
index 3890aca4..8210b695 100644
--- a/miosix/arch/common/core/atomic_ops_impl_cortexM0.h
+++ b/miosix/arch/common/core/atomic_ops_impl_cortexM0.h
@@ -51,7 +51,7 @@ inline int atomicSwap(volatile int *p, int v)
int result = *p;
*p = v;
enableInterrupts();
-
+ asm volatile("":::"memory");
return result;
}
@@ -60,6 +60,7 @@ inline void atomicAdd(volatile int *p, int incr)
disableInterrupts();
*p += incr;
enableInterrupts();
+ asm volatile("":::"memory");
}
inline int atomicAddExchange(volatile int *p, int incr)
@@ -68,7 +69,7 @@ inline int atomicAddExchange(volatile int *p, int incr)
int result = *p;
*p += incr;
enableInterrupts();
-
+ asm volatile("":::"memory");
return result;
}
@@ -78,7 +79,7 @@ inline int atomicCompareAndSwap(volatile int *p, int prev, int next)
int result = *p;
if(*p == prev) *p = next;
enableInterrupts();
-
+ asm volatile("":::"memory");
return result;
}
@@ -95,6 +96,7 @@ inline void *atomicFetchAndIncrement(void * const volatile * p, int offset,
volatile uint32_t *pt = reinterpret_cast<uint32_t*>(result) + offset;
*pt += incr;
enableInterrupts();
+ asm volatile("":::"memory");
return result;
}
--
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