diff --git a/Makefile b/Makefile
index 6c8092c395ce60ea16c806f71d2a1011ae067d4a..277dd02a7b10f04790c491ad40b99dc09f580df0 100644
--- a/Makefile
+++ b/Makefile
@@ -14,7 +14,7 @@ SUBDIRS := miosix
## List here your source files (both .s, .c and .cpp)
##
SRC := \
-main.cpp
+miosix/testsuite/testsuite.cpp
##
## List here additional static libraries with relative path
diff --git a/miosix/arch/cortexM3_stm32/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h
index b374a82f8492a64a63569aeda1a226d82205c690..8c366402c88aaba6c1ccf2fe4ad323940c02595d 100644
--- a/miosix/arch/cortexM3_stm32/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h
+++ b/miosix/arch/cortexM3_stm32/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h
@@ -37,6 +37,7 @@
#ifdef _MIOSIX
#include "interfaces/gpio.h"
+namespace miosix {
#else //_MIOSIX
#include "gpio.h"
@@ -183,4 +184,8 @@ typedef Gpio<GPIOD_BASE,13> pd13;
typedef Gpio<GPIOE_BASE,6> pe6;
typedef Gpio<GPIOB_BASE,8> pb8; //used to be Charger::en
+#ifdef _MIOSIX
+} //namespace miosix
+#else //_MIOSIX
+
#endif //HWMAPPING_H
diff --git a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c
index 7094d50524256331888a08cc8e282fc57d5d0e5b..22a3a62d2b0392b26eb9e5e2b99797bfcb41126a 100644
--- a/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c
+++ b/miosix/arch/cortexM3_stm32f2/common/CMSIS/system_stm32f2xx.c
@@ -133,7 +133,9 @@
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
//By TFT: Miosix uses the __ENABLE_XRAM macro to tell the startup code it wants XRAM
-#ifdef __ENABLE_XRAM
+//additionally, other boards may have the RAM connected in other ways, so
+//use this code only for the STM3220G_EVAL
+#if defined(__ENABLE_XRAM) && defined(_BOARD_STM3220G_EVAL)
#define DATA_IN_ExtSRAM
#endif //__ENABLE_XRAM
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg
index d9fc56da30c0390fcbdde5a4791252ae662f783f..559b22c67ee503eb601a7a8c6d08f1507e1e0f4b 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg
@@ -7,4 +7,11 @@ telnet_port 4444
gdb_port 3333
source [find interface/olimex-arm-usb-ocd.cfg]
-source [find board/stm3220g_eval.cfg]
+
+# increase working area to 128KB
+set WORKAREASIZE 0x20000
+
+# chip name
+set CHIPNAME STM32F207ZG
+
+source [find target/stm32f2x.cfg]
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
index 8e5b0fb93c87f050464bd932e8c7b74f6a4eaa76..644f36fabbb41c389a3c88ee5dbb04be3796bcd2 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
@@ -58,17 +58,111 @@ void IRQbspInit()
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
- RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |
- RCC_AHB1ENR_GPIOIEN;
+ RCC_AHB1ENR_GPIOGEN;
+ //Pins used for FSMC (SRAM):
+ //PD 0,1,4,5,7,8,9,10,11,12,14,15
+ //PE 0,1,7,8,9,10,11,12,13,14,15
+ //PF 0,1,2,3,4,5,12,13,14,15
+ //PG 0,1,2,3,4,5
GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS
- GPIOB->OSPEEDR=0xaaaaaaaa;
+ GPIOB->OSPEEDR=0xaaaaaaaa; //Except SRAM GPIOs that run @ 100MHz
GPIOC->OSPEEDR=0xaaaaaaaa;
- GPIOD->OSPEEDR=0xf3ff0f0f | 0xaaaaaaaa; //GPIOD,E,F,G are used by the FSMC
- GPIOE->OSPEEDR=0xffffc00f | 0xaaaaaaaa; //configure those pins as 100MHz
- GPIOF->OSPEEDR=0xff000fff | 0xaaaaaaaa; //(constants taken from
- GPIOG->OSPEEDR=0x000c0fff | 0xaaaaaaaa; // SystemInit_ExtMemCtl)
- GPIOH->OSPEEDR=0xaaaaaaaa;
- GPIOI->OSPEEDR=0xaaaaaaaa;
+ GPIOD->OSPEEDR=0xfbffefaf;
+ GPIOE->OSPEEDR=0xffffeaaf;
+ GPIOF->OSPEEDR=0xffaaafff;
+ GPIOG->OSPEEDR=0xaaaaafff;
+
+ //Port config (H=high, L=low, PU=pullup, PD=pulldown)
+ // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG |
+ //--+---------+---------+---------+---------+---------+---------+---------+
+ // 0| AF11 | AF11 | IN | AF12 | | | |
+ // 1| AF11 | AF11 | AF11 | AF12 | | | |
+ // 2| AF11 | IN PD | AF11 | AF12 | | | |
+ // 3| AF11 | AF0 | AF11 | IN PD | | | |
+ // 4| OUT H | AF0 | AF11 | AF12 | | | |
+ // 5| AF5 | AF5 | AF11 | AF12 | | | |
+ // 6| AF5 | IN PD | OUT L | IN PD | | | |
+ // 7| AF11 | IN PD | IN PD | AF12 | | | |
+ // 8| AF0 | AF11 | AF12 | AF12 | | | |
+ // 9| AF7 | IN PD | AF12 | AF12 | | | |
+ //10| AF7 | AF11 | AF12 | AF12 | | | |
+ //11| AF10 | AF11 | AF12 | AF12 | | | |
+ //12| AF10 | AF11 | AF12 | AF12 | | | |
+ //13| AF0 | AF11 | IN PU | IN PD | | | |
+ //14| AF0 | AF12 | IN PD | AF12 | | | |
+ //15| AF0 | AF12 | IN PD | AF12 | | | |
+ //TODO: PC0==mii_irq, requires sw pullup?
+ //PC13==sdio_cd, requires sw pu?
+ GPIOA->PUPDR=0xaaaaaaaa;
+ GPIOB->PUPDR=0xaaaaaaaa;
+ GPIOC->PUPDR=0xaaaaaaaa;
+ GPIOD->PUPDR=0xaaaaaaaa;
+ GPIOE->PUPDR=0xaaaaaaaa;
+ GPIOF->PUPDR=0xaaaaaaaa;
+ GPIOG->PUPDR=0xaaaaaaaa;
+
+ //FIXME -- begin
+ /* Connect PDx pins to FSMC Alternate function */
+ GPIOD->AFR[0] = 0x00cc00cc;
+ GPIOD->AFR[1] = 0xcc0ccccc;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xa2aa0a0a;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xf3ff0f0f;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FSMC Alternate function */
+ GPIOE->AFR[0] = 0xc00000cc;
+ GPIOE->AFR[1] = 0xcccccccc;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xaaaa800a;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xffffc00f;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FSMC Alternate function */
+ GPIOF->AFR[0] = 0x00cccccc;
+ GPIOF->AFR[1] = 0xcccc0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xaa000aaa;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xff000fff;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FSMC Alternate function */
+ GPIOG->AFR[0] = 0x00cccccc;
+ GPIOG->AFR[1] = 0x000000c0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00080aaa;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000c0fff;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FSMC Configuration ------------------------------------------------------*/
+ /* Enable the FSMC interface clock */
+ RCC->AHB3ENR = 0x00000001;
+
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001015;
+ FSMC_Bank1->BTCR[3] = 0x00010400;
+ FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+ //FIXME -- end
+
+ sram::cs1::mode(Mode::OUTPUT);
+ sram::cs1::high();
+
led::mode(Mode::OUTPUT);
sdCardDetect::mode(Mode::INPUT_PULL_UP);
ledOn();
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h
index 3f2564b6afccc16e3713e495c2d629f5d2bc32bb..460c1d8e2749c7c299dd36715884fc5de4ce51d0 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h
@@ -34,7 +34,7 @@
#define BSP_IMPL_H
#include "config/miosix_settings.h"
-#include "interfaces/gpio.h"
+#include "hwmapping.h"
namespace miosix {
@@ -47,7 +47,6 @@ namespace miosix {
* \internal
* used by the ledOn() and ledOff() implementation
*/
-typedef Gpio<GPIOI_BASE,9> led;
inline void ledOn()
{
@@ -60,7 +59,7 @@ inline void ledOff()
}
///\internal Pin connected to SD card detect
-typedef Gpio<GPIOH_BASE,13> sdCardDetect;
+typedef sdio::cd sdCardDetect;
/**
* Polls the SD card sense GPIO
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp
index a0742d1671d5af5cb0d7dbec264863fca5c5d2da..04ef0d7fd31400bd533d99bdd999d6ad120a297a 100644
--- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp
@@ -35,6 +35,7 @@
#include "interfaces/gpio.h"
#include "board_settings.h"
#include "drivers/dcc.h"
+#include "hwmapping.h"
#include <cstring>
#ifndef STDOUT_REDIRECTED_TO_DCC
@@ -101,8 +102,8 @@ void IRQstm32f2serialPortInit()
USART1->CR3 = 0;//Disable irda and smartcard mode
#ifdef SYSCLK_FREQ_120MHz
- //USART1 is connected to APB1 @ 30MHz
- const unsigned int brr = (97<<4) | (10<<0); //BRR=97.625 0.032% Error
+ //USART1 is connected to APB2 @ 60MHz
+ const unsigned int brr = (195<<4) | (5<<0); //BRR=195.3125 0% Error
#else
#warning "No serial baudrate for this clock frequency"
#endif
@@ -110,10 +111,10 @@ void IRQstm32f2serialPortInit()
USART1->BRR=brr;
//Now that serial port is active, configure I/Os
- Gpio<GPIOA_BASE,9>::alternateFunction(7);
- Gpio<GPIOA_BASE,9>::mode(Mode::ALTERNATE); //PA.9 = USART1 tx
- Gpio<GPIOA_BASE,10>::alternateFunction(7);
- Gpio<GPIOA_BASE,10>::mode(Mode::ALTERNATE); //PA.10 = USART1 rx
+ serial::tx::alternateFunction(7);
+ serial::tx::mode(Mode::ALTERNATE);
+ serial::rx::alternateFunction(7);
+ serial::rx::mode(Mode::ALTERNATE);
USART1->CR1 |= USART_CR1_TE | USART_CR1_RE;//Finally enable tx and rx
NVIC_SetPriority(USART1_IRQn,10);//Low priority for serial. (Max=0, min=15)
NVIC_EnableIRQ(USART1_IRQn);
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h
new file mode 100644
index 0000000000000000000000000000000000000000..c33dcf406902db6129d54846af204611e403584e
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h
@@ -0,0 +1,190 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef HWMAPPING_H
+#define HWMAPPING_H
+
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+typedef Gpio<GPIOE_BASE,2> led;
+
+//Spare GPIOs, brought out to a connector
+namespace gpio {
+typedef Gpio<GPIOE_BASE,3> g0;
+typedef Gpio<GPIOE_BASE,4> g1;
+typedef Gpio<GPIOE_BASE,5> g2;
+typedef Gpio<GPIOE_BASE,6> g3;
+}
+
+//Gpios that connect the ethernet transceiver to the microcontroller
+namespace mii {
+typedef Gpio<GPIOC_BASE,1> mdc;
+typedef Gpio<GPIOA_BASE,2> mdio;
+typedef Gpio<GPIOA_BASE,8> clk;
+typedef Gpio<GPIOC_BASE,6> res;
+typedef Gpio<GPIOC_BASE,0> irq;
+typedef Gpio<GPIOA_BASE,3> col;
+typedef Gpio<GPIOA_BASE,0> crs;
+typedef Gpio<GPIOA_BASE,1> rxc;
+typedef Gpio<GPIOA_BASE,7> rxdv;
+typedef Gpio<GPIOB_BASE,10> rxer;
+typedef Gpio<GPIOC_BASE,4> rxd0;
+typedef Gpio<GPIOC_BASE,5> rxd1;
+typedef Gpio<GPIOB_BASE,0> rxd2;
+typedef Gpio<GPIOB_BASE,1> rxd3;
+typedef Gpio<GPIOB_BASE,11> txen;
+typedef Gpio<GPIOC_BASE,3> txc;
+typedef Gpio<GPIOB_BASE,12> txd0;
+typedef Gpio<GPIOB_BASE,13> txd1;
+typedef Gpio<GPIOC_BASE,2> txd2;
+typedef Gpio<GPIOB_BASE,8> txd3;
+}
+
+//External SRAM, connected to FSMC
+namespace sram {
+typedef Gpio<GPIOD_BASE,7> cs1;
+typedef Gpio<GPIOD_BASE,4> oe;
+typedef Gpio<GPIOD_BASE,5> we;
+typedef Gpio<GPIOE_BASE,0> lb;
+typedef Gpio<GPIOE_BASE,1> ub;
+typedef Gpio<GPIOD_BASE,14> d0;
+typedef Gpio<GPIOD_BASE,15> d1;
+typedef Gpio<GPIOD_BASE,0> d2;
+typedef Gpio<GPIOD_BASE,1> d3;
+typedef Gpio<GPIOE_BASE,7> d4;
+typedef Gpio<GPIOE_BASE,8> d5;
+typedef Gpio<GPIOE_BASE,9> d6;
+typedef Gpio<GPIOE_BASE,10> d7;
+typedef Gpio<GPIOE_BASE,11> d8;
+typedef Gpio<GPIOE_BASE,12> d9;
+typedef Gpio<GPIOE_BASE,13> d10;
+typedef Gpio<GPIOE_BASE,14> d11;
+typedef Gpio<GPIOE_BASE,15> d12;
+typedef Gpio<GPIOD_BASE,8> d13;
+typedef Gpio<GPIOD_BASE,9> d14;
+typedef Gpio<GPIOD_BASE,10> d15;
+typedef Gpio<GPIOF_BASE,0> a0;
+typedef Gpio<GPIOF_BASE,1> a1;
+typedef Gpio<GPIOF_BASE,2> a2;
+typedef Gpio<GPIOF_BASE,3> a3;
+typedef Gpio<GPIOF_BASE,4> a4;
+typedef Gpio<GPIOF_BASE,5> a5;
+typedef Gpio<GPIOF_BASE,12> a6;
+typedef Gpio<GPIOF_BASE,13> a7;
+typedef Gpio<GPIOF_BASE,14> a8;
+typedef Gpio<GPIOF_BASE,15> a9;
+typedef Gpio<GPIOG_BASE,0> a10;
+typedef Gpio<GPIOG_BASE,1> a11;
+typedef Gpio<GPIOG_BASE,2> a12;
+typedef Gpio<GPIOG_BASE,3> a13;
+typedef Gpio<GPIOG_BASE,4> a14;
+typedef Gpio<GPIOG_BASE,5> a15;
+typedef Gpio<GPIOD_BASE,11> a16;
+typedef Gpio<GPIOD_BASE,12> a17;
+}
+
+//Connections to the optional nRF24L01 radio module
+namespace nrf {
+typedef Gpio<GPIOA_BASE,4> cs;
+typedef Gpio<GPIOA_BASE,5> sck;
+typedef Gpio<GPIOA_BASE,6> miso;
+typedef Gpio<GPIOB_BASE,5> mosi;
+typedef Gpio<GPIOF_BASE,6> ce;
+typedef Gpio<GPIOF_BASE,7> irq;
+}
+
+//Serial port
+namespace serial {
+typedef Gpio<GPIOA_BASE,9> tx;
+typedef Gpio<GPIOA_BASE,10> rx;
+}
+
+//USB host port
+namespace usbhost {
+typedef Gpio<GPIOA_BASE,11> dm;
+typedef Gpio<GPIOA_BASE,12> dp;
+}
+
+//USB device port
+namespace usbdevice {
+typedef Gpio<GPIOB_BASE,14> dm;
+typedef Gpio<GPIOB_BASE,15> dp;
+}
+
+//MicroSD card slot
+namespace sdio {
+typedef Gpio<GPIOC_BASE,8> d0;
+typedef Gpio<GPIOC_BASE,9> d1;
+typedef Gpio<GPIOC_BASE,10> d2;
+typedef Gpio<GPIOC_BASE,11> d3;
+typedef Gpio<GPIOC_BASE,12> ck;
+typedef Gpio<GPIOC_BASE,13> cd;
+typedef Gpio<GPIOD_BASE,2> cmd;
+}
+
+//JTAG port
+namespace jtag {
+typedef Gpio<GPIOA_BASE,15> tdi;
+typedef Gpio<GPIOB_BASE,3> tdo;
+typedef Gpio<GPIOA_BASE,13> tms;
+typedef Gpio<GPIOA_BASE,14> tck;
+typedef Gpio<GPIOB_BASE,4> trst;
+}
+
+//Unused pins, configured as pulldown
+namespace unused {
+typedef Gpio<GPIOB_BASE,2> u1; //Connected to ground, as it is boot1
+typedef Gpio<GPIOB_BASE,6> u2;
+typedef Gpio<GPIOB_BASE,7> u3;
+typedef Gpio<GPIOB_BASE,9> u4;
+typedef Gpio<GPIOC_BASE,7> u5;
+typedef Gpio<GPIOC_BASE,14> u6;
+typedef Gpio<GPIOC_BASE,15> u7;
+typedef Gpio<GPIOD_BASE,3> u8;
+typedef Gpio<GPIOD_BASE,6> u9;
+typedef Gpio<GPIOD_BASE,13> u10;
+typedef Gpio<GPIOF_BASE,8> u11;
+typedef Gpio<GPIOF_BASE,9> u12;
+typedef Gpio<GPIOF_BASE,10> u13;
+typedef Gpio<GPIOF_BASE,11> u14;
+typedef Gpio<GPIOG_BASE,6> u15;
+typedef Gpio<GPIOG_BASE,7> u16;
+typedef Gpio<GPIOG_BASE,8> u17;
+typedef Gpio<GPIOG_BASE,9> u18;
+typedef Gpio<GPIOG_BASE,10> u19;
+typedef Gpio<GPIOG_BASE,11> u20;
+typedef Gpio<GPIOG_BASE,12> u21;
+typedef Gpio<GPIOG_BASE,13> u22;
+typedef Gpio<GPIOG_BASE,14> u23;
+typedef Gpio<GPIOG_BASE,15> u24;
+}
+
+} //namespace miosix
+
+#endif //HWMAPPING_H