Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
Miosix Kernel
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
Avionics
Software Development
Miosix Kernel
Commits
cac84b49
Commit
cac84b49
authored
6 months ago
by
Federico
Browse files
Options
Downloads
Patches
Plain Diff
Better document how the MPU is used
parent
f8775dce
Branches
Branches containing commit
No related tags found
No related merge requests found
Changes
2
Show whitespace changes
Inline
Side-by-side
Showing
2 changed files
miosix/arch/common/cache/cortexMx_cache.cpp
+5
-0
5 additions, 0 deletions
miosix/arch/common/cache/cortexMx_cache.cpp
miosix/arch/cpu/armv7m/interfaces-impl/userspace.cpp
+10
-5
10 additions, 5 deletions
miosix/arch/cpu/armv7m/interfaces-impl/userspace.cpp
with
15 additions
and
5 deletions
miosix/arch/common/cache/cortexMx_cache.cpp
+
5
−
0
View file @
cac84b49
...
...
@@ -64,6 +64,11 @@ static void IRQconfigureCacheability(unsigned int region, unsigned int base,
void
IRQconfigureCache
(
const
unsigned
int
*
xramBase
,
unsigned
int
xramSize
)
{
// NOTE: using regions 0 to 3 for the kernel because in the ARM MPU in case
// of overlapping regions the one with the highest number takes priority.
// The lower regions are used by the kernel and by default forbid access to
// unprivileged code, while the higher numbered ones are used by processes
// to override the default deny policy for the process-specific memory.
IRQconfigureCacheability
(
0
,
0x00000000
,
0x20000000
);
IRQconfigureCacheability
(
1
,
0x20000000
,
0x20000000
);
if
(
xramSize
)
...
...
This diff is collapsed.
Click to expand it.
miosix/arch/cpu/armv7m/interfaces-impl/userspace.cpp
+
10
−
5
View file @
cac84b49
...
...
@@ -124,6 +124,11 @@ MPUConfiguration::MPUConfiguration(const unsigned int *elfBase, unsigned int elf
const
unsigned
int
*
imageBase
,
unsigned
int
imageSize
)
{
#if __MPU_PRESENT==1
// NOTE: using regions 6 and 7 for processes because in the ARM MPU in case
// of overlapping regions the one with the highest number takes priority.
// The lower regions are used by the kernel and by default forbid access to
// unprivileged code, thus we need higher numbered ones for processes to
// override the default deny policy for the process-specific memory.
// NOTE: The ARM documentation is unclear about the effect of the shareable
// bit on a single core architecture. Experimental evidence on an STM32F476
// shows that setting it in IRQconfigureCache for the internal RAM region
...
...
@@ -131,15 +136,15 @@ MPUConfiguration::MPUConfiguration(const unsigned int *elfBase, unsigned int elf
// For this reason, all regions are marked as not shareable
regValues
[
0
]
=
(
reinterpret_cast
<
unsigned
int
>
(
elfBase
)
&
(
~
0x1f
))
|
MPU_RBAR_VALID_Msk
|
6
;
//Region 6
regValues
[
2
]
=
(
reinterpret_cast
<
unsigned
int
>
(
imageBase
)
&
(
~
0x1f
))
|
MPU_RBAR_VALID_Msk
|
7
;
//Region 7
regValues
[
1
]
=
2
<<
MPU_RASR_AP_Pos
//Privileged: RW, unprivileged: RO
|
MPU_RASR_C_Msk
|
MPU_RASR_C_Msk
//Cacheable, write through
|
1
//Enable bit
|
sizeToMpu
(
elfSize
)
<<
1
;
regValues
[
2
]
=
(
reinterpret_cast
<
unsigned
int
>
(
imageBase
)
&
(
~
0x1f
))
|
MPU_RBAR_VALID_Msk
|
7
;
//Region 7
regValues
[
3
]
=
3
<<
MPU_RASR_AP_Pos
//Privileged: RW, unprivileged: RW
|
MPU_RASR_XN_Msk
|
MPU_RASR_C_Msk
|
MPU_RASR_XN_Msk
//Not executable
|
MPU_RASR_C_Msk
//Cacheable, write through
|
1
//Enable bit
|
sizeToMpu
(
imageSize
)
<<
1
;
#else //__MPU_PRESENT==1
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment