diff --git a/main.cpp b/main.cpp
index 8764b9fabb7ead786e8a9eae3d8bd03873dc6ec4..c5ca354d45df53eea342005dfd3b3084b53aee2e 100644
--- a/main.cpp
+++ b/main.cpp
@@ -8,4 +8,6 @@ using namespace miosix;
int main()
{
//iprintf("Hello world, write your application here\n");
+
+ //RAM is @ 0x60000000, test it!
}
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..d9fc56da30c0390fcbdde5a4791252ae662f783f
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg
@@ -0,0 +1,10 @@
+#
+# OpenOCD configuration file for in-circuit debugging of stm32
+#
+
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+source [find interface/olimex-arm-usb-ocd.cfg]
+source [find board/stm3220g_eval.cfg]
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h
new file mode 100644
index 0000000000000000000000000000000000000000..75bde00f486e9747f5cbf700bfbdc185debb0671
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h
@@ -0,0 +1,69 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef BOARD_SETTINGS_H
+#define BOARD_SETTINGS_H
+
+namespace miosix {
+
+/**
+ * \addtogroup Settings
+ * \{
+ */
+
+/// Size of stack for main().
+/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the
+/// STM32F207IG has 128KB of RAM so there is room for a big 4K stack.
+const unsigned int MAIN_STACK_SIZE=4*1024;
+
+/// Frequency of tick (in Hz). The frequency of the STM32F207ZG timer in the
+/// Miosix board can be divided by 1000. This allows to use a 1KHz tick and
+/// the minimun Thread::sleep value is 1ms
+/// For the priority scheduler this is also the context switch frequency
+const unsigned int TICK_FREQ=1000;
+
+///\internal Aux timer run @ 100KHz
+///Note that since the timer is only 16 bits this imposes a limit on the
+///burst measurement of 655ms. If due to a pause_kernel() or
+///disable_interrupts() section a thread runs for more than that time, a wrong
+///burst value will be measured
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
+
+///\def STDOUT_REDIRECTED_TO_DCC
+///If defined, stdout is redirected to the debug communication channel, and
+///will be printed if OpenOCD is connected. If not defined, stdout will be
+///redirected throug USART1, as usual.
+//#define STDOUT_REDIRECTED_TO_DCC
+
+/**
+ * \}
+ */
+
+} //namespace miosix
+
+#endif /* BOARD_SETTINGS_H */
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..d9fe83b258f981beaf6f3f7c7e786d48242a919e
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp
@@ -0,0 +1,443 @@
+
+#include "interfaces/arch_registers.h"
+#include "core/interrupts.h" //For the unexpected interrupt call
+#include <string.h>
+
+/*
+ * startup.cpp
+ * STM32 C++ startup.
+ * NOTE: for stm32f2 devices ONLY.
+ * - supports interrupt handlers in C++ without extern "C"
+ * - global constructors are correctly called before main()
+ * Developed by Terraneo Federico, based on ST startup code.
+ * Additionally modified to boot Miosix.
+ */
+
+//Will be called at the end of stage 1 of boot, function is implemented in
+//stage_2_boot.cpp
+extern "C" void _init();
+
+/**
+ * Calls C++ global constructors
+ * \param start first function pointer to call
+ * \param end one past the last function pointer to call
+ * Declared "noinline" to optimize code size
+ */
+static void call_constructors(unsigned long *start, unsigned long *end) __attribute__((noinline));
+static void call_constructors(unsigned long *start, unsigned long *end)
+{
+ for(unsigned long *i=start; i<end; i++)
+ {
+ void (*funcptr)();
+ funcptr=reinterpret_cast<void (*)()>(*i);
+ funcptr();
+ }
+}
+
+/**
+ * Called by Reset_Handler, performs initialization and calls main.
+ * Never returns.
+ */
+void program_startup() __attribute__((noreturn));
+void program_startup()
+{
+ //Cortex M3 core appears to get out of reset with interrupts already enabled
+ __disable_irq();
+
+ //These are defined in the linker script
+ extern unsigned char _etext asm("_etext");
+ extern unsigned char _data asm("_data");
+ extern unsigned char _edata asm("_edata");
+ extern unsigned char _bss_start asm("_bss_start");
+ extern unsigned char _bss_end asm("_bss_end");
+ extern unsigned long __preinit_array_start asm("__preinit_array_start");
+ extern unsigned long __preinit_array_end asm("__preinit_array_end");
+ extern unsigned long __init_array_start asm("__init_array_start");
+ extern unsigned long __init_array_end asm("__init_array_end");
+ extern unsigned long _ctor_start asm("_ctor_start");
+ extern unsigned long _ctor_end asm("_ctor_end");
+
+ //Initialize .data section, clear .bss section
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ #ifndef __CODE_IN_XRAM
+ memcpy(data, etext, edata-data);
+ #else //__CODE_IN_XRAM
+ (void)etext; //Avoid unused variable warning
+ (void)data;
+ (void)edata;
+ #endif //__CODE_IN_XRAM
+ memset(bss_start, 0, bss_end-bss_start);
+
+ //Initialize C++ global constructors
+ call_constructors(&__preinit_array_start, &__preinit_array_end);
+ call_constructors(&__init_array_start, &__init_array_end);
+ call_constructors(&_ctor_start, &_ctor_end);
+
+ //Move on to stage 2
+ _init();
+
+ //If main returns, reboot
+ NVIC_SystemReset();
+ for(;;) ;
+}
+
+/**
+ * Reset handler, called by hardware immediately after reset
+ */
+void Reset_Handler() __attribute__((__interrupt__, noreturn));
+void Reset_Handler()
+{
+ #ifdef __CODE_IN_XRAM
+ /**
+ * Before calling the initalization code, set the stack pointer to the
+ * required value. At first it might seem redundant setting the stack
+ * pointer since the hardware should take care of this, but there is a
+ * corner case in which it is not set properly:
+ * 1) A debugger like openocd is used to run the code
+ * 2) Debugged code is run from external RAM
+ * In this case, in FLASH starting from 0x00000000 there is a bootloader
+ * that forwards interrupt vectors to their address in external RAM
+ * at address 0x60000000. The bootloader can also be used to load the code
+ * but this is uninteresting here. The problem is that the bootloader uses
+ * the internal RAM for its stack, so @ 0x00000000 there is the value
+ * 0x20000000 (top of internal RAM). When a debugger like openocd loads the
+ * debuged code in external RAM starting from 0x60000000 it mimics the
+ * harware behaviour of setting the stack pointer. But it loads the value at
+ * 0x00000000, not the value at 0x60000000. Therefore the stack pointer
+ * is set to the stak used by the bootloader (top of INTERNAL RAM) instead
+ * of the stack of the debugged code (top of EXTERNAL RAM).
+ * Since this quirk happens only when running code from external RAM, the
+ * fix is enclosed in an #ifdef __CODE_IN_XRAM
+ */
+ asm volatile("ldr sp, =_main_stack_top\n\t");
+ #endif //__CODE_IN_XRAM
+
+ /*
+ * SystemInit() is called *before* initializing .data and zeroing .bss
+ * Despite all startup files provided by ST do the opposite, there are three
+ * good reasons to do so:
+ * First, the CMSIS specifications say that SystemInit() must not access
+ * global variables, so it is actually possible to call it before
+ * Second, when running Miosix with the xram linker scripts .data and .bss
+ * are placed in the external RAM, so we *must* call SystemInit(), which
+ * enables xram, before touching .data and .bss
+ * Third, this is a performance improvement since the loops that initialize
+ * .data and zeros .bss now run with the CPU at full speed instead of 16MHz
+ * Note that it is called before switching stacks because the memory
+ * at _heap_end can be unavailable until the external RAM is initialized.
+ */
+ SystemInit();
+
+ /*
+ * Initialize process stack and switch to it.
+ * This is required for booting Miosix, a small portion of the top of the
+ * heap area will be used as stack until the first thread starts. After,
+ * this stack will be abandoned and the process stack will point to the
+ * current thread's stack.
+ */
+ asm volatile("ldr r0, =_heap_end \n\t"
+ "msr psp, r0 \n\t"
+ "movw r0, #2 \n\n" //Privileged, process stack
+ "msr control, r0 \n\t"
+ "isb \n\t":::"r0");
+
+ program_startup();
+}
+
+/**
+ * All unused interrupts call this function.
+ */
+extern "C" void Default_Handler()
+{
+ unexpectedInterrupt();
+}
+
+//System handlers
+void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
+void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
+void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
+void /*__attribute__((weak))*/ MemManage_Handler();
+void /*__attribute__((weak))*/ BusFault_Handler();
+void /*__attribute__((weak))*/ UsageFault_Handler();
+void /*__attribute__((weak))*/ SVC_Handler();
+void /*__attribute__((weak))*/ DebugMon_Handler();
+void /*__attribute__((weak))*/ PendSV_Handler();
+void /*__attribute__((weak))*/ SysTick_Handler();
+
+//Interrupt handlers
+void __attribute__((weak)) WWDG_IRQHandler();
+void __attribute__((weak)) PVD_IRQHandler();
+void __attribute__((weak)) TAMP_STAMP_IRQHandler();
+void __attribute__((weak)) RTC_WKUP_IRQHandler();
+void __attribute__((weak)) FLASH_IRQHandler();
+void __attribute__((weak)) RCC_IRQHandler();
+void __attribute__((weak)) EXTI0_IRQHandler();
+void __attribute__((weak)) EXTI1_IRQHandler();
+void __attribute__((weak)) EXTI2_IRQHandler();
+void __attribute__((weak)) EXTI3_IRQHandler();
+void __attribute__((weak)) EXTI4_IRQHandler();
+void __attribute__((weak)) DMA1_Stream0_IRQHandler();
+void __attribute__((weak)) DMA1_Stream1_IRQHandler();
+void __attribute__((weak)) DMA1_Stream2_IRQHandler();
+void __attribute__((weak)) DMA1_Stream3_IRQHandler();
+void __attribute__((weak)) DMA1_Stream4_IRQHandler();
+void __attribute__((weak)) DMA1_Stream5_IRQHandler();
+void __attribute__((weak)) DMA1_Stream6_IRQHandler();
+void __attribute__((weak)) ADC_IRQHandler();
+void __attribute__((weak)) CAN1_TX_IRQHandler();
+void __attribute__((weak)) CAN1_RX0_IRQHandler();
+void __attribute__((weak)) CAN1_RX1_IRQHandler();
+void __attribute__((weak)) CAN1_SCE_IRQHandler();
+void __attribute__((weak)) EXTI9_5_IRQHandler();
+void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler();
+void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler();
+void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler();
+void __attribute__((weak)) TIM1_CC_IRQHandler();
+void __attribute__((weak)) TIM2_IRQHandler();
+void __attribute__((weak)) TIM3_IRQHandler();
+void __attribute__((weak)) TIM4_IRQHandler();
+void __attribute__((weak)) I2C1_EV_IRQHandler();
+void __attribute__((weak)) I2C1_ER_IRQHandler();
+void __attribute__((weak)) I2C2_EV_IRQHandler();
+void __attribute__((weak)) I2C2_ER_IRQHandler();
+void __attribute__((weak)) SPI1_IRQHandler();
+void __attribute__((weak)) SPI2_IRQHandler();
+void __attribute__((weak)) USART1_IRQHandler();
+void __attribute__((weak)) USART2_IRQHandler();
+void __attribute__((weak)) USART3_IRQHandler();
+void __attribute__((weak)) EXTI15_10_IRQHandler();
+void __attribute__((weak)) RTC_Alarm_IRQHandler();
+void __attribute__((weak)) OTG_FS_WKUP_IRQHandler();
+void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler();
+void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler();
+void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler();
+void __attribute__((weak)) TIM8_CC_IRQHandler();
+void __attribute__((weak)) DMA1_Stream7_IRQHandler();
+void __attribute__((weak)) FSMC_IRQHandler();
+void __attribute__((weak)) SDIO_IRQHandler();
+void __attribute__((weak)) TIM5_IRQHandler();
+void __attribute__((weak)) SPI3_IRQHandler();
+void __attribute__((weak)) UART4_IRQHandler();
+void __attribute__((weak)) UART5_IRQHandler();
+void __attribute__((weak)) TIM6_DAC_IRQHandler();
+void __attribute__((weak)) TIM7_IRQHandler();
+void __attribute__((weak)) DMA2_Stream0_IRQHandler();
+void __attribute__((weak)) DMA2_Stream1_IRQHandler();
+void __attribute__((weak)) DMA2_Stream2_IRQHandler();
+void __attribute__((weak)) DMA2_Stream3_IRQHandler();
+void __attribute__((weak)) DMA2_Stream4_IRQHandler();
+void __attribute__((weak)) ETH_IRQHandler();
+void __attribute__((weak)) ETH_WKUP_IRQHandler();
+void __attribute__((weak)) CAN2_TX_IRQHandler();
+void __attribute__((weak)) CAN2_RX0_IRQHandler();
+void __attribute__((weak)) CAN2_RX1_IRQHandler();
+void __attribute__((weak)) CAN2_SCE_IRQHandler();
+void __attribute__((weak)) OTG_FS_IRQHandler();
+void __attribute__((weak)) DMA2_Stream5_IRQHandler();
+void __attribute__((weak)) DMA2_Stream6_IRQHandler();
+void __attribute__((weak)) DMA2_Stream7_IRQHandler();
+void __attribute__((weak)) USART6_IRQHandler();
+void __attribute__((weak)) I2C3_EV_IRQHandler();
+void __attribute__((weak)) I2C3_ER_IRQHandler();
+void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler();
+void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler();
+void __attribute__((weak)) OTG_HS_WKUP_IRQHandler();
+void __attribute__((weak)) OTG_HS_IRQHandler();
+void __attribute__((weak)) DCMI_IRQHandler();
+void __attribute__((weak)) CRYP_IRQHandler();
+void __attribute__((weak)) HASH_RNG_IRQHandler();
+
+//Stack top, defined in the linker script
+extern char _main_stack_top asm("_main_stack_top");
+
+//Interrupt vectors, must be placed @ address 0x00000000
+//The extern declaration is required otherwise g++ optimizes it out
+extern void (* const __Vectors[])();
+void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
+{
+ reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External Interrupts */
+ WWDG_IRQHandler,
+ PVD_IRQHandler,
+ TAMP_STAMP_IRQHandler,
+ RTC_WKUP_IRQHandler,
+ FLASH_IRQHandler,
+ RCC_IRQHandler,
+ EXTI0_IRQHandler,
+ EXTI1_IRQHandler,
+ EXTI2_IRQHandler,
+ EXTI3_IRQHandler,
+ EXTI4_IRQHandler,
+ DMA1_Stream0_IRQHandler,
+ DMA1_Stream1_IRQHandler,
+ DMA1_Stream2_IRQHandler,
+ DMA1_Stream3_IRQHandler,
+ DMA1_Stream4_IRQHandler,
+ DMA1_Stream5_IRQHandler,
+ DMA1_Stream6_IRQHandler,
+ ADC_IRQHandler,
+ CAN1_TX_IRQHandler,
+ CAN1_RX0_IRQHandler,
+ CAN1_RX1_IRQHandler,
+ CAN1_SCE_IRQHandler,
+ EXTI9_5_IRQHandler,
+ TIM1_BRK_TIM9_IRQHandler,
+ TIM1_UP_TIM10_IRQHandler,
+ TIM1_TRG_COM_TIM11_IRQHandler,
+ TIM1_CC_IRQHandler,
+ TIM2_IRQHandler,
+ TIM3_IRQHandler,
+ TIM4_IRQHandler,
+ I2C1_EV_IRQHandler,
+ I2C1_ER_IRQHandler,
+ I2C2_EV_IRQHandler,
+ I2C2_ER_IRQHandler,
+ SPI1_IRQHandler,
+ SPI2_IRQHandler,
+ USART1_IRQHandler,
+ USART2_IRQHandler,
+ USART3_IRQHandler,
+ EXTI15_10_IRQHandler,
+ RTC_Alarm_IRQHandler,
+ OTG_FS_WKUP_IRQHandler,
+ TIM8_BRK_TIM12_IRQHandler,
+ TIM8_UP_TIM13_IRQHandler,
+ TIM8_TRG_COM_TIM14_IRQHandler,
+ TIM8_CC_IRQHandler,
+ DMA1_Stream7_IRQHandler,
+ FSMC_IRQHandler,
+ SDIO_IRQHandler,
+ TIM5_IRQHandler,
+ SPI3_IRQHandler,
+ UART4_IRQHandler,
+ UART5_IRQHandler,
+ TIM6_DAC_IRQHandler,
+ TIM7_IRQHandler,
+ DMA2_Stream0_IRQHandler,
+ DMA2_Stream1_IRQHandler,
+ DMA2_Stream2_IRQHandler,
+ DMA2_Stream3_IRQHandler,
+ DMA2_Stream4_IRQHandler,
+ ETH_IRQHandler,
+ ETH_WKUP_IRQHandler,
+ CAN2_TX_IRQHandler,
+ CAN2_RX0_IRQHandler,
+ CAN2_RX1_IRQHandler,
+ CAN2_SCE_IRQHandler,
+ OTG_FS_IRQHandler,
+ DMA2_Stream5_IRQHandler,
+ DMA2_Stream6_IRQHandler,
+ DMA2_Stream7_IRQHandler,
+ USART6_IRQHandler,
+ I2C3_EV_IRQHandler,
+ I2C3_ER_IRQHandler,
+ OTG_HS_EP1_OUT_IRQHandler,
+ OTG_HS_EP1_IN_IRQHandler,
+ OTG_HS_WKUP_IRQHandler,
+ OTG_HS_IRQHandler,
+ DCMI_IRQHandler,
+ CRYP_IRQHandler,
+ HASH_RNG_IRQHandler,
+};
+
+#pragma weak WWDG_IRQHandler = Default_Handler
+#pragma weak PVD_IRQHandler = Default_Handler
+#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
+#pragma weak RTC_WKUP_IRQHandler = Default_Handler
+#pragma weak FLASH_IRQHandler = Default_Handler
+#pragma weak RCC_IRQHandler = Default_Handler
+#pragma weak EXTI0_IRQHandler = Default_Handler
+#pragma weak EXTI1_IRQHandler = Default_Handler
+#pragma weak EXTI2_IRQHandler = Default_Handler
+#pragma weak EXTI3_IRQHandler = Default_Handler
+#pragma weak EXTI4_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
+#pragma weak ADC_IRQHandler = Default_Handler
+#pragma weak CAN1_TX_IRQHandler = Default_Handler
+#pragma weak CAN1_RX0_IRQHandler = Default_Handler
+#pragma weak CAN1_RX1_IRQHandler = Default_Handler
+#pragma weak CAN1_SCE_IRQHandler = Default_Handler
+#pragma weak EXTI9_5_IRQHandler = Default_Handler
+#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
+#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
+#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
+#pragma weak TIM1_CC_IRQHandler = Default_Handler
+#pragma weak TIM2_IRQHandler = Default_Handler
+#pragma weak TIM3_IRQHandler = Default_Handler
+#pragma weak TIM4_IRQHandler = Default_Handler
+#pragma weak I2C1_EV_IRQHandler = Default_Handler
+#pragma weak I2C1_ER_IRQHandler = Default_Handler
+#pragma weak I2C2_EV_IRQHandler = Default_Handler
+#pragma weak I2C2_ER_IRQHandler = Default_Handler
+#pragma weak SPI1_IRQHandler = Default_Handler
+#pragma weak SPI2_IRQHandler = Default_Handler
+#pragma weak USART1_IRQHandler = Default_Handler
+#pragma weak USART2_IRQHandler = Default_Handler
+#pragma weak USART3_IRQHandler = Default_Handler
+#pragma weak EXTI15_10_IRQHandler = Default_Handler
+#pragma weak RTC_Alarm_IRQHandler = Default_Handler
+#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
+#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
+#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
+#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
+#pragma weak TIM8_CC_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
+#pragma weak FSMC_IRQHandler = Default_Handler
+#pragma weak SDIO_IRQHandler = Default_Handler
+#pragma weak TIM5_IRQHandler = Default_Handler
+#pragma weak SPI3_IRQHandler = Default_Handler
+#pragma weak UART4_IRQHandler = Default_Handler
+#pragma weak UART5_IRQHandler = Default_Handler
+#pragma weak TIM6_DAC_IRQHandler = Default_Handler
+#pragma weak TIM7_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
+#pragma weak ETH_IRQHandler = Default_Handler
+#pragma weak ETH_WKUP_IRQHandler = Default_Handler
+#pragma weak CAN2_TX_IRQHandler = Default_Handler
+#pragma weak CAN2_RX0_IRQHandler = Default_Handler
+#pragma weak CAN2_RX1_IRQHandler = Default_Handler
+#pragma weak CAN2_SCE_IRQHandler = Default_Handler
+#pragma weak OTG_FS_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
+#pragma weak USART6_IRQHandler = Default_Handler
+#pragma weak I2C3_EV_IRQHandler = Default_Handler
+#pragma weak I2C3_ER_IRQHandler = Default_Handler
+#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
+#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
+#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
+#pragma weak OTG_HS_IRQHandler = Default_Handler
+#pragma weak DCMI_IRQHandler = Default_Handler
+#pragma weak CRYP_IRQHandler = Default_Handler
+#pragma weak HASH_RNG_IRQHandler = Default_Handler
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..8e5b0fb93c87f050464bd932e8c7b74f6a4eaa76
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp
@@ -0,0 +1,140 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp.cpp Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+
+#include <cstdlib>
+#include <inttypes.h>
+#include "interfaces/bsp.h"
+#ifdef WITH_FILESYSTEM
+#include "kernel/filesystem/filesystem.h"
+#endif //WITH_FILESYSTEM
+#include "kernel/kernel.h"
+#include "kernel/sync.h"
+#include "interfaces/delays.h"
+#include "interfaces/portability.h"
+#include "interfaces/arch_registers.h"
+#include "config/miosix_settings.h"
+#include "kernel/logging.h"
+#include "console-impl.h"
+
+namespace miosix {
+
+//
+// Initialization
+//
+
+void IRQbspInit()
+{
+ //Enable all gpios
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
+ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
+ RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
+ RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |
+ RCC_AHB1ENR_GPIOIEN;
+ GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS
+ GPIOB->OSPEEDR=0xaaaaaaaa;
+ GPIOC->OSPEEDR=0xaaaaaaaa;
+ GPIOD->OSPEEDR=0xf3ff0f0f | 0xaaaaaaaa; //GPIOD,E,F,G are used by the FSMC
+ GPIOE->OSPEEDR=0xffffc00f | 0xaaaaaaaa; //configure those pins as 100MHz
+ GPIOF->OSPEEDR=0xff000fff | 0xaaaaaaaa; //(constants taken from
+ GPIOG->OSPEEDR=0x000c0fff | 0xaaaaaaaa; // SystemInit_ExtMemCtl)
+ GPIOH->OSPEEDR=0xaaaaaaaa;
+ GPIOI->OSPEEDR=0xaaaaaaaa;
+ led::mode(Mode::OUTPUT);
+ sdCardDetect::mode(Mode::INPUT_PULL_UP);
+ ledOn();
+ delayMs(100);
+ ledOff();
+ #ifndef STDOUT_REDIRECTED_TO_DCC
+ IRQstm32f2serialPortInit();
+ #endif //STDOUT_REDIRECTED_TO_DCC
+}
+
+void bspInit2()
+{
+ //Nothing to do
+}
+
+//
+// Shutdown and reboot
+//
+
+/**
+This function disables filesystem (if enabled), serial port (if enabled) and
+puts the processor in deep sleep mode.<br>
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens.
+<br>This function does not return.<br>
+WARNING: close all files before using this function, since it unmounts the
+filesystem.<br>
+When in shutdown mode, power consumption of the miosix board is reduced to ~
+5uA??, however, true power consumption depends on what is connected to the GPIO
+pins. The user is responsible to put the devices connected to the GPIO pin in the
+minimal power consumption mode before calling shutdown(). Please note that to
+minimize power consumption all unused GPIO must not be left floating.
+*/
+void shutdown()
+{
+ pauseKernel();
+ #ifdef WITH_FILESYSTEM
+ Filesystem& fs=Filesystem::instance();
+ if(fs.isMounted()) fs.umount();
+ #endif //WITH_FILESYSTEM
+ //Disable interrupts
+ disableInterrupts();
+
+ /*
+ Removed because low power mode causes issues with SWD programming
+ RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating...
+ PWR->CR |= PWR_CR_PDDS; //Select standby mode
+ PWR->CR |= PWR_CR_CWUF;
+ PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source
+
+ SCB->SCR |= SCB_SCR_SLEEPDEEP;
+ __WFE();
+ NVIC_SystemReset();
+ */
+ for(;;) ;
+}
+
+void reboot()
+{
+ while(!Console::txComplete()) ;
+ pauseKernel();
+ //Turn off drivers
+ #ifdef WITH_FILESYSTEM
+ Filesystem::instance().umount();
+ #endif //WITH_FILESYSTEM
+ disableInterrupts();
+ miosix_private::IRQsystemReboot();
+}
+
+};//namespace miosix
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h
new file mode 100644
index 0000000000000000000000000000000000000000..3f2564b6afccc16e3713e495c2d629f5d2bc32bb
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h
@@ -0,0 +1,80 @@
+/***************************************************************************
+ * Copyright (C) 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp_impl.h Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+#ifndef BSP_IMPL_H
+#define BSP_IMPL_H
+
+#include "config/miosix_settings.h"
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+/**
+\addtogroup Hardware
+\{
+*/
+
+/**
+ * \internal
+ * used by the ledOn() and ledOff() implementation
+ */
+typedef Gpio<GPIOI_BASE,9> led;
+
+inline void ledOn()
+{
+ led::high();
+}
+
+inline void ledOff()
+{
+ led::low();
+}
+
+///\internal Pin connected to SD card detect
+typedef Gpio<GPIOH_BASE,13> sdCardDetect;
+
+/**
+ * Polls the SD card sense GPIO
+ * \return true if there is an uSD card in the socket.
+ */
+inline bool sdCardSense()
+{
+ return sdCardDetect::value()==0;
+}
+
+/**
+\}
+*/
+
+};//namespace miosix
+
+#endif //BSP_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console-impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console-impl.h
new file mode 100644
index 0000000000000000000000000000000000000000..549cddb662dda26775f21320d11027fa10a376de
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console-impl.h
@@ -0,0 +1,37 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#ifndef CONSOLE_IMPL_H
+#define CONSOLE_IMPL_H
+
+namespace miosix {
+
+void IRQstm32f2serialPortInit();
+
+} //namespace miosix
+
+#endif //CONSOLE_IMPL_H
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..a0742d1671d5af5cb0d7dbec264863fca5c5d2da
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/console.cpp
@@ -0,0 +1,228 @@
+/***************************************************************************
+ * Copyright (C) 2010, 2011, 2012 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#include "interfaces/console.h"
+#include "console-impl.h"
+#include "kernel/sync.h"
+#include "kernel/scheduler/scheduler.h"
+#include "kernel/logging.h"
+#include "interfaces/arch_registers.h"
+#include "interfaces/portability.h"
+#include "interfaces/gpio.h"
+#include "board_settings.h"
+#include "drivers/dcc.h"
+#include <cstring>
+
+#ifndef STDOUT_REDIRECTED_TO_DCC
+
+/**
+ * \internal
+ * serial port interrupt routine
+ * Since inside naked functions only assembler code is allowed, this function
+ * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls
+ * the implementation code in serial_irq_impl()
+ */
+void USART1_IRQHandler() __attribute__ ((naked));
+void USART1_IRQHandler()
+{
+ saveContext();
+ asm volatile("bl _ZN6miosix13serialIrqImplEv");
+ restoreContext();
+}
+
+namespace miosix {
+
+static Mutex rxMutex;///<\internal Mutex used to guard the rx queue
+static Mutex txMutex;///<\internal Mutex used to guard the tx queue
+const unsigned int SOFTWARE_RX_QUEUE=32;///<\internal Size of rx software queue
+static Queue<char,SOFTWARE_RX_QUEUE> rxQueue;///<\internal Rx software queue
+
+/**
+ * \internal
+ * Serial interrupt code. Declared noinline to avoid the compiler trying to
+ * inline it into the caller, which would violate the requirement on naked
+ * functions.
+ * Function is not static because otherwise the compiler optimizes it out...
+ */
+void serialIrqImpl() __attribute__((noinline));
+void serialIrqImpl()
+{
+ bool hppw=false;
+ unsigned int status=USART1->SR;
+ if(status & USART_SR_ORE) //Receiver overrun
+ {
+ char c=USART1->DR; //Always read data, since this clears interrupt flags
+ if((status & USART_SR_RXNE) && ((status & 0x7)==0))
+ rxQueue.IRQput(c,hppw);
+ } else if(status & USART_SR_RXNE) //Receiver data available
+ {
+ char c=USART1->DR; //Always read data, since this clears interrupt flags
+ if((status & 0x7)==0) //If no noise nor framing nor parity error
+ {
+ rxQueue.IRQput(c,hppw);
+ }
+ }
+ if(hppw) Scheduler::IRQfindNextThread();
+}
+
+void IRQstm32f2serialPortInit()
+{
+ rxQueue.IRQreset();
+ //Enable clock to GPIOA and USART1
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
+ RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
+ //Enabled, 8 data bit, no parity, interrupt on character rx
+ USART1->CR1 = USART_CR1_UE | USART_CR1_RXNEIE;
+ USART1->CR2 = 0;//Disable lin mode and synchronous mode
+ USART1->CR3 = 0;//Disable irda and smartcard mode
+
+ #ifdef SYSCLK_FREQ_120MHz
+ //USART1 is connected to APB1 @ 30MHz
+ const unsigned int brr = (97<<4) | (10<<0); //BRR=97.625 0.032% Error
+ #else
+ #warning "No serial baudrate for this clock frequency"
+ #endif
+ //baudrate=19200
+ USART1->BRR=brr;
+
+ //Now that serial port is active, configure I/Os
+ Gpio<GPIOA_BASE,9>::alternateFunction(7);
+ Gpio<GPIOA_BASE,9>::mode(Mode::ALTERNATE); //PA.9 = USART1 tx
+ Gpio<GPIOA_BASE,10>::alternateFunction(7);
+ Gpio<GPIOA_BASE,10>::mode(Mode::ALTERNATE); //PA.10 = USART1 rx
+ USART1->CR1 |= USART_CR1_TE | USART_CR1_RE;//Finally enable tx and rx
+ NVIC_SetPriority(USART1_IRQn,10);//Low priority for serial. (Max=0, min=15)
+ NVIC_EnableIRQ(USART1_IRQn);
+}
+
+static void serialWriteImpl(const char *str, unsigned int len)
+{
+ {
+ Lock<Mutex> l(txMutex);
+ for(unsigned int i=0;i<len;i++)
+ {
+ while((USART1->SR & USART_SR_TXE)==0) ;
+ USART1->DR=*str++;
+ }
+ }
+}
+
+void Console::write(const char *str)
+{
+ serialWriteImpl(str,std::strlen(str));
+}
+
+void Console::write(const char *data, int length)
+{
+ serialWriteImpl(data,length);
+}
+
+bool Console::txComplete()
+{
+ return (USART1->SR & USART_SR_TC)!=0;
+}
+
+void Console::IRQwrite(const char *str)
+{
+ while((*str)!='\0')
+ {
+ //Wait until the hardware fifo is ready to accept one char
+ while((USART1->SR & USART_SR_TXE)==0) ; //Wait until ready
+ USART1->DR=*str++;
+ }
+}
+
+bool Console::IRQtxComplete()
+{
+ return (USART1->SR & USART_SR_TC)!=0;
+}
+
+char Console::readChar()
+{
+ Lock<Mutex> l(rxMutex);
+ char result;
+ rxQueue.get(result);
+ return result;
+}
+
+bool Console::readCharNonBlocking(char& c)
+{
+ Lock<Mutex> l(rxMutex);
+ if(rxQueue.isEmpty()==false)
+ {
+ rxQueue.get(c);
+ return true;
+ }
+ return false;
+}
+
+} // namespace miosix
+
+#else //STDOUT_REDIRECTED_TO_DCC
+
+namespace miosix {
+
+void Console::write(const char *str)
+{
+ debugWrite(str,std::strlen(str));
+}
+
+void Console::write(const char *data, int length)
+{
+ debugWrite(data,length);
+}
+
+bool Console::txComplete()
+{
+ return true;
+}
+
+void Console::IRQwrite(const char *str)
+{
+ IRQdebugWrite(str);
+}
+
+bool Console::IRQtxComplete()
+{
+ return true;
+}
+
+char Console::readChar()
+{
+ errorLog("***stdin is not available in DCC");
+ for(;;) ;
+ return 0; //Only to avoid a compiler warning
+}
+
+bool Console::readCharNonBlocking(char& c)
+{
+ return false;
+}
+
+} //namespace miosix
+
+#endif //STDOUT_REDIRECTED_TO_DCC
diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld
new file mode 100644
index 0000000000000000000000000000000000000000..bc19fe4c0fc0de4a22a16ea4c4ff23d65dbf4a0d
--- /dev/null
+++ b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld
@@ -0,0 +1,166 @@
+/*
+ * C++ enabled linker script for stm32 (1M FLASH, 128K RAM)
+ * Developed by TFT: Terraneo Federico Technologies
+ * Optimized for use with the Miosix kernel
+ */
+
+/*
+ * This linker script puts:
+ * - read only data and code (.text, .rodata, .eh_*) in flash
+ * - stacks, heap and sections .data and .bss in the internal ram
+ * - the external ram (if available) is not used.
+ */
+
+/*
+ * The main stack is used for interrupt handling by the kernel.
+ *
+ * *** Readme ***
+ * This linker script places the main stack (used by the kernel for interrupts)
+ * at the bottom of the ram, instead of the top. This is done for two reasons:
+ *
+ * - as an optimization for microcontrollers with little ram memory. In fact
+ * the implementation of malloc from newlib requests memory to the OS in 4KB
+ * block (except the first block that can be smaller). This is probably done
+ * for compatibility with OSes with an MMU and paged memory. To see why this
+ * is bad, consider a microcontroller with 8KB of ram: when malloc finishes
+ * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
+ * fail because the top part of the ram is used by the main stack. As a
+ * result, the top part of the memory will not be used by malloc, even if
+ * available (and it is nearly *half* the ram on an 8KB mcu). By placing the
+ * main stack at the bottom of the ram, the upper 4KB block will be entirely
+ * free and available as heap space.
+ *
+ * - In case of main stack overflow the cpu will fault because access to memory
+ * before the beginning of the ram faults. Instead with the default stack
+ * placement the main stack will silently collide with the heap.
+ * Note: if increasing the main stack size also increase the ORIGIN value in
+ * the MEMORY definitions below accordingly.
+ */
+_main_stack_size = 0x00000200; /* main stack = 512Bytes */
+_main_stack_top = 0x20000000 + _main_stack_size;
+ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
+
+/* end of the heap on 128KB microcontrollers */
+_heap_end = 0x20020000; /* end of available ram */
+
+/* identify the Entry Point */
+ENTRY(_Z13Reset_Handlerv)
+
+/* specify the memory areas */
+MEMORY
+{
+ flash(rx) : ORIGIN = 0, LENGTH = 1M
+
+ /*
+ * Note, the ram starts at 0x20000000 but it is necessary to add the size
+ * of the main stack, so it is 0x20000200.
+ */
+ ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200
+}
+
+/* now define the output sections */
+SECTIONS
+{
+ . = 0;
+
+ /* .text section: code goes to flash */
+ .text :
+ {
+ /* Startup code must go at address 0 */
+ KEEP(*(.isr_vector))
+
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ /* these sections for thumb interwork? */
+ *(.glue_7)
+ *(.glue_7t)
+ /* these sections for C++? */
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.ARM.extab*)
+ *(.gnu.linkonce.armextab.*)
+
+ . = ALIGN(4);
+ /* .rodata: constant data */
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ /* C++ Static constructors/destructors (eabi) */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /* C++ Static constructors/destructors (elf) */
+ . = ALIGN(4);
+ _ctor_start = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ _ctor_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > flash
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ . = ALIGN(8);
+ _etext = .;
+
+ /* .data section: global variables go to ram, but also store a copy to
+ flash to initialize them */
+ .data : ALIGN(8)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ _edata = .;
+ } > ram AT > flash
+
+ /* .bss section: uninitialized global variables go to ram */
+ _bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ . = ALIGN(8);
+ } > ram
+ _bss_end = .;
+
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index f963354d242dabe0ace48b36f436175ae24299c6..7d1cc8df21817dac40549af00691f7bb1644cbee 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -13,13 +13,14 @@
## architecture
##
#OPT_BOARD := lpc2138_miosix_board
-OPT_BOARD := stm32f103ze_stm3210e-eval
+#OPT_BOARD := stm32f103ze_stm3210e-eval
#OPT_BOARD := stm32f103ve_mp3v2
#OPT_BOARD := stm32f100rb_stm32vldiscovery
#OPT_BOARD := stm32f103ve_strive_mini
#OPT_BOARD := stm32f103ze_redbull_v2
#OPT_BOARD := stm32f407vg_stm32f4discovery
#OPT_BOARD := stm32f207ig_stm3220g-eval
+OPT_BOARD := stm32f207zg_ethboard_v2
##
## Optimization flags, choose one.
@@ -173,6 +174,29 @@ ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval)
endif
+##---------------------------------------------------------------------------
+## stm32f207zg_ethboard_v2
+##
+ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2)
+
+ ## Linker script type, there are three options
+ ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld)
+ ## the most common choice, available for all microcontrollers
+ LINKER_SCRIPT_PATH := arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/
+ LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_rom.ld
+
+ ## Enable/disable initialization of external RAM at boot. Three options:
+ ## __ENABLE_XRAM : If you want the heap in xram (with an appropriate linker
+ ## script selected above)
+ ## __ENABLE_XRAM and __CODE_IN_XRAM : Debug mode with code + stack + heap
+ ## in xram (with an appropriate linker script selected above)
+ ## none selected : don't use xram (with an appropriate linker script
+ ## selected above)
+ XRAM := -D__ENABLE_XRAM
+ #XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM
+
+endif
+
############################################################################
## From the options selected above, now fill all the variables needed to ##
## build Miosix. You should modify something here only if you are adding ##
@@ -203,6 +227,8 @@ else ifeq ($(OPT_BOARD),stm32f407vg_stm32f4discovery)
ARCH := cortexM4_stm32f4
else ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval)
ARCH := cortexM3_stm32f2
+else ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2)
+ ARCH := cortexM3_stm32f2
else
$(error Error: no board specified in miosix/config/Makefile.inc)
endif
@@ -619,7 +645,7 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
ARCH_INC := arch/cortexM3_stm32f2/common
##-------------------------------------------------------------------------
- ## BOARD: stm32f4discovery
+ ## BOARD: stm32f207ig_stm3220g-eval
##
ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval)
## Base directory with header files for this board
@@ -657,6 +683,45 @@ else ifeq ($(ARCH),cortexM3_stm32f2)
PROGRAM_CMDLINE := qstlink2 -cqewV ./main.bin
endif
+ ##-------------------------------------------------------------------------
+ ## BOARD: stm32f207zg_ethboard_v2
+ ##
+ else ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2)
+ ## Base directory with header files for this board
+ BOARD_INC := arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2
+
+ ## Select linker script and boot file
+ ## Their path must be relative to the miosix directory.
+ BOOT_FILE := $(BOARD_INC)/core/stage_1_boot.o
+ #LINKER_SCRIPT := already selected in board options
+
+ ## Select architecture specific files
+ ## These are the files in arch/<arch name>/<board name>
+ ARCH_SRC := \
+ $(ARCH_INC)/interfaces-impl/disk.cpp \
+ $(BOARD_INC)/interfaces-impl/console.cpp \
+ $(BOARD_INC)/interfaces-impl/bsp.cpp
+
+ ## Add a #define to allow querying board name
+ CFLAGS_BASE += -D_BOARD_ETHBOARDV2
+ CXXFLAGS_BASE += -D_BOARD_ETHBOARDV2
+
+ ## Clock frequency
+ CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_120MHz=120000000
+
+ ## Select programmer command line
+ ## This is the program that is invoked when the user types
+ ## 'make program'
+ ## The command must provide a way to program the board, or print an
+ ## error message saying that 'make program' is not supported for that
+ ## board.
+ ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_1m+128k_all_in_xram.ld)
+ PROGRAM_CMDLINE := miosix/bootloaders/stm32/pc_loader/pc_loader \
+ /dev/ttyUSB0 main.bin
+ else
+ PROGRAM_CMDLINE := stm32flash -w main.hex -v /dev/ttyUSB1
+ endif
+
##-------------------------------------------------------------------------
## End of board list
##
diff --git a/miosix_np_2/nbproject/configurations.xml b/miosix_np_2/nbproject/configurations.xml
index 6d64703629e4cd82ebafa6c3f39c976abfa372c7..4c79af640255b4d640a061c44605578e4971a654 100644
--- a/miosix_np_2/nbproject/configurations.xml
+++ b/miosix_np_2/nbproject/configurations.xml
@@ -166,6 +166,19 @@
</df>
<in>board_settings.h</in>
</df>
+ <df name="stm32f207zg_EthBoardV2">
+ <df name="core">
+ <in>stage_1_boot.cpp</in>
+ </df>
+ <df name="interfaces-impl">
+ <in>bsp.cpp</in>
+ <in>bsp_impl.h</in>
+ <in>console-impl.h</in>
+ <in>console.cpp</in>
+ </df>
+ <in>board_settings.h</in>
+ <in>stm32_1m+128k_rom.ld</in>
+ </df>
</df>
<df name="cortexM4_stm32f4">
<df name="common">