From dedbe3b906e08c29f4b1bd87a70918b39ea76a8a Mon Sep 17 00:00:00 2001
From: Terraneo Federico <fede.tft@miosix.org>
Date: Sun, 19 Aug 2018 00:09:03 +0200
Subject: [PATCH] Removed unneeded DSB in cacheless architectures

---
 miosix/arch/common/core/cache_cortexMx.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/miosix/arch/common/core/cache_cortexMx.h b/miosix/arch/common/core/cache_cortexMx.h
index 728c594c..2c0e6667 100644
--- a/miosix/arch/common/core/cache_cortexMx.h
+++ b/miosix/arch/common/core/cache_cortexMx.h
@@ -122,6 +122,7 @@ void IRQconfigureCache(const unsigned int *xramBase=nullptr, unsigned int xramSi
  */
 inline void markBufferBeforeDmaWrite(const void *buffer, int size)
 {
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1)
     // You may think that since the cache is configured as write-through,
     // there's nothing to do before the DMA can read a memory buffer just
     // written by the CPU, right? Wrong! Other than the cache, there's the
@@ -132,6 +133,7 @@ inline void markBufferBeforeDmaWrite(const void *buffer, int size)
     // this __DSB() is removed. Apparently, the characters remian in the write
     // buffer.
     __DSB();
+#endif
 }
 
 /**
-- 
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