diff --git a/miosix/arch/common/drivers/stm32f7_serial.cpp b/miosix/arch/common/drivers/stm32f7_serial.cpp index 89f789a3a91721e4a535d79271cfca0979e7b322..812eb3eefdcdbecee3d841978ee4717132b3ce75 100644 --- a/miosix/arch/common/drivers/stm32f7_serial.cpp +++ b/miosix/arch/common/drivers/stm32f7_serial.cpp @@ -306,7 +306,7 @@ static const STM32SerialHW ports[maxPorts] = { DMA2_Channel7, DMA2_Channel7_IRQn, STM32SerialDMAHW::Channel7, {7+7, 35}, DMA2_Channel6, DMA2_Channel6_IRQn, STM32SerialDMAHW::Channel6, {7+6, 34} } }, }; -#elif defined(STM32H755xx) +#elif defined(STM32H755xx) || defined(STM32H753xx) static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; static const STM32SerialAltFunc::Span uart1AfSpans[]={{1,14,7},{0,0,4}}; @@ -351,6 +351,60 @@ static const STM32SerialHW ports[maxPorts] = { { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB4, RCC_APB4ENR_LPUART1EN, { 0 } }, }; +#elif defined(STM32H723xx) +static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; +static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; +static const STM32SerialAltFunc::Span af11Spans[]={{0,0,11}}; +static const STM32SerialAltFunc::Span uart1AfSpans[]={{1,14,7},{0,0,4}}; +static const STM32SerialAltFunc::Span uart4AfSpans[]={{0,11,8},{0,15,6},{0,0,8}}; +static const STM32SerialAltFunc::Span uart5AfSpans[]={{2,8,14},{0,0,8}}; +static const STM32SerialAltFunc::Span uart7AfSpans[]={{4,0,11},{0,0,7}}; +static const STM32SerialAltFunc::Span lpuart1AfSpans[]={{1,0,3},{0,0,8}}; +constexpr int maxPorts = 11; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {uart1AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, {8+7, 42}, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, {8+5, 41} } }, + { USART2, USART2_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 44}, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, {0+5, 43} } }, + { USART3, USART3_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 46}, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 45} } }, + { UART4 , UART4_IRQn , {uart4AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, {0+4, 64}, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, {0+2, 63} } }, + { UART5 , UART5_IRQn , {uart5AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, {0+7, 66}, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 65} } }, + { USART6, USART6_IRQn, {af7Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, {8+6, 72}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 71} } }, + { UART7 , UART7_IRQn , {uart7AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 80}, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 79} } }, + { UART8 , UART8_IRQn , {af8Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 82}, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 81} } }, + { UART9 , UART9_IRQn , {af11Spans}, false, STM32Bus::APB2, RCC_APB2ENR_UART9EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Stream0, DMA2_Stream0_IRQn, STM32SerialDMAHW::Stream0, {8+0, 117}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 116} } }, + { USART10, USART10_IRQn, {af11Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART10EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Stream0, DMA2_Stream0_IRQn, STM32SerialDMAHW::Stream0, {8+0, 119}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 118} } }, + { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB4, RCC_APB4ENR_LPUART1EN, + { 0 } }, +}; #else #error Unsupported STM32 chip for this serial driver #endif diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/boot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca14d36d1f7feee139f2fea02ea77cb148707b0c --- /dev/null +++ b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/boot.cpp @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see <http://www.gnu.org/licenses/> * + ***************************************************************************/ + +#include "drivers/pll.h" +#include "cache/cortexMx_cache.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + SystemInit(); + startPll(); + miosix::IRQconfigureCache(); +} + +} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index dc16c6c432d7704813afe6d28d3639478c7a0ad1..0000000000000000000000000000000000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,576 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "cache/cortexMx_cache.h" -#include "drivers/pll.h" -#include "kernel/stage_2_boot.h" -#include <string.h> - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32h753 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - startPll(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void /*__attribute__((weak))*/ SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_AVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT1_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) FDCAN_CAL_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_PSSI_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) OCTOSPI1_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) MDIOS_WKUP_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); -void __attribute__((weak)) MDMA_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) HSEM1_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) DMAMUX2_OVR_IRQHandler(); -void __attribute__((weak)) BDMA_Channel0_IRQHandler(); -void __attribute__((weak)) BDMA_Channel1_IRQHandler(); -void __attribute__((weak)) BDMA_Channel2_IRQHandler(); -void __attribute__((weak)) BDMA_Channel3_IRQHandler(); -void __attribute__((weak)) BDMA_Channel4_IRQHandler(); -void __attribute__((weak)) BDMA_Channel5_IRQHandler(); -void __attribute__((weak)) BDMA_Channel6_IRQHandler(); -void __attribute__((weak)) BDMA_Channel7_IRQHandler(); -void __attribute__((weak)) COMP_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) LPTIM3_IRQHandler(); -void __attribute__((weak)) LPTIM4_IRQHandler(); -void __attribute__((weak)) LPTIM5_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) ECC_IRQHandler(); -void __attribute__((weak)) SAI4_IRQHandler(); -void __attribute__((weak)) DTS_IRQHandler(); -void __attribute__((weak)) WAKEUP_PIN_IRQHandler(); -void __attribute__((weak)) OCTOSPI2_IRQHandler(); -void __attribute__((weak)) FMAC_IRQHandler(); -void __attribute__((weak)) CORDIC_IRQHandler(); -void __attribute__((weak)) UART9_IRQHandler(); -void __attribute__((weak)) USART10_IRQHandler(); -void __attribute__((weak)) I2C5_EV_IRQHandler(); -void __attribute__((weak)) I2C5_ER_IRQHandler(); -void __attribute__((weak)) FDCAN3_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN3_IT1_IRQHandler(); -void __attribute__((weak)) TIM23_IRQHandler(); -void __attribute__((weak)) TIM24_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_AVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - FDCAN1_IT0_IRQHandler, - FDCAN2_IT0_IRQHandler, - FDCAN1_IT1_IRQHandler, - FDCAN2_IT1_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - 0, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - FDCAN_CAL_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_PSSI_IRQHandler, // - 0, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - 0, - OCTOSPI1_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - 0, - 0, - 0, - 0, - DMAMUX1_OVR_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - 0, - SWPMI1_IRQHandler, - TIM15_IRQHandler, - TIM16_IRQHandler, - TIM17_IRQHandler, - MDIOS_WKUP_IRQHandler, - MDIOS_IRQHandler, - 0, - MDMA_IRQHandler, - 0, - SDMMC2_IRQHandler, - HSEM1_IRQHandler, - 0, - ADC3_IRQHandler, - DMAMUX2_OVR_IRQHandler, - BDMA_Channel0_IRQHandler, - BDMA_Channel1_IRQHandler, - BDMA_Channel2_IRQHandler, - BDMA_Channel3_IRQHandler, - BDMA_Channel4_IRQHandler, - BDMA_Channel5_IRQHandler, - BDMA_Channel6_IRQHandler, - BDMA_Channel7_IRQHandler, - COMP_IRQHandler, - LPTIM2_IRQHandler, - LPTIM3_IRQHandler, - LPTIM4_IRQHandler, - LPTIM5_IRQHandler, - LPUART1_IRQHandler, - 0, - CRS_IRQHandler, - ECC_IRQHandler, - SAI4_IRQHandler, - DTS_IRQHandler, - 0, - WAKEUP_PIN_IRQHandler, - OCTOSPI2_IRQHandler, - 0, - 0, - FMAC_IRQHandler, - CORDIC_IRQHandler, - UART9_IRQHandler, - USART10_IRQHandler, - I2C5_EV_IRQHandler, - I2C5_ER_IRQHandler, - FDCAN3_IT0_IRQHandler, - FDCAN3_IT1_IRQHandler, - TIM23_IRQHandler, - TIM24_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_AVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT1_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak FDCAN_CAL_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_PSSI_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak OCTOSPI1_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak MDIOS_WKUP_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler -#pragma weak MDMA_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak HSEM1_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak DMAMUX2_OVR_IRQHandler = Default_Handler -#pragma weak BDMA_Channel0_IRQHandler = Default_Handler -#pragma weak BDMA_Channel1_IRQHandler = Default_Handler -#pragma weak BDMA_Channel2_IRQHandler = Default_Handler -#pragma weak BDMA_Channel3_IRQHandler = Default_Handler -#pragma weak BDMA_Channel4_IRQHandler = Default_Handler -#pragma weak BDMA_Channel5_IRQHandler = Default_Handler -#pragma weak BDMA_Channel6_IRQHandler = Default_Handler -#pragma weak BDMA_Channel7_IRQHandler = Default_Handler -#pragma weak COMP_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak LPTIM3_IRQHandler = Default_Handler -#pragma weak LPTIM4_IRQHandler = Default_Handler -#pragma weak LPTIM5_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak ECC_IRQHandler = Default_Handler -#pragma weak SAI4_IRQHandler = Default_Handler -#pragma weak DTS_IRQHandler = Default_Handler -#pragma weak WAKEUP_PIN_IRQHandler = Default_Handler -#pragma weak OCTOSPI2_IRQHandler = Default_Handler -#pragma weak FMAC_IRQHandler = Default_Handler -#pragma weak CORDIC_IRQHandler = Default_Handler -#pragma weak UART9_IRQHandler = Default_Handler -#pragma weak USART10_IRQHandler = Default_Handler -#pragma weak I2C5_EV_IRQHandler = Default_Handler -#pragma weak I2C5_ER_IRQHandler = Default_Handler -#pragma weak FDCAN3_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN3_IT1_IRQHandler = Default_Handler -#pragma weak TIM23_IRQHandler = Default_Handler -#pragma weak TIM24_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h index f1b822eb83c157d0350a9a0488f0cbf05eb5cb29..1956249432a8f1d5abc5b7819afd48520dd02059 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h +++ b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h @@ -19,3 +19,6 @@ //CPU level alone, the bus matrices and peripherals themselves may also reorder //accesses as a side-effect of how they work. #define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 162, so there are 163 +#define MIOSIX_NUM_PERIPHERAL_IRQ 163 diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp index d25b0d4ca10ec6d4a705bd85cd7b8ee02e78a923..6cac84ea80b96d1fdb88ac6d86206d1a83f4a90d 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp +++ b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp @@ -33,6 +33,7 @@ #include <cstdlib> #include <inttypes.h> #include <sys/ioctl.h> +#include "interfaces/bsp.h" #include "interfaces_private/bsp_private.h" #include "kernel/kernel.h" #include "kernel/sync.h" @@ -77,10 +78,11 @@ void IRQbspInit() ledOn(); delayMs(100); ledOff(); - auto tx=Gpio<GPIOD_BASE,8>::getPin(); tx.alternateFunction(7); - auto rx=Gpio<GPIOD_BASE,9>::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>( - new STM32Serial(defaultSerialPort,defaultSerialSpeed,tx,rx))); + DefaultConsole::instance().IRQset( + STM32SerialBase::get<defaultSerialTxPin,defaultSerialRxPin, + defaultSerialRtsPin,defaultSerialCtsPin>( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); } void bspInit2() diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld index e938c9c2ec0630ec156b13e88ff1782df22c1d75..a75cb5a929abed3d9854f85d0e614fc812e00ecb 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld +++ b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld @@ -44,7 +44,7 @@ ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); _heap_end = 0x24020000; /* end of available ram */ /* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) +ENTRY(_ZN6miosix13Reset_HandlerEv) /* specify the memory areas */ MEMORY @@ -121,7 +121,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*crtend.o(.ctors)) - _ctor_end = .; + _ctor_end = .; . = ALIGN(4); KEEP (*crtbegin.o(.dtors)) diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/boot.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca14d36d1f7feee139f2fea02ea77cb148707b0c --- /dev/null +++ b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/boot.cpp @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see <http://www.gnu.org/licenses/> * + ***************************************************************************/ + +#include "drivers/pll.h" +#include "cache/cortexMx_cache.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + SystemInit(); + startPll(); + miosix::IRQconfigureCache(); +} + +} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp deleted file mode 100644 index c33a3ad282960e1f8eabb6dcfb0d5cd20eba9281..0000000000000000000000000000000000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp +++ /dev/null @@ -1,567 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "cache/cortexMx_cache.h" -#include "drivers/pll.h" -#include "kernel/stage_2_boot.h" -#include <string.h> - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32h753 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - startPll(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_AVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT1_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) FDCAN_CAL_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); -void __attribute__((weak)) HRTIM1_Master_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMA_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMB_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMC_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMD_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIME_IRQHandler(); -void __attribute__((weak)) HRTIM1_FLT_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SAI3_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) MDIOS_WKUP_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDMA_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) HSEM1_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) DMAMUX2_OVR_IRQHandler(); -void __attribute__((weak)) BDMA_Channel0_IRQHandler(); -void __attribute__((weak)) BDMA_Channel1_IRQHandler(); -void __attribute__((weak)) BDMA_Channel2_IRQHandler(); -void __attribute__((weak)) BDMA_Channel3_IRQHandler(); -void __attribute__((weak)) BDMA_Channel4_IRQHandler(); -void __attribute__((weak)) BDMA_Channel5_IRQHandler(); -void __attribute__((weak)) BDMA_Channel6_IRQHandler(); -void __attribute__((weak)) BDMA_Channel7_IRQHandler(); -void __attribute__((weak)) COMP1_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) LPTIM3_IRQHandler(); -void __attribute__((weak)) LPTIM4_IRQHandler(); -void __attribute__((weak)) LPTIM5_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) SAI4_IRQHandler(); -void __attribute__((weak)) WAKEUP_PIN_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_AVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - FDCAN1_IT0_IRQHandler, - FDCAN2_IT0_IRQHandler, - FDCAN1_IT1_IRQHandler, - FDCAN2_IT1_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - 0, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - FDCAN_CAL_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - OTG_FS_EP1_OUT_IRQHandler, - OTG_FS_EP1_IN_IRQHandler, - OTG_FS_WKUP_IRQHandler, - OTG_FS_IRQHandler, - DMAMUX1_OVR_IRQHandler, - HRTIM1_Master_IRQHandler, - HRTIM1_TIMA_IRQHandler, - HRTIM1_TIMB_IRQHandler, - HRTIM1_TIMC_IRQHandler, - HRTIM1_TIMD_IRQHandler, - HRTIM1_TIME_IRQHandler, - HRTIM1_FLT_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SAI3_IRQHandler, - SWPMI1_IRQHandler, - TIM15_IRQHandler, - TIM16_IRQHandler, - TIM17_IRQHandler, - MDIOS_WKUP_IRQHandler, - MDIOS_IRQHandler, - JPEG_IRQHandler, - MDMA_IRQHandler, - 0, - SDMMC2_IRQHandler, - HSEM1_IRQHandler, - 0, - ADC3_IRQHandler, - DMAMUX2_OVR_IRQHandler, - BDMA_Channel0_IRQHandler, - BDMA_Channel1_IRQHandler, - BDMA_Channel2_IRQHandler, - BDMA_Channel3_IRQHandler, - BDMA_Channel4_IRQHandler, - BDMA_Channel5_IRQHandler, - BDMA_Channel6_IRQHandler, - BDMA_Channel7_IRQHandler, - COMP1_IRQHandler, - LPTIM2_IRQHandler, - LPTIM3_IRQHandler, - LPTIM4_IRQHandler, - LPTIM5_IRQHandler, - LPUART1_IRQHandler, - 0, - CRS_IRQHandler, - 0, - SAI4_IRQHandler, - 0, - 0, - WAKEUP_PIN_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_AVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT1_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak FDCAN_CAL_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler -#pragma weak HRTIM1_Master_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMA_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMB_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMC_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMD_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIME_IRQHandler = Default_Handler -#pragma weak HRTIM1_FLT_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SAI3_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak MDIOS_WKUP_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDMA_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak HSEM1_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak DMAMUX2_OVR_IRQHandler = Default_Handler -#pragma weak BDMA_Channel0_IRQHandler = Default_Handler -#pragma weak BDMA_Channel1_IRQHandler = Default_Handler -#pragma weak BDMA_Channel2_IRQHandler = Default_Handler -#pragma weak BDMA_Channel3_IRQHandler = Default_Handler -#pragma weak BDMA_Channel4_IRQHandler = Default_Handler -#pragma weak BDMA_Channel5_IRQHandler = Default_Handler -#pragma weak BDMA_Channel6_IRQHandler = Default_Handler -#pragma weak BDMA_Channel7_IRQHandler = Default_Handler -#pragma weak COMP1_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak LPTIM3_IRQHandler = Default_Handler -#pragma weak LPTIM4_IRQHandler = Default_Handler -#pragma weak LPTIM5_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak SAI4_IRQHandler = Default_Handler -#pragma weak WAKEUP_PIN_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h index 2e554b1a0b84e15ef8554250f10ec944679af4fd..d13b03f1cbd6346ed73a65d32d9dea61585fa75e 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h +++ b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h @@ -19,3 +19,6 @@ //CPU level alone, the bus matrices and peripherals themselves may also reorder //accesses as a side-effect of how they work. #define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 149, so there are 150 +#define MIOSIX_NUM_PERIPHERAL_IRQ 150 diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp index 1b7725687d2923a91b12fd53b2d35dd603b6204d..4ad630093cbe156ff6b0a22506872ba743f7d54f 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp +++ b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp @@ -33,6 +33,7 @@ #include <cstdlib> #include <inttypes.h> #include <sys/ioctl.h> +#include "interfaces/bsp.h" #include "interfaces_private/bsp_private.h" #include "kernel/kernel.h" #include "kernel/sync.h" @@ -78,10 +79,11 @@ void IRQbspInit() ledOn(); delayMs(100); ledOff(); - auto tx=Gpio<GPIOB_BASE,14>::getPin(); tx.alternateFunction(4); - auto rx=Gpio<GPIOB_BASE,15>::getPin(); rx.alternateFunction(4); - DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>( - new STM32Serial(1,defaultSerialSpeed,tx,rx))); + DefaultConsole::instance().IRQset( + STM32SerialBase::get<defaultSerialTxPin,defaultSerialRxPin, + defaultSerialRtsPin,defaultSerialCtsPin>( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); } void bspInit2() diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld index 47cf466f153199aed1949bb11151b37b816c4516..d6bbf18c875c165808e326f94f8b5b9309488e1a 100644 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld +++ b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld @@ -44,7 +44,7 @@ ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); _heap_end = 0x24080000; /* end of available ram */ /* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) +ENTRY(_ZN6miosix13Reset_HandlerEv) /* specify the memory areas */ MEMORY @@ -121,7 +121,7 @@ SECTIONS KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*crtend.o(.ctors)) - _ctor_end = .; + _ctor_end = .; . = ALIGN(4); KEEP (*crtbegin.o(.dtors)) diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc index 12d9a49fe87bfcd22f247f1cc17a304ae5dca1fd..35358360370a2664c831769a23bfaa2ad1bd380c 100644 --- a/miosix/config/Makefile.inc +++ b/miosix/config/Makefile.inc @@ -2661,7 +2661,7 @@ else ifeq ($(ARCH),cortexM7_stm32h7) ## Select architecture specific files ## These are the files in arch/<arch name>/<board name> ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ + $(BOARD_INC)/boot.cpp \ arch/common/drivers/stm32_hardware_rng.cpp \ $(BOARD_INC)/interfaces-impl/bsp.cpp @@ -2694,7 +2694,7 @@ else ifeq ($(ARCH),cortexM7_stm32h7) ## Select architecture specific files ## These are the files in arch/<arch name>/<board name> ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ + $(BOARD_INC)/boot.cpp \ arch/common/drivers/stm32_hardware_rng.cpp \ $(BOARD_INC)/interfaces-impl/bsp.cpp diff --git a/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h index 5078fc785b9a2830f54e9bedb9d7fd75fcad65bd..4fd16e94143f42e3ae358c88ec887c4b354b9d8c 100644 --- a/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h +++ b/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h @@ -27,6 +27,8 @@ #pragma once +#include "interfaces/gpio.h" + /** * \internal * Versioning for board_settings.h for out of git tree projects @@ -45,12 +47,27 @@ namespace miosix { const unsigned int MAIN_STACK_SIZE=4*1024; /// Serial port -//This board only exposes USART1, without flow control +/// This board only exposes USART3, without flow control +/// Serial ports 1 to 11 are available (11 is LPUART1) +const unsigned int defaultSerial=3; const unsigned int defaultSerialSpeed=115200; -const unsigned int defaultSerialPort=3; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio<GPIOA_BASE,9>; +//using defaultSerialRxPin = Gpio<GPIOA_BASE,10>; +//using defaultSerialRtsPin = Gpio<GPIOA_BASE,12>; +//using defaultSerialCtsPin = Gpio<GPIOA_BASE,11>; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio<GPIOA_BASE,2>; +//using defaultSerialRxPin = Gpio<GPIOA_BASE,3>; +//using defaultSerialRtsPin = Gpio<GPIOA_BASE,1>; +//using defaultSerialCtsPin = Gpio<GPIOA_BASE,0>; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio<GPIOD_BASE,8>; +using defaultSerialRxPin = Gpio<GPIOD_BASE,9>; +using defaultSerialRtsPin = Gpio<GPIOB_BASE,14>; +using defaultSerialCtsPin = Gpio<GPIOB_BASE,13>; //SD card driver static const unsigned char sdVoltage=33; //Board powered @ 3.3V diff --git a/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h b/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h index 26f0d78597853f1a72665a5f663ca9ba8d19a5ed..01502c0966ba25ef7969ff971f12a0ec0bffec19 100644 --- a/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h +++ b/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h @@ -27,6 +27,8 @@ #pragma once +#include "interfaces/gpio.h" + /** * \internal * Versioning for board_settings.h for out of git tree projects @@ -46,10 +48,26 @@ const unsigned int MAIN_STACK_SIZE=4*1024; /// Serial port //This board only exposes USART1, without flow control +/// Serial ports 1 to 9 are available (9 is LPUART1) +const unsigned int defaultSerial=1; const unsigned int defaultSerialSpeed=115200; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio<GPIOB_BASE,14>; +using defaultSerialRxPin = Gpio<GPIOB_BASE,15>; +using defaultSerialRtsPin = Gpio<GPIOA_BASE,12>; +using defaultSerialCtsPin = Gpio<GPIOA_BASE,11>; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio<GPIOA_BASE,2>; +//using defaultSerialRxPin = Gpio<GPIOA_BASE,3>; +//using defaultSerialRtsPin = Gpio<GPIOA_BASE,1>; +//using defaultSerialCtsPin = Gpio<GPIOA_BASE,0>; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio<GPIOB_BASE,10>; +//using defaultSerialRxPin = Gpio<GPIOB_BASE,11>; +//using defaultSerialRtsPin = Gpio<GPIOB_BASE,14>; +//using defaultSerialCtsPin = Gpio<GPIOB_BASE,13>; //SD card driver static const unsigned char sdVoltage=33; //Board powered @ 3.3V