diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json index 5b8fc33c9a92ca2b1c750e9c11dc7e1f041d96af..2a83b9b7e3b7a7342b6c74588a0b44059501c90a 100644 --- a/.vscode/c_cpp_properties.json +++ b/.vscode/c_cpp_properties.json @@ -317,6 +317,59 @@ ], "limitSymbolsToIncludedHeaders": true } + }, + { + "name": "stm32f429zi_skyward_ciuti", + "cStandard": "c11", + "cppStandard": "c++11", + "compilerPath": "/opt/arm-miosix-eabi/bin/arm-miosix-eabi-g++", + "defines": [ + "DEBUG", + "_ARCH_CORTEXM3_STM32F2", + "_BOARD_STM32F205RC_SKYWARD_CIUTI", + "_MIOSIX_BOARDNAME=stm32f205RC_skyward_ciuti", + "HSE_VALUE=25000000", + "SYSCLK_FREQ_120MHz=120000000", + "_MIOSIX", + "__cplusplus=201103L" + ], + "includePath": [ + "${workspaceFolder}/libs/miosix-kernel/miosix/config/arch/cortexM3_stm32f2/stm32f205rc_skyward_ciuti", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_ciuti", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/cortexM3_stm32f2/common", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/common", + "${workspaceFolder}/libs/miosix-kernel/miosix", + "${workspaceFolder}/libs/mavlink-skyward-lib", + "${workspaceFolder}/libs/fmt/include", + "${workspaceFolder}/libs/eigen", + "${workspaceFolder}/libs/tscpp", + "${workspaceFolder}/libs", + "${workspaceFolder}/src/shared", + "${workspaceFolder}/src/tests" + ], + "browse": { + "path": [ + "${workspaceFolder}/libs/miosix-kernel/miosix/config/arch/cortexM3_stm32f2/stm32f205rc_skyward_ciuti", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_ciuti", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/cortexM3_stm32f2/common", + "${workspaceFolder}/libs/miosix-kernel/miosix/stdlib_integration", + "${workspaceFolder}/libs/miosix-kernel/miosix/arch/common", + "${workspaceFolder}/libs/miosix-kernel/miosix/interfaces", + "${workspaceFolder}/libs/miosix-kernel/miosix/filesystem", + "${workspaceFolder}/libs/miosix-kernel/miosix/kernel", + "${workspaceFolder}/libs/miosix-kernel/miosix/util", + "${workspaceFolder}/libs/miosix-kernel/miosix/e20", + "${workspaceFolder}/libs/miosix-kernel/miosix/*", + "${workspaceFolder}/libs/mavlink-skyward-lib", + "${workspaceFolder}/libs/eigen", + "${workspaceFolder}/libs/tscpp", + "${workspaceFolder}/libs/mxgui", + "${workspaceFolder}/libs/fmt", + "${workspaceFolder}/src/shared", + "${workspaceFolder}/src/tests" + ], + "limitSymbolsToIncludedHeaders": true + } } ], "version": 4 diff --git a/.vscode/settings.json b/.vscode/settings.json index 970b24a8f12050767f47bbe36f4aa685b888e1ea..499e63fbe0bc2fbf8adf05ba283e4de56d1fb77a 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -136,6 +136,7 @@ "croll", "cwise", "cyaw", + "DATABUS", "deleteme", "DMEIE", "Doxyfile", @@ -182,6 +183,7 @@ "MINC", "miosix", "mkdir", + "mosfet", "mosi", "MPXHZ", "Musso", @@ -234,6 +236,7 @@ "vbat", "velnord", "vout", + "vsense", "Xbee", "xnord", "yned" diff --git a/libs/miosix-kernel b/libs/miosix-kernel index f677ab34c0972ce06f622386acc560cb6da4b832..80ae230d328892074ef362c46f8ed72ec07a3141 160000 --- a/libs/miosix-kernel +++ b/libs/miosix-kernel @@ -1 +1 @@ -Subproject commit f677ab34c0972ce06f622386acc560cb6da4b832 +Subproject commit 80ae230d328892074ef362c46f8ed72ec07a3141 diff --git a/libs/mxgui b/libs/mxgui index bf9ef728fbe5f6df084120bdbde51c335951ac48..3ce4e0588633ead6328e65b1e711ea39375a805e 160000 --- a/libs/mxgui +++ b/libs/mxgui @@ -1 +1 @@ -Subproject commit bf9ef728fbe5f6df084120bdbde51c335951ac48 +Subproject commit 3ce4e0588633ead6328e65b1e711ea39375a805e diff --git a/src/shared/utils/ClockUtils.h b/src/shared/utils/ClockUtils.h index 3d671d9f48311aae9bae40d24b5f022e6d9d8e8e..addbdafb8c0bc54895f75fea3f8cb7294c257274 100644 --- a/src/shared/utils/ClockUtils.h +++ b/src/shared/utils/ClockUtils.h @@ -79,7 +79,7 @@ inline uint32_t ClockUtils::getAPBFrequency(APB bus) // The position of the PPRE1 bit in RCC->CFGR is different in some stm32 #ifdef _ARCH_CORTEXM3_STM32 const uint32_t ppre1 = 8; -#elif _ARCH_CORTEXM4_STM32F4 +#elif _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM3_STM32F2 const uint32_t ppre1 = 10; #else #error "Architecture not supported by TimerUtils" @@ -95,7 +95,7 @@ inline uint32_t ClockUtils::getAPBFrequency(APB bus) // The position of the PPRE2 bit in RCC->CFGR is different in some stm32 #ifdef _ARCH_CORTEXM3_STM32 const uint32_t ppre2 = 11; -#elif _ARCH_CORTEXM4_STM32F4 +#elif _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM3_STM32F2 const uint32_t ppre2 = 13; #else #error "Architecture not supported by TimerUtils" @@ -159,9 +159,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral) case BKPSRAM_BASE: RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN; break; +#ifndef _ARCH_CORTEXM3_STM32F2 case CCMDATARAM_BASE: RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN; break; +#endif case DMA1_BASE: RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; break; @@ -173,9 +175,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral) RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN; break; #endif +#ifndef _ARCH_CORTEXM3_STM32F2 case ETH_MAC_BASE: RCC->AHB1ENR |= RCC_AHB1ENR_ETHMACEN; break; +#endif case USB_OTG_HS_PERIPH_BASE: RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN; break; @@ -183,9 +187,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral) // AHB2 peripherals { +#ifndef _ARCH_CORTEXM3_STM32F2 case DCMI_BASE: RCC->AHB2ENR |= RCC_AHB2ENR_DCMIEN; break; +#endif case RNG_BASE: RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; break; @@ -395,9 +401,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral) case BKPSRAM_BASE: RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN; break; +#ifndef _ARCH_CORTEXM3_STM32F2 case CCMDATARAM_BASE: RCC->AHB1ENR &= ~RCC_AHB1ENR_CCMDATARAMEN; break; +#endif case DMA1_BASE: RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN; break; @@ -409,9 +417,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral) RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2DEN; break; #endif +#ifndef _ARCH_CORTEXM3_STM32F2 case ETH_MAC_BASE: RCC->AHB1ENR &= ~RCC_AHB1ENR_ETHMACEN; break; +#endif case USB_OTG_HS_PERIPH_BASE: RCC->AHB1ENR &= ~RCC_AHB1ENR_OTGHSEN; break; @@ -419,9 +429,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral) // AHB2 peripherals { +#ifndef _ARCH_CORTEXM3_STM32F2 case DCMI_BASE: RCC->AHB2ENR &= ~RCC_AHB2ENR_DCMIEN; break; +#endif case RNG_BASE: RCC->AHB2ENR &= ~RCC_AHB2ENR_RNGEN; break;