diff --git a/cmake/boardcore.cmake b/cmake/boardcore.cmake
index 8bd4c6b27c57ce4b0b7cc01993586353fc3368c4..85a9460af1df62a61416beecb3976a89e67037e0 100644
--- a/cmake/boardcore.cmake
+++ b/cmake/boardcore.cmake
@@ -57,6 +57,7 @@ set(BOARDCORE_SRC
${BOARDCORE_PATH}/src/shared/drivers/canbus/CanDriver/CanInterrupt.cpp
${BOARDCORE_PATH}/src/shared/drivers/canbus/CanProtocol/CanProtocol.cpp
${BOARDCORE_PATH}/src/shared/drivers/dma/DMA.cpp
+ ${BOARDCORE_PATH}/src/shared/drivers/dma/DMADefs.cpp
${BOARDCORE_PATH}/src/shared/drivers/interrupt/external_interrupts.cpp
${BOARDCORE_PATH}/src/shared/drivers/timer/PWM.cpp
${BOARDCORE_PATH}/src/shared/drivers/timer/CountedPWM.cpp
diff --git a/src/shared/drivers/dma/DMA.cpp b/src/shared/drivers/dma/DMA.cpp
index d654466d8b3cf8e63635626fedd7e96d7604e081..a38af66d3880dea77c9e1ac6606451bcca9242e1 100644
--- a/src/shared/drivers/dma/DMA.cpp
+++ b/src/shared/drivers/dma/DMA.cpp
@@ -1,5 +1,5 @@
-/* Copyright (c) 2023 Skyward Experimental Rocketry
- * Author: Alberto Nidasio
+/* Copyright (c) 2025 Skyward Experimental Rocketry
+ * Author: Alberto Nidasio, Fabrizio Monti
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/src/shared/drivers/dma/DMA.h b/src/shared/drivers/dma/DMA.h
index c62fa1c6adfd7b8e2421bd930f940dffae836456..63ede2588ba6da57a4508bdf241c1267a8179757 100644
--- a/src/shared/drivers/dma/DMA.h
+++ b/src/shared/drivers/dma/DMA.h
@@ -1,5 +1,5 @@
-/* Copyright (c) 2023 Skyward Experimental Rocketry
- * Author: Alberto Nidasio
+/* Copyright (c) 2025 Skyward Experimental Rocketry
+ * Author: Alberto Nidasio, Fabrizio Monti
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
diff --git a/src/shared/drivers/dma/DMADefs.cpp b/src/shared/drivers/dma/DMADefs.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..176729890d0aa4f742c5c3063d63311bf97cd980
--- /dev/null
+++ b/src/shared/drivers/dma/DMADefs.cpp
@@ -0,0 +1,452 @@
+/* Copyright (c) 2025 Skyward Experimental Rocketry
+ * Author: Alberto Nidasio, Fabrizio Monti
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "DMADefs.h"
+
+namespace Boardcore
+{
+
+namespace DMADefs
+{
+
+const IRQn_Type irqNumberMapping[] = {
+ DMA1_Stream0_IRQn, DMA1_Stream1_IRQn, DMA1_Stream2_IRQn, DMA1_Stream3_IRQn,
+ DMA1_Stream4_IRQn, DMA1_Stream5_IRQn, DMA1_Stream6_IRQn, DMA1_Stream7_IRQn,
+ DMA2_Stream0_IRQn, DMA2_Stream1_IRQn, DMA2_Stream2_IRQn, DMA2_Stream3_IRQn,
+ DMA2_Stream4_IRQn, DMA2_Stream5_IRQn, DMA2_Stream6_IRQn, DMA2_Stream7_IRQn,
+};
+
+const std::multimap<Peripherals, std::pair<DMAStreamId, Channel>>
+ mapPeripherals = {
+
+#ifdef STM32F407xx
+ // MEM-TO-MEM (only dma2 can perform mem-to-mem copy)
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str1, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ // {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL0}}, // Stream currently not supported
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str5, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str7, Channel::CHANNEL0}},
+
+ // SPI
+ {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str5, Channel::CHANNEL3}},
+ // {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str2, Channel::CHANNEL3}},
+ {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str0, Channel::CHANNEL3}},
+
+ {Peripherals::PE_SPI2_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL0}},
+ // {Peripherals::PE_SPI2_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL0}}, // Stream currently not supported
+
+ {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL0}},
+
+ // UART & USART
+ {Peripherals::PE_USART1_TX,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL4}},
+ {Peripherals::PE_USART1_RX,
+ {DMAStreamId::DMA2_Str2, Channel::CHANNEL4}},
+ {Peripherals::PE_USART1_RX,
+ {DMAStreamId::DMA2_Str5, Channel::CHANNEL4}},
+
+ {Peripherals::PE_USART2_TX,
+ {DMAStreamId::DMA1_Str6, Channel::CHANNEL4}},
+ {Peripherals::PE_USART2_RX,
+ {DMAStreamId::DMA1_Str5, Channel::CHANNEL4}},
+
+ // {Peripherals::PE_USART3_TX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL4}}, // Stream currently not supported
+ {Peripherals::PE_USART3_TX,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL7}},
+ // {Peripherals::PE_USART3_RX, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL4}}, // Stream currently not supported
+
+ {Peripherals::PE_UART4_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL4}},
+ {Peripherals::PE_UART4_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL4}},
+
+ {Peripherals::PE_UART5_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL4}},
+ {Peripherals::PE_UART5_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL4}},
+
+ {Peripherals::PE_USART6_TX,
+ {DMAStreamId::DMA2_Str6, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_TX,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_RX,
+ {DMAStreamId::DMA2_Str1, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_RX,
+ {DMAStreamId::DMA2_Str2, Channel::CHANNEL5}},
+
+ // I2C
+ {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str6, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL1}},
+
+ {Peripherals::PE_I2C2_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL7}},
+ // {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+
+ {Peripherals::PE_I2C3_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL3}},
+ {Peripherals::PE_I2C3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL3}},
+
+ {Peripherals::PE_I2S2_EXT_TX,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL2}},
+ // {Peripherals::PE_I2S2_EXT_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+
+ {Peripherals::PE_I2S3_EXT_TX,
+ {DMAStreamId::DMA1_Str5, Channel::CHANNEL2}},
+ {Peripherals::PE_I2S3_EXT_RX,
+ {DMAStreamId::DMA1_Str2, Channel::CHANNEL2}},
+ {Peripherals::PE_I2S3_EXT_RX,
+ {DMAStreamId::DMA1_Str0, Channel::CHANNEL3}},
+
+ // TIMERS
+ {Peripherals::PE_TIM1_UP, {DMAStreamId::DMA2_Str5, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_TRIG,
+ {DMAStreamId::DMA2_Str0, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_TRIG,
+ {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_COM, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str1, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH4, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+
+ // {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
+ // {Peripherals::PE_TIM2_CH3, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
+
+ {Peripherals::PE_TIM3_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_TRIG,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH1, {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH2, {DMAStreamId::DMA1_Str5, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH4, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
+
+ {Peripherals::PE_TIM4_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL2}},
+ {Peripherals::PE_TIM4_CH1, {DMAStreamId::DMA1_Str0, Channel::CHANNEL2}},
+ // {Peripherals::PE_TIM4_CH2, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL2}}, // Stream currently not supported
+ {Peripherals::PE_TIM4_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL2}},
+
+ {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ {Peripherals::PE_TIM5_CH1, {DMAStreamId::DMA1_Str2, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_CH2, {DMAStreamId::DMA1_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_CH3, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+
+ // {Peripherals::PE_TIM6_UP, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+
+ {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL1}},
+ {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str4, Channel::CHANNEL1}},
+
+ {Peripherals::PE_TIM8_UP, {DMAStreamId::DMA2_Str1, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_TRIG,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_COM, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ // {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+ {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str4, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH4, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+
+ // Others
+ {Peripherals::PE_DAC1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL7}},
+ {Peripherals::PE_DAC2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL7}},
+
+ {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
+
+ {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL1}},
+ // {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str3, Channel::CHANNEL1}},
+ // // Stream currently not supported
+
+ {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str0, Channel::CHANNEL2}},
+ {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str1, Channel::CHANNEL2}},
+
+ {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str1, Channel::CHANNEL1}},
+ {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str7, Channel::CHANNEL1}},
+
+ // {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str3, Channel::CHANNEL4}},
+ // // Stream currently not supported
+ {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str6, Channel::CHANNEL4}},
+
+ {Peripherals::PE_CRYP_OUT, {DMAStreamId::DMA2_Str5, Channel::CHANNEL2}},
+ {Peripherals::PE_CRYP_IN, {DMAStreamId::DMA2_Str6, Channel::CHANNEL2}},
+
+ {Peripherals::PE_HASH_IN, {DMAStreamId::DMA2_Str7, Channel::CHANNEL2}},
+
+#endif // STM32F407xx
+
+#ifdef STM32F429xx
+
+ // MEM-TO-MEM (only dma2 can perform mem-to-mem copy)
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str1, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ // {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL0}}, // Stream currently not supported
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str5, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str7, Channel::CHANNEL0}},
+
+ // SPI
+ {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str5, Channel::CHANNEL3}},
+ // {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str2, Channel::CHANNEL3}},
+ {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str0, Channel::CHANNEL3}},
+
+ {Peripherals::PE_SPI2_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL0}},
+ // {Peripherals::PE_SPI2_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL0}}, // Stream currently not supported
+
+ {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL0}},
+
+ {Peripherals::PE_SPI4_TX, {DMAStreamId::DMA2_Str1, Channel::CHANNEL4}},
+ {Peripherals::PE_SPI4_TX, {DMAStreamId::DMA2_Str4, Channel::CHANNEL5}},
+ {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str0, Channel::CHANNEL4}},
+ {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str3, Channel::CHANNEL5}},
+
+ {Peripherals::PE_SPI5_TX, {DMAStreamId::DMA2_Str4, Channel::CHANNEL2}},
+ {Peripherals::PE_SPI5_TX, {DMAStreamId::DMA2_Str6, Channel::CHANNEL7}},
+ {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str3, Channel::CHANNEL2}},
+ {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str5, Channel::CHANNEL7}},
+
+ {Peripherals::PE_SPI6_TX, {DMAStreamId::DMA2_Str5, Channel::CHANNEL1}},
+ {Peripherals::PE_SPI6_RX, {DMAStreamId::DMA2_Str6, Channel::CHANNEL1}},
+
+ // UART & USART
+ {Peripherals::PE_USART1_TX,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL4}},
+ {Peripherals::PE_USART1_RX,
+ {DMAStreamId::DMA2_Str2, Channel::CHANNEL4}},
+ {Peripherals::PE_USART1_RX,
+ {DMAStreamId::DMA2_Str5, Channel::CHANNEL4}},
+
+ {Peripherals::PE_USART2_TX,
+ {DMAStreamId::DMA1_Str6, Channel::CHANNEL4}},
+ {Peripherals::PE_USART2_RX,
+ {DMAStreamId::DMA1_Str5, Channel::CHANNEL4}},
+
+ // {Peripherals::PE_USART3_TX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL4}}, // Stream currently not supported
+ {Peripherals::PE_USART3_TX,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL7}},
+ // {Peripherals::PE_USART3_RX, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL4}}, // Stream currently not supported
+
+ {Peripherals::PE_UART4_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL4}},
+ {Peripherals::PE_UART4_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL4}},
+
+ {Peripherals::PE_UART5_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL4}},
+ {Peripherals::PE_UART5_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL4}},
+
+ {Peripherals::PE_UART7_TX, {DMAStreamId::DMA1_Str1, Channel::CHANNEL5}},
+ {Peripherals::PE_UART7_RX, {DMAStreamId::DMA1_Str3, Channel::CHANNEL5}},
+
+ {Peripherals::PE_UART8_TX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL5}},
+ {Peripherals::PE_UART8_RX, {DMAStreamId::DMA1_Str6, Channel::CHANNEL5}},
+
+ {Peripherals::PE_USART6_TX,
+ {DMAStreamId::DMA2_Str6, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_TX,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_RX,
+ {DMAStreamId::DMA2_Str1, Channel::CHANNEL5}},
+ {Peripherals::PE_USART6_RX,
+ {DMAStreamId::DMA2_Str2, Channel::CHANNEL5}},
+
+ // I2C
+ {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str6, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL1}},
+ {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL1}},
+
+ {Peripherals::PE_I2C2_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL7}},
+ // {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+
+ {Peripherals::PE_I2C3_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL3}},
+ {Peripherals::PE_I2C3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL3}},
+
+ {Peripherals::PE_I2S2_EXT_TX,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL2}},
+ // {Peripherals::PE_I2S2_EXT_RX, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+
+ {Peripherals::PE_I2S3_EXT_TX,
+ {DMAStreamId::DMA1_Str5, Channel::CHANNEL2}},
+ {Peripherals::PE_I2S3_EXT_RX,
+ {DMAStreamId::DMA1_Str2, Channel::CHANNEL2}},
+ {Peripherals::PE_I2S3_EXT_RX,
+ {DMAStreamId::DMA1_Str0, Channel::CHANNEL3}},
+
+ // TIMERS
+ {Peripherals::PE_TIM1_UP, {DMAStreamId::DMA2_Str5, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_TRIG,
+ {DMAStreamId::DMA2_Str0, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_TRIG,
+ {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_COM, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str1, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM1_CH4, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
+
+ // {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
+ // {Peripherals::PE_TIM2_CH3, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL3}}, // Stream currently not supported
+ {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
+ {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
+
+ {Peripherals::PE_TIM3_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_TRIG,
+ {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH1, {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH2, {DMAStreamId::DMA1_Str5, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL5}},
+ {Peripherals::PE_TIM3_CH4, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
+
+ {Peripherals::PE_TIM4_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL2}},
+ {Peripherals::PE_TIM4_CH1, {DMAStreamId::DMA1_Str0, Channel::CHANNEL2}},
+ // {Peripherals::PE_TIM4_CH2, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL2}}, // Stream currently not supported
+ {Peripherals::PE_TIM4_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL2}},
+
+ {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ {Peripherals::PE_TIM5_CH1, {DMAStreamId::DMA1_Str2, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_CH2, {DMAStreamId::DMA1_Str4, Channel::CHANNEL6}},
+ {Peripherals::PE_TIM5_CH3, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
+ // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+ // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str3,
+ // Channel::CHANNEL6}}, // Stream currently not supported
+
+ // {Peripherals::PE_TIM6_UP, {DMAStreamId::DMA1_Str1,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+
+ {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL1}},
+ {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str4, Channel::CHANNEL1}},
+
+ {Peripherals::PE_TIM8_UP, {DMAStreamId::DMA2_Str1, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_TRIG,
+ {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_COM, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ // {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str3,
+ // Channel::CHANNEL7}}, // Stream currently not supported
+ {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
+ {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str4, Channel::CHANNEL7}},
+ {Peripherals::PE_TIM8_CH4, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
+
+ // Others
+ {Peripherals::PE_DAC1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL7}},
+ {Peripherals::PE_DAC2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL7}},
+
+ {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
+ {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
+
+ {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL1}},
+ // {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str3, Channel::CHANNEL1}},
+ // // Stream currently not supported
+
+ {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str0, Channel::CHANNEL2}},
+ {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str1, Channel::CHANNEL2}},
+
+ {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str1, Channel::CHANNEL0}},
+ {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str3, Channel::CHANNEL0}},
+
+ {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str5, Channel::CHANNEL0}},
+ {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str4, Channel::CHANNEL1}},
+
+ {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str1, Channel::CHANNEL1}},
+ {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str7, Channel::CHANNEL1}},
+
+ // {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str3, Channel::CHANNEL4}},
+ // // Stream currently not supported
+ {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str6, Channel::CHANNEL4}},
+
+ {Peripherals::PE_CRYP_OUT, {DMAStreamId::DMA2_Str5, Channel::CHANNEL2}},
+ {Peripherals::PE_CRYP_IN, {DMAStreamId::DMA2_Str6, Channel::CHANNEL2}},
+
+ {Peripherals::PE_HASH_IN, {DMAStreamId::DMA2_Str7, Channel::CHANNEL2}},
+
+#endif // STM32F429xx
+};
+
+} // namespace DMADefs
+
+} // namespace Boardcore
diff --git a/src/shared/drivers/dma/DMADefs.h b/src/shared/drivers/dma/DMADefs.h
index bdbca679f3b3e6437ccdbfa3f2c1a54fef2d3886..88797e8abe295b5744dc2c6dc488405a6044f8cf 100644
--- a/src/shared/drivers/dma/DMADefs.h
+++ b/src/shared/drivers/dma/DMADefs.h
@@ -1,5 +1,5 @@
/* Copyright (c) 2025 Skyward Experimental Rocketry
- * Author: Fabrizio Monti
+ * Author: Alberto Nidasio, Fabrizio Monti
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -58,18 +58,6 @@ enum class DMAStreamId : uint8_t
DMA2_Str7 = 15,
};
-/**
- * @brief Mapping between `DMAStreamId` and the corresponding irq number.
- * This is needed because irq number values are not contiguous and they are
- * architecture dependent.
- */
-const IRQn_Type irqNumberMapping[] = {
- DMA1_Stream0_IRQn, DMA1_Stream1_IRQn, DMA1_Stream2_IRQn, DMA1_Stream3_IRQn,
- DMA1_Stream4_IRQn, DMA1_Stream5_IRQn, DMA1_Stream6_IRQn, DMA1_Stream7_IRQn,
- DMA2_Stream0_IRQn, DMA2_Stream1_IRQn, DMA2_Stream2_IRQn, DMA2_Stream3_IRQn,
- DMA2_Stream4_IRQn, DMA2_Stream5_IRQn, DMA2_Stream6_IRQn, DMA2_Stream7_IRQn,
-};
-
/**
* @brief Channels selectable for each dma stream.
*/
@@ -182,245 +170,20 @@ enum class Peripherals : uint8_t
};
+/**
+ * @brief Mapping between `DMAStreamId` and the corresponding irq number.
+ * This is needed because irq number values are not contiguous and they are
+ * architecture dependent.
+ */
+extern const IRQn_Type irqNumberMapping[];
+
/**
* @brief Maps the peripherals to the dma streams (and
* the corresponding channel) that are connected with.
*/
-const std::multimap<Peripherals, std::pair<DMAStreamId, Channel>>
- mapPeripherals = {
-
- // MEM-TO-MEM (only dma2 can perform mem-to-mem copy)
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str1, Channel::CHANNEL0}},
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
- // {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL0}}, // Stream currently not supported
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str5, Channel::CHANNEL0}},
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
- {Peripherals::PE_MEM_ONLY, {DMAStreamId::DMA2_Str7, Channel::CHANNEL0}},
-
- // SPI
- {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str5, Channel::CHANNEL3}},
- // {Peripherals::PE_SPI1_TX, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL3}}, // Stream currently not supported
- {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str2, Channel::CHANNEL3}},
- {Peripherals::PE_SPI1_RX, {DMAStreamId::DMA2_Str0, Channel::CHANNEL3}},
-
- {Peripherals::PE_SPI2_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL0}},
- // {Peripherals::PE_SPI2_RX, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL0}}, // Stream currently not supported
-
- {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL0}},
- {Peripherals::PE_SPI3_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL0}},
- {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL0}},
- {Peripherals::PE_SPI3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL0}},
-
- // {Peripherals::PE_SPI4_TX, {DMAStreamId::DMA2_Str1,
- // Channel::CHANNEL4}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI4_TX, {DMAStreamId::DMA2_Str4,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str0,
- // Channel::CHANNEL4}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI4_RX, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
-
- // {Peripherals::PE_SPI5_TX, {DMAStreamId::DMA2_Str4,
- // Channel::CHANNEL2}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI5_TX, {DMAStreamId::DMA2_Str6,
- // Channel::CHANNEL7}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL2}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI5_RX, {DMAStreamId::DMA2_Str5,
- // Channel::CHANNEL7}}, // available on STM32F42xxx and STM32F43xxx only
-
- // {Peripherals::PE_SPI6_TX, {DMAStreamId::DMA2_Str5,
- // Channel::CHANNEL1}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SPI6_RX, {DMAStreamId::DMA2_Str6,
- // Channel::CHANNEL1}}, // available on STM32F42xxx and STM32F43xxx only
-
- // UART & USART
- {Peripherals::PE_USART1_TX,
- {DMAStreamId::DMA2_Str7, Channel::CHANNEL4}},
- {Peripherals::PE_USART1_RX,
- {DMAStreamId::DMA2_Str2, Channel::CHANNEL4}},
- {Peripherals::PE_USART1_RX,
- {DMAStreamId::DMA2_Str5, Channel::CHANNEL4}},
-
- {Peripherals::PE_USART2_TX,
- {DMAStreamId::DMA1_Str6, Channel::CHANNEL4}},
- {Peripherals::PE_USART2_RX,
- {DMAStreamId::DMA1_Str5, Channel::CHANNEL4}},
-
- // {Peripherals::PE_USART3_TX, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL4}}, // Stream currently not supported
- {Peripherals::PE_USART3_TX,
- {DMAStreamId::DMA1_Str4, Channel::CHANNEL7}},
- // {Peripherals::PE_USART3_RX, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL4}}, // Stream currently not supported
-
- {Peripherals::PE_UART4_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL4}},
- {Peripherals::PE_UART4_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL4}},
-
- {Peripherals::PE_UART5_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL4}},
- {Peripherals::PE_UART5_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL4}},
-
- // {Peripherals::PE_UART7_TX, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_UART7_RX, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
-
- // {Peripherals::PE_UART8_TX, {DMAStreamId::DMA1_Str0,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_UART8_RX, {DMAStreamId::DMA1_Str6,
- // Channel::CHANNEL5}}, // available on STM32F42xxx and STM32F43xxx only
-
- {Peripherals::PE_USART6_TX,
- {DMAStreamId::DMA2_Str6, Channel::CHANNEL5}},
- {Peripherals::PE_USART6_TX,
- {DMAStreamId::DMA2_Str7, Channel::CHANNEL5}},
- {Peripherals::PE_USART6_RX,
- {DMAStreamId::DMA2_Str1, Channel::CHANNEL5}},
- {Peripherals::PE_USART6_RX,
- {DMAStreamId::DMA2_Str2, Channel::CHANNEL5}},
-
- // I2C
- {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str6, Channel::CHANNEL1}},
- {Peripherals::PE_I2C1_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL1}},
- {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str0, Channel::CHANNEL1}},
- {Peripherals::PE_I2C1_RX, {DMAStreamId::DMA1_Str5, Channel::CHANNEL1}},
-
- {Peripherals::PE_I2C2_TX, {DMAStreamId::DMA1_Str7, Channel::CHANNEL7}},
- {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL7}},
- // {Peripherals::PE_I2C2_RX, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL7}}, // Stream currently not supported
-
- {Peripherals::PE_I2C3_TX, {DMAStreamId::DMA1_Str4, Channel::CHANNEL3}},
- {Peripherals::PE_I2C3_RX, {DMAStreamId::DMA1_Str2, Channel::CHANNEL3}},
-
- {Peripherals::PE_I2S2_EXT_TX,
- {DMAStreamId::DMA1_Str4, Channel::CHANNEL2}},
- // {Peripherals::PE_I2S2_EXT_RX, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL3}}, // Stream currently not supported
-
- {Peripherals::PE_I2S3_EXT_TX,
- {DMAStreamId::DMA1_Str5, Channel::CHANNEL2}},
- {Peripherals::PE_I2S3_EXT_RX,
- {DMAStreamId::DMA1_Str2, Channel::CHANNEL2}},
- {Peripherals::PE_I2S3_EXT_RX,
- {DMAStreamId::DMA1_Str0, Channel::CHANNEL3}},
-
- // TIMERS
- {Peripherals::PE_TIM1_UP, {DMAStreamId::DMA2_Str5, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_TRIG,
- {DMAStreamId::DMA2_Str0, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_TRIG,
- {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_COM, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
- {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str1, Channel::CHANNEL6}},
- // {Peripherals::PE_TIM1_CH1, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL6}}, // Stream currently not supported
- {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
- {Peripherals::PE_TIM1_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL0}},
- {Peripherals::PE_TIM1_CH3, {DMAStreamId::DMA2_Str6, Channel::CHANNEL6}},
- {Peripherals::PE_TIM1_CH4, {DMAStreamId::DMA2_Str4, Channel::CHANNEL6}},
-
- // {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL3}}, // Stream currently not supported
- {Peripherals::PE_TIM2_UP, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
- {Peripherals::PE_TIM2_CH1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL3}},
- {Peripherals::PE_TIM2_CH2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
- // {Peripherals::PE_TIM2_CH3, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL3}}, // Stream currently not supported
- {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str6, Channel::CHANNEL3}},
- {Peripherals::PE_TIM2_CH4, {DMAStreamId::DMA1_Str7, Channel::CHANNEL3}},
-
- {Peripherals::PE_TIM3_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
- {Peripherals::PE_TIM3_TRIG,
- {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
- {Peripherals::PE_TIM3_CH1, {DMAStreamId::DMA1_Str4, Channel::CHANNEL5}},
- {Peripherals::PE_TIM3_CH2, {DMAStreamId::DMA1_Str5, Channel::CHANNEL5}},
- {Peripherals::PE_TIM3_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL5}},
- {Peripherals::PE_TIM3_CH4, {DMAStreamId::DMA1_Str2, Channel::CHANNEL5}},
-
- {Peripherals::PE_TIM4_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL2}},
- {Peripherals::PE_TIM4_CH1, {DMAStreamId::DMA1_Str0, Channel::CHANNEL2}},
- // {Peripherals::PE_TIM4_CH2, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL2}}, // Stream currently not supported
- {Peripherals::PE_TIM4_CH3, {DMAStreamId::DMA1_Str7, Channel::CHANNEL2}},
-
- {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
- {Peripherals::PE_TIM5_UP, {DMAStreamId::DMA1_Str6, Channel::CHANNEL6}},
- // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL6}}, // Stream currently not supported
- // {Peripherals::PE_TIM5_TRIG, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL6}}, // Stream currently not supported
- {Peripherals::PE_TIM5_CH1, {DMAStreamId::DMA1_Str2, Channel::CHANNEL6}},
- {Peripherals::PE_TIM5_CH2, {DMAStreamId::DMA1_Str4, Channel::CHANNEL6}},
- {Peripherals::PE_TIM5_CH3, {DMAStreamId::DMA1_Str0, Channel::CHANNEL6}},
- // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL6}}, // Stream currently not supported
- // {Peripherals::PE_TIM5_CH4, {DMAStreamId::DMA1_Str3,
- // Channel::CHANNEL6}}, // Stream currently not supported
-
- // {Peripherals::PE_TIM6_UP, {DMAStreamId::DMA1_Str1,
- // Channel::CHANNEL7}}, // Stream currently not supported
-
- {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str2, Channel::CHANNEL1}},
- {Peripherals::PE_TIM7_UP, {DMAStreamId::DMA1_Str4, Channel::CHANNEL1}},
-
- {Peripherals::PE_TIM8_UP, {DMAStreamId::DMA2_Str1, Channel::CHANNEL7}},
- {Peripherals::PE_TIM8_TRIG,
- {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
- {Peripherals::PE_TIM8_COM, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
- {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
- {Peripherals::PE_TIM8_CH1, {DMAStreamId::DMA2_Str2, Channel::CHANNEL7}},
- {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
- // {Peripherals::PE_TIM8_CH2, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL7}}, // Stream currently not supported
- {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str2, Channel::CHANNEL0}},
- {Peripherals::PE_TIM8_CH3, {DMAStreamId::DMA2_Str4, Channel::CHANNEL7}},
- {Peripherals::PE_TIM8_CH4, {DMAStreamId::DMA2_Str7, Channel::CHANNEL7}},
-
- // Others
- {Peripherals::PE_DAC1, {DMAStreamId::DMA1_Str5, Channel::CHANNEL7}},
- {Peripherals::PE_DAC2, {DMAStreamId::DMA1_Str6, Channel::CHANNEL7}},
-
- {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str0, Channel::CHANNEL0}},
- {Peripherals::PE_ADC1, {DMAStreamId::DMA2_Str4, Channel::CHANNEL0}},
-
- {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str2, Channel::CHANNEL1}},
- // {Peripherals::PE_ADC2, {DMAStreamId::DMA2_Str3, Channel::CHANNEL1}},
- // // Stream currently not supported
-
- {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str0, Channel::CHANNEL2}},
- {Peripherals::PE_ADC3, {DMAStreamId::DMA2_Str1, Channel::CHANNEL2}},
-
- // {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str1,
- // Channel::CHANNEL0}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SAI1_A, {DMAStreamId::DMA2_Str3,
- // Channel::CHANNEL0}}, // available on STM32F42xxx and STM32F43xxx only
-
- // {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str5,
- // Channel::CHANNEL0}}, // available on STM32F42xxx and STM32F43xxx only
- // {Peripherals::PE_SAI1_B, {DMAStreamId::DMA2_Str4,
- // Channel::CHANNEL1}}, // available on STM32F42xxx and STM32F43xxx only
-
- {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str1, Channel::CHANNEL1}},
- {Peripherals::PE_DCMI, {DMAStreamId::DMA2_Str7, Channel::CHANNEL1}},
-
- // {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str3, Channel::CHANNEL4}},
- // // Stream currently not supported
- {Peripherals::PE_SDIO, {DMAStreamId::DMA2_Str6, Channel::CHANNEL4}},
-
- {Peripherals::PE_CRYP_OUT, {DMAStreamId::DMA2_Str5, Channel::CHANNEL2}},
- {Peripherals::PE_CRYP_IN, {DMAStreamId::DMA2_Str6, Channel::CHANNEL2}},
-
- {Peripherals::PE_HASH_IN, {DMAStreamId::DMA2_Str7, Channel::CHANNEL2}},
-};
+extern const std::multimap<Peripherals, std::pair<DMAStreamId, Channel>>
+ mapPeripherals;
} // namespace DMADefs
-} // namespace Boardcore
\ No newline at end of file
+} // namespace Boardcore
diff --git a/src/shared/drivers/dma/DMAStream.h b/src/shared/drivers/dma/DMAStream.h
deleted file mode 100644
index ad3fd03b853712dfab297e91e9fbee8d9cdd970b..0000000000000000000000000000000000000000
--- a/src/shared/drivers/dma/DMAStream.h
+++ /dev/null
@@ -1,510 +0,0 @@
-/* Copyright (c) 2021 Skyward Experimental Rocketry
- * Author: Alberto Nidasio
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <diagnostic/PrintLogger.h>
-#include <interfaces/arch_registers.h>
-
-namespace Boardcore
-{
-
-/**
- * @brief Driver for STM32 DMA streams.
- *
- * Direct Memory Access is used in order to provide high-speed data transfer
- * between peripherals and memory and betweeen memory and memory. Data can be
- * quickly moved by DMA without any CPU interacion.
- *
- * The STM32F4 family features two DMA controller, each with 8 streams.
- *
- * DMA features are:
- * - Four-word depth 32 FIFO memory buffers per stream, that can be used in FIFO
- * mode or direct mode
- * - Double buffering
- * - Software programmable piorities between DMA stream requests (4 levels)
- * - The number of data items to be transferred can be managed either by the DMA
- * controller or by the peripheral:
- * - DMA flow controller: the number of data items to be transferred is
- * software-programmable form 1 to 65535
- * - Peripheral flow controller: the number of data items to be transferred is
- * unknown and controlled by the source or the destination peripheral that
- * signals the end of the transfer by hardware
- * - Incrementing or non incrementing adressing for source and destination
- * - Circular buffer management
- *
- * Note that only DMA2 controller can perform memory-to-memory transactions.
- *
- * Each DMA transfer consists of three operations:
- * - A loading from the peripheral data register or a location in memory
- * - A storage of the data loaded to the peripheral data register or a location
- * in memory
- * - A post-decrement of the counter of transeffer data items (NDTR)
- *
- * After an event, the peripheral sends a request signal to the DMA controller.
- * The DMA controller serves the request depending on the channel priorities. As
- * soon as the DMA controller accesses the peripheral, an acknowledge signal is
- * sent to the peripheral by the DMA controller. The peripheral releases its
- * request as soon as it gets the acknowledge signal.
- *
- * Each stream is associated with a DMA request that can be selected out of 8
- * possible channel requests.
- *
- * Note that configuration functions have effect only if the stream is disabled.
- */
-class DMAStream
-{
-public:
- enum class Channel : uint32_t
- {
- CHANNEL0 = 0,
- CHANNEL1 = DMA_SxCR_CHSEL_0,
- CHANNEL2 = DMA_SxCR_CHSEL_1,
- CHANNEL3 = DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0,
- CHANNEL4 = DMA_SxCR_CHSEL_2,
- CHANNEL5 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0,
- CHANNEL6 = DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1,
- CHANNEL7 = DMA_SxCR_CHSEL,
- };
-
- enum class MemoryBurstConfiguration : uint32_t
- {
- SINGLE_TRANSFER = 0,
- INCR4 = DMA_SxCR_MBURST_0,
- INCR8 = DMA_SxCR_MBURST_1,
- INCR16 = DMA_SxCR_MBURST,
- };
-
- enum class PeripheralBurstConfiguration : uint32_t
- {
- SINGLE_TRANSFER = 0,
- INCR4 = DMA_SxCR_PBURST_0,
- INCR8 = DMA_SxCR_PBURST_1,
- INCR16 = DMA_SxCR_PBURST,
- };
-
- enum class PriorityLevel : uint32_t
- {
- LOW = 0,
- MEDIUM = DMA_SxCR_PL_0,
- HIGH = DMA_SxCR_PL_1,
- VERY_HIGH = DMA_SxCR_PL,
- };
-
- enum class MemoryDataSize : uint32_t
- {
- BYTE = 0,
- HALF_WORD = DMA_SxCR_MSIZE_0,
- WORD = DMA_SxCR_MSIZE_1
- };
-
- enum class PeripheralDataSize : uint32_t
- {
- BYTE = 0,
- HALF_WORD = DMA_SxCR_PSIZE_0,
- WORD = DMA_SxCR_PSIZE_1
- };
-
- enum class DataTransferDirection : uint32_t
- {
- PERIPH_TO_MEM = 0,
- MEM_TO_PERIPH = DMA_SxCR_DIR_0,
- MEM_TO_MEM = DMA_SxCR_DIR_1,
- };
-
- DMAStream(DMA_Stream_TypeDef* dmaStream);
-
- DMA_TypeDef* getController();
-
- DMA_Stream_TypeDef* getStream();
-
- void reset();
-
- void enable();
-
- void disable();
-
- void setStreamChannel(Channel channel);
-
- void setStreamMemoryBurstConfiguration(MemoryBurstConfiguration config);
-
- void setStreamPeripheralBurstConfiguration(
- PeripheralBurstConfiguration config);
-
- void enableDoubleBufferMode();
-
- void disableDoubleBufferMode();
-
- void setStreamPriorityLevel(PriorityLevel priorityLevel);
-
- void setMemoryDataSize(MemoryDataSize size);
-
- void setPeripheralDataSize(PeripheralDataSize size);
-
- void enableMemoryIncrement();
-
- void disableMemoryIncrement();
-
- void enablePeripheralIncrement();
-
- void disablePeripheralIncrement();
-
- void enableCircularMode();
-
- void disableCircularMode();
-
- void setDataTransferDirection(DataTransferDirection direction);
-
- void setPeripheralFlowController();
-
- void setDMAFlowController();
-
- void disableTransferCompleteInterrupt();
-
- void enableTransferCompleteInterrupt();
-
- void enableHalfTransferCompleteInterrupt();
-
- void disableHalfTransferCompleteInterrupt();
-
- void enableTransferErrorInterrupt();
-
- void disableTransferErrorInterrupt();
-
- void enableDirectModeErrorInterrupt();
-
- void disableDirectModeErrorInterrupt();
-
- /**
- * @brief Sets the number of data items to transfer.
- *
- * The NDTR register decrements after each DMA transfer. Once the transfer
- * has completed, this register can either stay at zero (when the stream is
- * in normal mode) or be reloaded automatically with the previusly
- * programmed value in the following cases:
- * - When the stream is configure in circular mode
- * - When the stream is enabled again (by setting EN bit to 1)
- * If the value of the NDTR register is zero, no transaction can be served
- * even if the stream is enabled.
- */
- void setNumberOfDataItems(uint16_t numberOfDataItems);
-
- uint16_t readNumberOfDataItems();
-
- void setPeripheralAddress(uint32_t* address);
-
- void setMemory0Address(uint32_t* address);
-
- /**
- * @brief Sets the memory address used only in double buffer mode.
- */
- void setMemory1Address(uint32_t* address);
-
- void clearStatusRegister();
-
-private:
- DMA_TypeDef* dmaController;
- DMA_Stream_TypeDef* dmaStream;
-
- // Interrupt status flags
- volatile uint32_t* IFCR; ///< Interrupt flags clear register
- uint32_t IFCR_MASK; ///< Clear mask for all interrupt flags
-
- PrintLogger logger = Logging::getLogger("DMAStream");
-};
-
-inline DMAStream::DMAStream(DMA_Stream_TypeDef* dmaStream)
- : dmaStream(dmaStream)
-{
- // Find the correct DMA controller
- if (reinterpret_cast<uint32_t*>(dmaStream) < &(DMA2->LISR))
- dmaController = DMA1;
- else
- dmaController = DMA2;
-
- // Find the corret interrupt flags clear register
- if (dmaController == DMA1)
- if (dmaStream <= DMA1_Stream3)
- IFCR = &(DMA1->LIFCR);
- else
- IFCR = &(DMA1->HIFCR);
- else if (dmaStream <= DMA2_Stream3)
- IFCR = &(DMA2->LIFCR);
- else
- IFCR = &(DMA2->HIFCR);
-
- // Find the correct clear mask
- if (dmaStream == DMA1_Stream0 || dmaStream == DMA2_Stream0)
- {
- IFCR_MASK = DMA_LIFCR_CFEIF0 | DMA_LIFCR_CHTIF0 | DMA_LIFCR_CTCIF0 |
- DMA_LIFCR_CTEIF0 | DMA_LIFCR_CDMEIF0;
- }
- else if (dmaStream == DMA1_Stream1 || dmaStream == DMA2_Stream1)
- {
- IFCR_MASK = DMA_LIFCR_CFEIF1 | DMA_LIFCR_CHTIF1 | DMA_LIFCR_CTCIF1 |
- DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1;
- }
- else if (dmaStream == DMA1_Stream2 || dmaStream == DMA2_Stream2)
- {
- IFCR_MASK = DMA_LIFCR_CFEIF2 | DMA_LIFCR_CHTIF2 | DMA_LIFCR_CTCIF2 |
- DMA_LIFCR_CTEIF2 | DMA_LIFCR_CDMEIF2;
- }
- else if (dmaStream == DMA1_Stream3 || dmaStream == DMA2_Stream3)
- {
- IFCR_MASK = DMA_LIFCR_CFEIF3 | DMA_LIFCR_CHTIF3 | DMA_LIFCR_CTCIF3 |
- DMA_LIFCR_CTEIF3 | DMA_LIFCR_CDMEIF3;
- }
- else if (dmaStream == DMA1_Stream4 || dmaStream == DMA2_Stream4)
- {
- IFCR_MASK = DMA_HIFCR_CFEIF4 | DMA_HIFCR_CHTIF4 | DMA_HIFCR_CTCIF4 |
- DMA_HIFCR_CTEIF4 | DMA_HIFCR_CDMEIF4;
- }
- else if (dmaStream == DMA1_Stream5 || dmaStream == DMA2_Stream5)
- {
- IFCR_MASK = DMA_HIFCR_CFEIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTCIF5 |
- DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5;
- }
- else if (dmaStream == DMA1_Stream6 || dmaStream == DMA2_Stream6)
- {
- IFCR_MASK = DMA_HIFCR_CFEIF6 | DMA_HIFCR_CHTIF6 | DMA_HIFCR_CTCIF6 |
- DMA_HIFCR_CTEIF6 | DMA_HIFCR_CDMEIF6;
- }
- else if (dmaStream == DMA1_Stream7 || dmaStream == DMA2_Stream7)
- {
- IFCR_MASK = DMA_HIFCR_CFEIF7 | DMA_HIFCR_CHTIF7 | DMA_HIFCR_CTCIF7 |
- DMA_HIFCR_CTEIF7 | DMA_HIFCR_CDMEIF7;
- }
- else
- {
- IFCR_MASK = 0;
- LOG_CRIT(logger, "Could not recognize DMA stream");
- }
-}
-
-inline DMA_TypeDef* DMAStream::getController() { return dmaController; }
-
-inline DMA_Stream_TypeDef* DMAStream::getStream() { return dmaStream; }
-
-inline void DMAStream::reset()
-{
- // Disable stream
- dmaStream->CR &= ~DMA_SxCR_EN;
-
- // Wait for the stream to be disabled
- while (dmaStream->CR & DMA_SxCR_EN)
- ;
-
- // Clear the registers
- dmaStream->CR = 0;
- dmaStream->FCR = 0;
- clearStatusRegister();
-
- // Wait for the stream to be disabled
- while (dmaStream->CR & DMA_SxCR_EN)
- ;
-}
-
-inline void DMAStream::enable()
-{
- // Before enabling the stream ensures all status flags are cleared
- clearStatusRegister();
-
- // Enable the stream
- dmaStream->CR |= DMA_SxCR_EN;
-}
-
-inline void DMAStream::disable() { dmaStream->CR &= ~DMA_SxCR_EN; }
-
-inline void DMAStream::setStreamChannel(Channel channel)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_CHSEL;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(channel);
-}
-
-inline void DMAStream::setStreamMemoryBurstConfiguration(
- MemoryBurstConfiguration config)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_MBURST;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(config);
-}
-
-inline void DMAStream::setStreamPeripheralBurstConfiguration(
- PeripheralBurstConfiguration config)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_PBURST;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(config);
-}
-
-inline void DMAStream::enableDoubleBufferMode()
-{
- dmaStream->CR |= DMA_SxCR_DBM;
-}
-
-inline void DMAStream::disableDoubleBufferMode()
-{
- dmaStream->CR &= ~DMA_SxCR_DBM;
-}
-
-inline void DMAStream::setStreamPriorityLevel(PriorityLevel priorityLevel)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_PL;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(priorityLevel);
-}
-
-inline void DMAStream::setMemoryDataSize(MemoryDataSize size)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_MSIZE;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(size);
-}
-
-inline void DMAStream::setPeripheralDataSize(PeripheralDataSize size)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_PSIZE;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(size);
-}
-
-inline void DMAStream::enableMemoryIncrement()
-{
- dmaStream->CR |= DMA_SxCR_MINC;
-}
-
-inline void DMAStream::disableMemoryIncrement()
-{
- dmaStream->CR &= ~DMA_SxCR_MINC;
-}
-
-inline void DMAStream::enablePeripheralIncrement()
-{
- dmaStream->CR |= DMA_SxCR_PINC;
-}
-
-inline void DMAStream::disablePeripheralIncrement()
-{
- dmaStream->CR &= ~DMA_SxCR_PINC;
-}
-
-inline void DMAStream::enableCircularMode() { dmaStream->CR |= DMA_SxCR_CIRC; }
-
-inline void DMAStream::disableCircularMode() { dmaStream->CR |= DMA_SxCR_CIRC; }
-
-inline void DMAStream::setDataTransferDirection(DataTransferDirection direction)
-{
- // First clear the configuration
- dmaStream->CR &= ~DMA_SxCR_DIR;
-
- // Set the new value
- dmaStream->CR |= static_cast<uint32_t>(direction);
-}
-
-inline void DMAStream::setPeripheralFlowController()
-{
- dmaStream->CR |= DMA_SxCR_PFCTRL;
-}
-
-inline void DMAStream::setDMAFlowController()
-{
- dmaStream->CR &= ~DMA_SxCR_PFCTRL;
-}
-
-inline void DMAStream::enableTransferCompleteInterrupt()
-{
- dmaStream->CR |= DMA_SxCR_TCIE;
-}
-
-inline void DMAStream::disableTransferCompleteInterrupt()
-{
- dmaStream->CR &= ~DMA_SxCR_TCIE;
-}
-
-inline void DMAStream::enableHalfTransferCompleteInterrupt()
-{
- dmaStream->CR |= DMA_SxCR_HTIE;
-}
-
-inline void DMAStream::disableHalfTransferCompleteInterrupt()
-{
- dmaStream->CR &= ~DMA_SxCR_HTIE;
-}
-
-inline void DMAStream::enableTransferErrorInterrupt()
-{
- dmaStream->CR |= DMA_SxCR_TEIE;
-}
-
-inline void DMAStream::disableTransferErrorInterrupt()
-{
- dmaStream->CR &= ~DMA_SxCR_TEIE;
-}
-
-inline void DMAStream::enableDirectModeErrorInterrupt()
-{
- dmaStream->CR |= DMA_SxCR_DMEIE;
-}
-
-inline void DMAStream::disableDirectModeErrorInterrupt()
-{
- dmaStream->CR &= ~DMA_SxCR_DMEIE;
-}
-
-inline void DMAStream::setNumberOfDataItems(uint16_t numberOfDataItems)
-{
- dmaStream->NDTR = numberOfDataItems;
-}
-
-inline uint16_t DMAStream::readNumberOfDataItems() { return dmaStream->NDTR; }
-
-inline void DMAStream::setPeripheralAddress(uint32_t* address)
-{
- dmaStream->PAR = reinterpret_cast<uint32_t>(address);
-}
-
-inline void DMAStream::setMemory0Address(uint32_t* address)
-{
- dmaStream->M0AR = reinterpret_cast<uint32_t>(address);
-}
-
-inline void DMAStream::setMemory1Address(uint32_t* address)
-{
- dmaStream->M1AR = reinterpret_cast<uint32_t>(address);
-}
-
-inline void DMAStream::clearStatusRegister() { *IFCR |= IFCR_MASK; }
-
-} // namespace Boardcore
diff --git a/src/tests/drivers/test-dma-mem-to-mem.cpp b/src/tests/drivers/test-dma-mem-to-mem.cpp
index 7109a1e3d2bb5bc558edbd3519cb320c286e6282..7807b8810b09418db111c7a12e3d9f40ad833e70 100644
--- a/src/tests/drivers/test-dma-mem-to-mem.cpp
+++ b/src/tests/drivers/test-dma-mem-to-mem.cpp
@@ -1,5 +1,5 @@
-/* Copyright (c) 2023 Skyward Experimental Rocketry
- * Authors: Alberto Nidasio
+/* Copyright (c) 2025 Skyward Experimental Rocketry
+ * Authors: Alberto Nidasio, Fabrizio Monti
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal