diff --git a/libs/mxgui b/libs/mxgui
index bf9ef728fbe5f6df084120bdbde51c335951ac48..3ce4e0588633ead6328e65b1e711ea39375a805e 160000
--- a/libs/mxgui
+++ b/libs/mxgui
@@ -1 +1 @@
-Subproject commit bf9ef728fbe5f6df084120bdbde51c335951ac48
+Subproject commit 3ce4e0588633ead6328e65b1e711ea39375a805e
diff --git a/src/shared/utils/ClockUtils.h b/src/shared/utils/ClockUtils.h
index 3d671d9f48311aae9bae40d24b5f022e6d9d8e8e..addbdafb8c0bc54895f75fea3f8cb7294c257274 100644
--- a/src/shared/utils/ClockUtils.h
+++ b/src/shared/utils/ClockUtils.h
@@ -79,7 +79,7 @@ inline uint32_t ClockUtils::getAPBFrequency(APB bus)
         // The position of the PPRE1 bit in RCC->CFGR is different in some stm32
 #ifdef _ARCH_CORTEXM3_STM32
         const uint32_t ppre1 = 8;
-#elif _ARCH_CORTEXM4_STM32F4
+#elif _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM3_STM32F2
         const uint32_t ppre1 = 10;
 #else
 #error "Architecture not supported by TimerUtils"
@@ -95,7 +95,7 @@ inline uint32_t ClockUtils::getAPBFrequency(APB bus)
         // The position of the PPRE2 bit in RCC->CFGR is different in some stm32
 #ifdef _ARCH_CORTEXM3_STM32
         const uint32_t ppre2 = 11;
-#elif _ARCH_CORTEXM4_STM32F4
+#elif _ARCH_CORTEXM4_STM32F4 | _ARCH_CORTEXM3_STM32F2
         const uint32_t ppre2 = 13;
 #else
 #error "Architecture not supported by TimerUtils"
@@ -159,9 +159,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
             case BKPSRAM_BASE:
                 RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
                 break;
+#ifndef _ARCH_CORTEXM3_STM32F2
             case CCMDATARAM_BASE:
                 RCC->AHB1ENR |= RCC_AHB1ENR_CCMDATARAMEN;
                 break;
+#endif
             case DMA1_BASE:
                 RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
                 break;
@@ -173,9 +175,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
                 RCC->AHB1ENR |= RCC_AHB1ENR_DMA2DEN;
                 break;
 #endif
+#ifndef _ARCH_CORTEXM3_STM32F2
             case ETH_MAC_BASE:
                 RCC->AHB1ENR |= RCC_AHB1ENR_ETHMACEN;
                 break;
+#endif
             case USB_OTG_HS_PERIPH_BASE:
                 RCC->AHB1ENR |= RCC_AHB1ENR_OTGHSEN;
                 break;
@@ -183,9 +187,11 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
 
         // AHB2 peripherals
         {
+#ifndef _ARCH_CORTEXM3_STM32F2
             case DCMI_BASE:
                 RCC->AHB2ENR |= RCC_AHB2ENR_DCMIEN;
                 break;
+#endif
             case RNG_BASE:
                 RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
                 break;
@@ -395,9 +401,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral)
             case BKPSRAM_BASE:
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN;
                 break;
+#ifndef _ARCH_CORTEXM3_STM32F2
             case CCMDATARAM_BASE:
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_CCMDATARAMEN;
                 break;
+#endif
             case DMA1_BASE:
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA1EN;
                 break;
@@ -409,9 +417,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral)
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_DMA2DEN;
                 break;
 #endif
+#ifndef _ARCH_CORTEXM3_STM32F2
             case ETH_MAC_BASE:
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_ETHMACEN;
                 break;
+#endif
             case USB_OTG_HS_PERIPH_BASE:
                 RCC->AHB1ENR &= ~RCC_AHB1ENR_OTGHSEN;
                 break;
@@ -419,9 +429,11 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral)
 
         // AHB2 peripherals
         {
+#ifndef _ARCH_CORTEXM3_STM32F2
             case DCMI_BASE:
                 RCC->AHB2ENR &= ~RCC_AHB2ENR_DCMIEN;
                 break;
+#endif
             case RNG_BASE:
                 RCC->AHB2ENR &= ~RCC_AHB2ENR_RNGEN;
                 break;