diff --git a/.idea/.gitignore b/.idea/.gitignore
deleted file mode 100644
index 73f69e0958611ac6e00bde95641f6699030ad235..0000000000000000000000000000000000000000
--- a/.idea/.gitignore
+++ /dev/null
@@ -1,8 +0,0 @@
-# Default ignored files
-/shelf/
-/workspace.xml
-# Datasource local storage ignored files
-/dataSources/
-/dataSources.local.xml
-# Editor-based HTTP Client requests
-/httpRequests/
diff --git a/.idea/.name b/.idea/.name
deleted file mode 100644
index e3612db561986620a2f96b7ede6acdc269e32011..0000000000000000000000000000000000000000
--- a/.idea/.name
+++ /dev/null
@@ -1 +0,0 @@
-SkywardBoardcore
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
deleted file mode 100644
index e7d1117d2b21bbf39c6a4c4de712a7e81dfe36af..0000000000000000000000000000000000000000
--- a/.idea/cmake.xml
+++ /dev/null
@@ -1,9 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
- <component name="CMakeSharedSettings">
- <configurations>
- <configuration PROFILE_NAME="Debug" ENABLED="true" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache -DCMAKE_TOOLCHAIN_FILE=$CMakeProjectDir$/libs/miosix-kernel/miosix/_tools/toolchain.cmake -GNinja" />
- <configuration PROFILE_NAME="Release" ENABLED="true" CONFIG_NAME="Release" GENERATION_OPTIONS="-DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache -DCMAKE_TOOLCHAIN_FILE=$CMakeProjectDir$/libs/miosix-kernel/miosix/_tools/toolchain.cmake -GNinja" />
- </configurations>
- </component>
-</project>
diff --git a/.idea/codeStyles/Project.xml b/.idea/codeStyles/Project.xml
deleted file mode 100644
index c8f84c3534495485e6264ba5b723b469a07d689c..0000000000000000000000000000000000000000
--- a/.idea/codeStyles/Project.xml
+++ /dev/null
@@ -1,7 +0,0 @@
-<component name="ProjectCodeStyleConfiguration">
- <code_scheme name="Project" version="173">
- <clangFormatSettings>
- <option name="ENABLED" value="true" />
- </clangFormatSettings>
- </code_scheme>
-</component>
diff --git a/.idea/codeStyles/codeStyleConfig.xml b/.idea/codeStyles/codeStyleConfig.xml
deleted file mode 100644
index 0f7bc519db610a2e6290d61d592e9fdac90c8cde..0000000000000000000000000000000000000000
--- a/.idea/codeStyles/codeStyleConfig.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<component name="ProjectCodeStyleConfiguration">
- <state>
- <option name="USE_PER_PROJECT_SETTINGS" value="true" />
- </state>
-</component>
diff --git a/.idea/misc.xml b/.idea/misc.xml
deleted file mode 100644
index 48114834858e9d1f2cdb249f0bd14a39f6d05a29..0000000000000000000000000000000000000000
--- a/.idea/misc.xml
+++ /dev/null
@@ -1,13 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
- <component name="CMakeWorkspace" PROJECT_DIR="$PROJECT_DIR$" />
- <component name="CidrRootsConfiguration">
- <sourceRoots>
- <file path="$PROJECT_DIR$/src" />
- </sourceRoots>
- <excludeRoots>
- <file path="$PROJECT_DIR$/build" />
- <file path="$PROJECT_DIR$/libs" />
- </excludeRoots>
- </component>
-</project>
diff --git a/.idea/modules.xml b/.idea/modules.xml
deleted file mode 100644
index 661190e704ce2747abc8820df2bacd7e2a5498f3..0000000000000000000000000000000000000000
--- a/.idea/modules.xml
+++ /dev/null
@@ -1,8 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
- <component name="ProjectModuleManager">
- <modules>
- <module fileurl="file://$PROJECT_DIR$/.idea/skyward-boardcore.iml" filepath="$PROJECT_DIR$/.idea/skyward-boardcore.iml" />
- </modules>
- </component>
-</project>
diff --git a/.idea/skyward-boardcore.iml b/.idea/skyward-boardcore.iml
deleted file mode 100644
index 8afe22e01d18c67c07eeaae0128209012f347937..0000000000000000000000000000000000000000
--- a/.idea/skyward-boardcore.iml
+++ /dev/null
@@ -1,2 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<module classpath="CMake" type="CPP_MODULE" version="4" />
diff --git a/.idea/vcs.xml b/.idea/vcs.xml
deleted file mode 100644
index da9f74d6e37609a3bb73e3560e44e2beec899c96..0000000000000000000000000000000000000000
--- a/.idea/vcs.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project version="4">
- <component name="VcsDirectoryMappings">
- <mapping directory="$PROJECT_DIR$" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/Catch2" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/eigen" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/fmt" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/mavlink_skyward_lib" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/miosix-kernel" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/miosix-kernel/miosix/_examples/datalogger/tscpp" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/mxgui" vcs="Git" />
- <mapping directory="$PROJECT_DIR$/libs/tscpp" vcs="Git" />
- </component>
-</project>
diff --git a/data/fault_list.csv b/data/fault_list.csv
deleted file mode 100644
index aff4f3d879cf4618d98f3174d8edcd44bb5d33f6..0000000000000000000000000000000000000000
--- a/data/fault_list.csv
+++ /dev/null
@@ -1,2 +0,0 @@
-"Category","Name (letters,numbers,underscores,NO SPACES, all caps!)","Description","Generated Name(autogenerated column!)"
-"ANAKIN","TEST_FAULT","This fault is for testing","F_ANAKIN_TEST_FAULT"
diff --git a/data/gdb/stm32f4-stlinv2.cfg b/data/gdb/stm32f4-stlinv2.cfg
deleted file mode 100644
index dae3992fe332fc448d931bfd42127b07aaf699b2..0000000000000000000000000000000000000000
--- a/data/gdb/stm32f4-stlinv2.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
-# http://www.st.com/internet/evalboard/product/252419.jsp
-
-source [find interface/stlink-v2-1.cfg]
-
-source [find target/stm32f4x.cfg]
-
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
diff --git a/data/gdb/stm32f7-stlinv2.cfg b/data/gdb/stm32f7-stlinv2.cfg
deleted file mode 100644
index 3be1bf3d82a99f997e27888c5ed73cce6a3ce8e2..0000000000000000000000000000000000000000
--- a/data/gdb/stm32f7-stlinv2.cfg
+++ /dev/null
@@ -1,9 +0,0 @@
-# This is an STM32F7 discovery board with a single STM32F407VGT6 chip.
-# http://www.st.com/internet/evalboard/product/252419.jsp
-
-source [find interface/stlink-v2-1.cfg]
-
-source [find target/stm32f7x.cfg]
-
-# use hardware reset, connect under reset
-reset_config srst_only srst_nogate
diff --git a/data/gdb/stm32f750.svd b/data/gdb/stm32f750.svd
deleted file mode 100644
index bc698fc0d203d7316e5ba916942a48241c2d183d..0000000000000000000000000000000000000000
--- a/data/gdb/stm32f750.svd
+++ /dev/null
@@ -1,68098 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<device xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_1.xsd">
- <name>STM32F750</name>
- <version>1.3</version>
- <description>STM32F750</description>
- <cpu>
- <name>CM7</name>
- <revision>r0p1</revision>
- <endian>little</endian>
- <mpuPresent>true</mpuPresent>
- <fpuPresent>true</fpuPresent>
- <nvicPrioBits>4</nvicPrioBits>
- <vendorSystickConfig>false</vendorSystickConfig>
- </cpu>
- <!--Bus Interface Properties-->
- <!--Cortex-M3 is byte addressable-->
- <addressUnitBits>8</addressUnitBits>
- <!--the maximum data bit width accessible within a single transfer-->
- <width>32</width>
- <!--Register Default Properties-->
- <size>0x20</size>
- <resetValue>0x0</resetValue>
- <resetMask>0xFFFFFFFF</resetMask>
- <peripherals>
- <peripheral>
- <name>RNG</name>
- <description>Random number generator</description>
- <groupName>RNG</groupName>
- <baseAddress>0x50060800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>HASH_RNG</name>
- <description>Hash and Rng global interrupt</description>
- <value>80</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IE</name>
- <description>Interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RNGEN</name>
- <description>Random number generator enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SEIS</name>
- <description>Seed error interrupt status</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CEIS</name>
- <description>Clock error interrupt status</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SECS</name>
- <description>Seed error current status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CECS</name>
- <description>Clock error current status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DRDY</name>
- <description>Data ready</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>data register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RNDATA</name>
- <description>Random data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>HASH</name>
- <description>Hash processor</description>
- <groupName>HASH</groupName>
- <baseAddress>0x50060400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INIT</name>
- <description>Initialize message digest calculation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>DMAE</name>
- <description>DMA enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DATATYPE</name>
- <description>Data type selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MODE</name>
- <description>Mode selection</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALGO0</name>
- <description>Algorithm selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NBW</name>
- <description>Number of words already pushed</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DINNE</name>
- <description>DIN not empty</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MDMAT</name>
- <description>Multiple DMA Transfers</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LKEY</name>
- <description>Long key selection</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALGO1</name>
- <description>ALGO</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DIN</name>
- <displayName>DIN</displayName>
- <description>data input register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATAIN</name>
- <description>Data input</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>STR</name>
- <displayName>STR</displayName>
- <description>start register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DCAL</name>
- <description>Digest calculation</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>NBLW</name>
- <description>Number of valid bits in the last word of the message</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>HR0</name>
- <displayName>HR0</displayName>
- <description>digest registers</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H0</name>
- <description>H0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HR1</name>
- <displayName>HR1</displayName>
- <description>digest registers</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H1</name>
- <description>H1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HR2</name>
- <displayName>HR2</displayName>
- <description>digest registers</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H2</name>
- <description>H2</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HR3</name>
- <displayName>HR3</displayName>
- <description>digest registers</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H3</name>
- <description>H3</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HR4</name>
- <displayName>HR4</displayName>
- <description>digest registers</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H4</name>
- <description>H4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IMR</name>
- <displayName>IMR</displayName>
- <description>interrupt enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DCIE</name>
- <description>Digest calculation completion interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DINIE</name>
- <description>Data input interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000001</resetValue>
- <fields>
- <field>
- <name>BUSY</name>
- <description>Busy bit</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMAS</name>
- <description>DMA Status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DCIS</name>
- <description>Digest calculation completion interrupt status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DINIS</name>
- <description>Data input interrupt status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR0</name>
- <displayName>CSR0</displayName>
- <description>context swap registers</description>
- <addressOffset>0xF8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR0</name>
- <description>CSR0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR1</name>
- <displayName>CSR1</displayName>
- <description>context swap registers</description>
- <addressOffset>0xFC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR1</name>
- <description>CSR1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR2</name>
- <displayName>CSR2</displayName>
- <description>context swap registers</description>
- <addressOffset>0x100</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR2</name>
- <description>CSR2</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR3</name>
- <displayName>CSR3</displayName>
- <description>context swap registers</description>
- <addressOffset>0x104</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR3</name>
- <description>CSR3</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR4</name>
- <displayName>CSR4</displayName>
- <description>context swap registers</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR4</name>
- <description>CSR4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR5</name>
- <displayName>CSR5</displayName>
- <description>context swap registers</description>
- <addressOffset>0x10C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR5</name>
- <description>CSR5</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR6</name>
- <displayName>CSR6</displayName>
- <description>context swap registers</description>
- <addressOffset>0x110</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR6</name>
- <description>CSR6</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR7</name>
- <displayName>CSR7</displayName>
- <description>context swap registers</description>
- <addressOffset>0x114</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR7</name>
- <description>CSR7</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR8</name>
- <displayName>CSR8</displayName>
- <description>context swap registers</description>
- <addressOffset>0x118</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR8</name>
- <description>CSR8</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR9</name>
- <displayName>CSR9</displayName>
- <description>context swap registers</description>
- <addressOffset>0x11C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR9</name>
- <description>CSR9</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR10</name>
- <displayName>CSR10</displayName>
- <description>context swap registers</description>
- <addressOffset>0x120</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR10</name>
- <description>CSR10</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR11</name>
- <displayName>CSR11</displayName>
- <description>context swap registers</description>
- <addressOffset>0x124</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR11</name>
- <description>CSR11</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR12</name>
- <displayName>CSR12</displayName>
- <description>context swap registers</description>
- <addressOffset>0x128</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR12</name>
- <description>CSR12</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR13</name>
- <displayName>CSR13</displayName>
- <description>context swap registers</description>
- <addressOffset>0x12C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR13</name>
- <description>CSR13</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR14</name>
- <displayName>CSR14</displayName>
- <description>context swap registers</description>
- <addressOffset>0x130</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR14</name>
- <description>CSR14</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR15</name>
- <displayName>CSR15</displayName>
- <description>context swap registers</description>
- <addressOffset>0x134</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR15</name>
- <description>CSR15</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR16</name>
- <displayName>CSR16</displayName>
- <description>context swap registers</description>
- <addressOffset>0x138</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR16</name>
- <description>CSR16</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR17</name>
- <displayName>CSR17</displayName>
- <description>context swap registers</description>
- <addressOffset>0x13C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR17</name>
- <description>CSR17</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR18</name>
- <displayName>CSR18</displayName>
- <description>context swap registers</description>
- <addressOffset>0x140</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR18</name>
- <description>CSR18</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR19</name>
- <displayName>CSR19</displayName>
- <description>context swap registers</description>
- <addressOffset>0x144</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR19</name>
- <description>CSR19</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR20</name>
- <displayName>CSR20</displayName>
- <description>context swap registers</description>
- <addressOffset>0x148</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR20</name>
- <description>CSR20</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR21</name>
- <displayName>CSR21</displayName>
- <description>context swap registers</description>
- <addressOffset>0x14C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR21</name>
- <description>CSR21</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR22</name>
- <displayName>CSR22</displayName>
- <description>context swap registers</description>
- <addressOffset>0x150</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR22</name>
- <description>CSR22</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR23</name>
- <displayName>CSR23</displayName>
- <description>context swap registers</description>
- <addressOffset>0x154</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR23</name>
- <description>CSR23</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR24</name>
- <displayName>CSR24</displayName>
- <description>context swap registers</description>
- <addressOffset>0x158</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR24</name>
- <description>CSR24</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR25</name>
- <displayName>CSR25</displayName>
- <description>context swap registers</description>
- <addressOffset>0x15C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR25</name>
- <description>CSR25</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR26</name>
- <displayName>CSR26</displayName>
- <description>context swap registers</description>
- <addressOffset>0x160</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR26</name>
- <description>CSR26</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR27</name>
- <displayName>CSR27</displayName>
- <description>context swap registers</description>
- <addressOffset>0x164</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR27</name>
- <description>CSR27</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR28</name>
- <displayName>CSR28</displayName>
- <description>context swap registers</description>
- <addressOffset>0x168</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR28</name>
- <description>CSR28</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR29</name>
- <displayName>CSR29</displayName>
- <description>context swap registers</description>
- <addressOffset>0x16C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR29</name>
- <description>CSR29</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR30</name>
- <displayName>CSR30</displayName>
- <description>context swap registers</description>
- <addressOffset>0x170</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR30</name>
- <description>CSR30</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR31</name>
- <displayName>CSR31</displayName>
- <description>context swap registers</description>
- <addressOffset>0x174</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR31</name>
- <description>CSR31</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR32</name>
- <displayName>CSR32</displayName>
- <description>context swap registers</description>
- <addressOffset>0x178</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR32</name>
- <description>CSR32</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR33</name>
- <displayName>CSR33</displayName>
- <description>context swap registers</description>
- <addressOffset>0x17C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR33</name>
- <description>CSR33</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR34</name>
- <displayName>CSR34</displayName>
- <description>context swap registers</description>
- <addressOffset>0x180</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR34</name>
- <description>CSR34</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR35</name>
- <displayName>CSR35</displayName>
- <description>context swap registers</description>
- <addressOffset>0x184</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR35</name>
- <description>CSR35</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR36</name>
- <displayName>CSR36</displayName>
- <description>context swap registers</description>
- <addressOffset>0x188</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR36</name>
- <description>CSR36</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR37</name>
- <displayName>CSR37</displayName>
- <description>context swap registers</description>
- <addressOffset>0x18C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR37</name>
- <description>CSR37</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR38</name>
- <displayName>CSR38</displayName>
- <description>context swap registers</description>
- <addressOffset>0x190</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR38</name>
- <description>CSR38</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR39</name>
- <displayName>CSR39</displayName>
- <description>context swap registers</description>
- <addressOffset>0x194</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR39</name>
- <description>CSR39</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR40</name>
- <displayName>CSR40</displayName>
- <description>context swap registers</description>
- <addressOffset>0x198</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR40</name>
- <description>CSR40</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR41</name>
- <displayName>CSR41</displayName>
- <description>context swap registers</description>
- <addressOffset>0x19C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR41</name>
- <description>CSR41</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR42</name>
- <displayName>CSR42</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1A0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR42</name>
- <description>CSR42</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR43</name>
- <displayName>CSR43</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1A4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR43</name>
- <description>CSR43</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR44</name>
- <displayName>CSR44</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1A8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR44</name>
- <description>CSR44</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR45</name>
- <displayName>CSR45</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1AC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR45</name>
- <description>CSR45</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR46</name>
- <displayName>CSR46</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1B0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR46</name>
- <description>CSR46</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR47</name>
- <displayName>CSR47</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1B4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR47</name>
- <description>CSR47</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR48</name>
- <displayName>CSR48</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1B8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR48</name>
- <description>CSR48</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR49</name>
- <displayName>CSR49</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1BC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR49</name>
- <description>CSR49</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR50</name>
- <displayName>CSR50</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1C0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR50</name>
- <description>CSR50</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR51</name>
- <displayName>CSR51</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1C4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR51</name>
- <description>CSR51</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR52</name>
- <displayName>CSR52</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1C8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR52</name>
- <description>CSR52</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR53</name>
- <displayName>CSR53</displayName>
- <description>context swap registers</description>
- <addressOffset>0x1CC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSR53</name>
- <description>CSR53</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR0</name>
- <displayName>HASH_HR0</displayName>
- <description>HASH digest register</description>
- <addressOffset>0x310</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H0</name>
- <description>H0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR1</name>
- <displayName>HASH_HR1</displayName>
- <description>read-only</description>
- <addressOffset>0x314</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H1</name>
- <description>H1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR2</name>
- <displayName>HASH_HR2</displayName>
- <description>read-only</description>
- <addressOffset>0x318</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H2</name>
- <description>H2</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR3</name>
- <displayName>HASH_HR3</displayName>
- <description>read-only</description>
- <addressOffset>0x31C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H3</name>
- <description>H3</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR4</name>
- <displayName>HASH_HR4</displayName>
- <description>read-only</description>
- <addressOffset>0x320</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H4</name>
- <description>H4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR5</name>
- <displayName>HASH_HR5</displayName>
- <description>read-only</description>
- <addressOffset>0x324</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H5</name>
- <description>H5</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR6</name>
- <displayName>HASH_HR6</displayName>
- <description>read-only</description>
- <addressOffset>0x328</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H6</name>
- <description>H6</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HASH_HR7</name>
- <displayName>HASH_HR7</displayName>
- <description>read-only</description>
- <addressOffset>0x32C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>H7</name>
- <description>H7</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>CRYP</name>
- <description>Cryptographic processor</description>
- <groupName>CRYP</groupName>
- <baseAddress>0x50060000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>CRYP</name>
- <description>CRYP crypto global interrupt</description>
- <value>79</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ALGODIR</name>
- <description>Algorithm direction</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALGOMODE0</name>
- <description>Algorithm mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DATATYPE</name>
- <description>Data type selection</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>KEYSIZE</name>
- <description>Key size selection (AES mode only)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FFLUSH</name>
- <description>FIFO flush</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CRYPEN</name>
- <description>Cryptographic processor enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GCM_CCMPH</name>
- <description>GCM_CCMPH</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALGOMODE3</name>
- <description>ALGOMODE</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000003</resetValue>
- <fields>
- <field>
- <name>BUSY</name>
- <description>Busy bit</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OFFU</name>
- <description>Output FIFO full</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OFNE</name>
- <description>Output FIFO not empty</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IFNF</name>
- <description>Input FIFO not full</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IFEM</name>
- <description>Input FIFO empty</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIN</name>
- <displayName>DIN</displayName>
- <description>data input register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATAIN</name>
- <description>Data input</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DOUT</name>
- <displayName>DOUT</displayName>
- <description>data output register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATAOUT</name>
- <description>Data output</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMACR</name>
- <displayName>DMACR</displayName>
- <description>DMA control register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DOEN</name>
- <description>DMA output enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIEN</name>
- <description>DMA input enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IMSCR</name>
- <displayName>IMSCR</displayName>
- <description>interrupt mask set/clear register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OUTIM</name>
- <description>Output FIFO service interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INIM</name>
- <description>Input FIFO service interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RISR</name>
- <displayName>RISR</displayName>
- <description>raw interrupt status register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000001</resetValue>
- <fields>
- <field>
- <name>OUTRIS</name>
- <description>Output FIFO service raw interrupt status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INRIS</name>
- <description>Input FIFO service raw interrupt status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MISR</name>
- <displayName>MISR</displayName>
- <description>masked interrupt status register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OUTMIS</name>
- <description>Output FIFO service masked interrupt status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INMIS</name>
- <description>Input FIFO service masked interrupt status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K0LR</name>
- <displayName>K0LR</displayName>
- <description>key registers</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b224</name>
- <description>b224</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b225</name>
- <description>b225</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b226</name>
- <description>b226</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b227</name>
- <description>b227</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b228</name>
- <description>b228</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b229</name>
- <description>b229</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b230</name>
- <description>b230</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b231</name>
- <description>b231</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b232</name>
- <description>b232</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b233</name>
- <description>b233</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b234</name>
- <description>b234</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b235</name>
- <description>b235</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b236</name>
- <description>b236</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b237</name>
- <description>b237</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b238</name>
- <description>b238</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b239</name>
- <description>b239</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b240</name>
- <description>b240</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b241</name>
- <description>b241</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b242</name>
- <description>b242</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b243</name>
- <description>b243</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b244</name>
- <description>b244</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b245</name>
- <description>b245</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b246</name>
- <description>b246</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b247</name>
- <description>b247</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b248</name>
- <description>b248</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b249</name>
- <description>b249</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b250</name>
- <description>b250</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b251</name>
- <description>b251</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b252</name>
- <description>b252</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b253</name>
- <description>b253</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b254</name>
- <description>b254</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b255</name>
- <description>b255</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K0RR</name>
- <displayName>K0RR</displayName>
- <description>key registers</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b192</name>
- <description>b192</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b193</name>
- <description>b193</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b194</name>
- <description>b194</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b195</name>
- <description>b195</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b196</name>
- <description>b196</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b197</name>
- <description>b197</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b198</name>
- <description>b198</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b199</name>
- <description>b199</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b200</name>
- <description>b200</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b201</name>
- <description>b201</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b202</name>
- <description>b202</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b203</name>
- <description>b203</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b204</name>
- <description>b204</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b205</name>
- <description>b205</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b206</name>
- <description>b206</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b207</name>
- <description>b207</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b208</name>
- <description>b208</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b209</name>
- <description>b209</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b210</name>
- <description>b210</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b211</name>
- <description>b211</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b212</name>
- <description>b212</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b213</name>
- <description>b213</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b214</name>
- <description>b214</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b215</name>
- <description>b215</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b216</name>
- <description>b216</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b217</name>
- <description>b217</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b218</name>
- <description>b218</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b219</name>
- <description>b219</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b220</name>
- <description>b220</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b221</name>
- <description>b221</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b222</name>
- <description>b222</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b223</name>
- <description>b223</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K1LR</name>
- <displayName>K1LR</displayName>
- <description>key registers</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b160</name>
- <description>b160</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b161</name>
- <description>b161</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b162</name>
- <description>b162</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b163</name>
- <description>b163</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b164</name>
- <description>b164</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b165</name>
- <description>b165</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b166</name>
- <description>b166</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b167</name>
- <description>b167</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b168</name>
- <description>b168</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b169</name>
- <description>b169</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b170</name>
- <description>b170</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b171</name>
- <description>b171</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b172</name>
- <description>b172</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b173</name>
- <description>b173</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b174</name>
- <description>b174</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b175</name>
- <description>b175</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b176</name>
- <description>b176</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b177</name>
- <description>b177</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b178</name>
- <description>b178</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b179</name>
- <description>b179</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b180</name>
- <description>b180</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b181</name>
- <description>b181</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b182</name>
- <description>b182</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b183</name>
- <description>b183</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b184</name>
- <description>b184</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b185</name>
- <description>b185</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b186</name>
- <description>b186</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b187</name>
- <description>b187</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b188</name>
- <description>b188</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b189</name>
- <description>b189</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b190</name>
- <description>b190</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b191</name>
- <description>b191</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K1RR</name>
- <displayName>K1RR</displayName>
- <description>key registers</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b128</name>
- <description>b128</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b129</name>
- <description>b129</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b130</name>
- <description>b130</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b131</name>
- <description>b131</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b132</name>
- <description>b132</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b133</name>
- <description>b133</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b134</name>
- <description>b134</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b135</name>
- <description>b135</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b136</name>
- <description>b136</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b137</name>
- <description>b137</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b138</name>
- <description>b138</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b139</name>
- <description>b139</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b140</name>
- <description>b140</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b141</name>
- <description>b141</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b142</name>
- <description>b142</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b143</name>
- <description>b143</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b144</name>
- <description>b144</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b145</name>
- <description>b145</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b146</name>
- <description>b146</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b147</name>
- <description>b147</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b148</name>
- <description>b148</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b149</name>
- <description>b149</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b150</name>
- <description>b150</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b151</name>
- <description>b151</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b152</name>
- <description>b152</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b153</name>
- <description>b153</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b154</name>
- <description>b154</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b155</name>
- <description>b155</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b156</name>
- <description>b156</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b157</name>
- <description>b157</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b158</name>
- <description>b158</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b159</name>
- <description>b159</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K2LR</name>
- <displayName>K2LR</displayName>
- <description>key registers</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b96</name>
- <description>b96</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b97</name>
- <description>b97</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b98</name>
- <description>b98</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b99</name>
- <description>b99</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b100</name>
- <description>b100</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b101</name>
- <description>b101</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b102</name>
- <description>b102</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b103</name>
- <description>b103</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b104</name>
- <description>b104</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b105</name>
- <description>b105</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b106</name>
- <description>b106</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b107</name>
- <description>b107</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b108</name>
- <description>b108</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b109</name>
- <description>b109</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b110</name>
- <description>b110</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b111</name>
- <description>b111</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b112</name>
- <description>b112</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b113</name>
- <description>b113</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b114</name>
- <description>b114</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b115</name>
- <description>b115</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b116</name>
- <description>b116</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b117</name>
- <description>b117</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b118</name>
- <description>b118</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b119</name>
- <description>b119</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b120</name>
- <description>b120</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b121</name>
- <description>b121</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b122</name>
- <description>b122</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b123</name>
- <description>b123</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b124</name>
- <description>b124</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b125</name>
- <description>b125</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b126</name>
- <description>b126</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b127</name>
- <description>b127</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K2RR</name>
- <displayName>K2RR</displayName>
- <description>key registers</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b64</name>
- <description>b64</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b65</name>
- <description>b65</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b66</name>
- <description>b66</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b67</name>
- <description>b67</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b68</name>
- <description>b68</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b69</name>
- <description>b69</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b70</name>
- <description>b70</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b71</name>
- <description>b71</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b72</name>
- <description>b72</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b73</name>
- <description>b73</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b74</name>
- <description>b74</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b75</name>
- <description>b75</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b76</name>
- <description>b76</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b77</name>
- <description>b77</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b78</name>
- <description>b78</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b79</name>
- <description>b79</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b80</name>
- <description>b80</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b81</name>
- <description>b81</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b82</name>
- <description>b82</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b83</name>
- <description>b83</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b84</name>
- <description>b84</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b85</name>
- <description>b85</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b86</name>
- <description>b86</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b87</name>
- <description>b87</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b88</name>
- <description>b88</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b89</name>
- <description>b89</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b90</name>
- <description>b90</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b91</name>
- <description>b91</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b92</name>
- <description>b92</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b93</name>
- <description>b93</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b94</name>
- <description>b94</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b95</name>
- <description>b95</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K3LR</name>
- <displayName>K3LR</displayName>
- <description>key registers</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b32</name>
- <description>b32</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b33</name>
- <description>b33</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b34</name>
- <description>b34</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b35</name>
- <description>b35</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b36</name>
- <description>b36</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b37</name>
- <description>b37</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b38</name>
- <description>b38</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b39</name>
- <description>b39</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b40</name>
- <description>b40</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b41</name>
- <description>b41</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b42</name>
- <description>b42</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b43</name>
- <description>b43</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b44</name>
- <description>b44</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b45</name>
- <description>b45</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b46</name>
- <description>b46</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b47</name>
- <description>b47</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b48</name>
- <description>b48</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b49</name>
- <description>b49</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b50</name>
- <description>b50</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b51</name>
- <description>b51</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b52</name>
- <description>b52</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b53</name>
- <description>b53</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b54</name>
- <description>b54</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b55</name>
- <description>b55</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b56</name>
- <description>b56</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b57</name>
- <description>b57</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b58</name>
- <description>b58</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b59</name>
- <description>b59</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b60</name>
- <description>b60</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b61</name>
- <description>b61</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b62</name>
- <description>b62</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b63</name>
- <description>b63</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>K3RR</name>
- <displayName>K3RR</displayName>
- <description>key registers</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>b0</name>
- <description>b0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b1</name>
- <description>b1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b2</name>
- <description>b2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b3</name>
- <description>b3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b4</name>
- <description>b4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b5</name>
- <description>b5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b6</name>
- <description>b6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b7</name>
- <description>b7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b8</name>
- <description>b8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b9</name>
- <description>b9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b10</name>
- <description>b10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b11</name>
- <description>b11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b12</name>
- <description>b12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b13</name>
- <description>b13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b14</name>
- <description>b14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b15</name>
- <description>b15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b16</name>
- <description>b16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b17</name>
- <description>b17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b18</name>
- <description>b18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b19</name>
- <description>b19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b20</name>
- <description>b20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b21</name>
- <description>b21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b22</name>
- <description>b22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b23</name>
- <description>b23</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b24</name>
- <description>b24</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b25</name>
- <description>b25</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b26</name>
- <description>b26</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b27</name>
- <description>b27</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b28</name>
- <description>b28</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b29</name>
- <description>b29</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b30</name>
- <description>b30</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>b31</name>
- <description>b31</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IV0LR</name>
- <displayName>IV0LR</displayName>
- <description>initialization vector registers</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IV31</name>
- <description>IV31</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV30</name>
- <description>IV30</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV29</name>
- <description>IV29</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV28</name>
- <description>IV28</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV27</name>
- <description>IV27</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV26</name>
- <description>IV26</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV25</name>
- <description>IV25</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV24</name>
- <description>IV24</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV23</name>
- <description>IV23</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV22</name>
- <description>IV22</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV21</name>
- <description>IV21</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV20</name>
- <description>IV20</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV19</name>
- <description>IV19</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV18</name>
- <description>IV18</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV17</name>
- <description>IV17</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV16</name>
- <description>IV16</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV15</name>
- <description>IV15</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV14</name>
- <description>IV14</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV13</name>
- <description>IV13</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV12</name>
- <description>IV12</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV11</name>
- <description>IV11</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV10</name>
- <description>IV10</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV9</name>
- <description>IV9</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV8</name>
- <description>IV8</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV7</name>
- <description>IV7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV6</name>
- <description>IV6</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV5</name>
- <description>IV5</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV4</name>
- <description>IV4</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV3</name>
- <description>IV3</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV2</name>
- <description>IV2</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV1</name>
- <description>IV1</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV0</name>
- <description>IV0</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IV0RR</name>
- <displayName>IV0RR</displayName>
- <description>initialization vector registers</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IV63</name>
- <description>IV63</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV62</name>
- <description>IV62</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV61</name>
- <description>IV61</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV60</name>
- <description>IV60</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV59</name>
- <description>IV59</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV58</name>
- <description>IV58</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV57</name>
- <description>IV57</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV56</name>
- <description>IV56</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV55</name>
- <description>IV55</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV54</name>
- <description>IV54</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV53</name>
- <description>IV53</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV52</name>
- <description>IV52</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV51</name>
- <description>IV51</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV50</name>
- <description>IV50</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV49</name>
- <description>IV49</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV48</name>
- <description>IV48</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV47</name>
- <description>IV47</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV46</name>
- <description>IV46</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV45</name>
- <description>IV45</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV44</name>
- <description>IV44</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV43</name>
- <description>IV43</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV42</name>
- <description>IV42</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV41</name>
- <description>IV41</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV40</name>
- <description>IV40</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV39</name>
- <description>IV39</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV38</name>
- <description>IV38</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV37</name>
- <description>IV37</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV36</name>
- <description>IV36</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV35</name>
- <description>IV35</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV34</name>
- <description>IV34</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV33</name>
- <description>IV33</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV32</name>
- <description>IV32</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IV1LR</name>
- <displayName>IV1LR</displayName>
- <description>initialization vector registers</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IV95</name>
- <description>IV95</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV94</name>
- <description>IV94</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV93</name>
- <description>IV93</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV92</name>
- <description>IV92</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV91</name>
- <description>IV91</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV90</name>
- <description>IV90</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV89</name>
- <description>IV89</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV88</name>
- <description>IV88</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV87</name>
- <description>IV87</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV86</name>
- <description>IV86</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV85</name>
- <description>IV85</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV84</name>
- <description>IV84</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV83</name>
- <description>IV83</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV82</name>
- <description>IV82</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV81</name>
- <description>IV81</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV80</name>
- <description>IV80</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV79</name>
- <description>IV79</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV78</name>
- <description>IV78</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV77</name>
- <description>IV77</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV76</name>
- <description>IV76</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV75</name>
- <description>IV75</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV74</name>
- <description>IV74</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV73</name>
- <description>IV73</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV72</name>
- <description>IV72</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV71</name>
- <description>IV71</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV70</name>
- <description>IV70</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV69</name>
- <description>IV69</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV68</name>
- <description>IV68</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV67</name>
- <description>IV67</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV66</name>
- <description>IV66</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV65</name>
- <description>IV65</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV64</name>
- <description>IV64</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IV1RR</name>
- <displayName>IV1RR</displayName>
- <description>initialization vector registers</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IV127</name>
- <description>IV127</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV126</name>
- <description>IV126</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV125</name>
- <description>IV125</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV124</name>
- <description>IV124</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV123</name>
- <description>IV123</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV122</name>
- <description>IV122</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV121</name>
- <description>IV121</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV120</name>
- <description>IV120</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV119</name>
- <description>IV119</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV118</name>
- <description>IV118</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV117</name>
- <description>IV117</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV116</name>
- <description>IV116</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV115</name>
- <description>IV115</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV114</name>
- <description>IV114</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV113</name>
- <description>IV113</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV112</name>
- <description>IV112</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV111</name>
- <description>IV111</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV110</name>
- <description>IV110</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV109</name>
- <description>IV109</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV108</name>
- <description>IV108</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV107</name>
- <description>IV107</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV106</name>
- <description>IV106</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV105</name>
- <description>IV105</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV104</name>
- <description>IV104</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV103</name>
- <description>IV103</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV102</name>
- <description>IV102</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV101</name>
- <description>IV101</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV100</name>
- <description>IV100</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV99</name>
- <description>IV99</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV98</name>
- <description>IV98</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV97</name>
- <description>IV97</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IV96</name>
- <description>IV96</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM0R</name>
- <displayName>CSGCMCCM0R</displayName>
- <description>context swap register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM0R</name>
- <description>CSGCMCCM0R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM1R</name>
- <displayName>CSGCMCCM1R</displayName>
- <description>context swap register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM1R</name>
- <description>CSGCMCCM1R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM2R</name>
- <displayName>CSGCMCCM2R</displayName>
- <description>context swap register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM2R</name>
- <description>CSGCMCCM2R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM3R</name>
- <displayName>CSGCMCCM3R</displayName>
- <description>context swap register</description>
- <addressOffset>0x5C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM3R</name>
- <description>CSGCMCCM3R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM4R</name>
- <displayName>CSGCMCCM4R</displayName>
- <description>context swap register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM4R</name>
- <description>CSGCMCCM4R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM5R</name>
- <displayName>CSGCMCCM5R</displayName>
- <description>context swap register</description>
- <addressOffset>0x64</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM5R</name>
- <description>CSGCMCCM5R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM6R</name>
- <displayName>CSGCMCCM6R</displayName>
- <description>context swap register</description>
- <addressOffset>0x68</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM6R</name>
- <description>CSGCMCCM6R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCMCCM7R</name>
- <displayName>CSGCMCCM7R</displayName>
- <description>context swap register</description>
- <addressOffset>0x6C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCMCCM7R</name>
- <description>CSGCMCCM7R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM0R</name>
- <displayName>CSGCM0R</displayName>
- <description>context swap register</description>
- <addressOffset>0x70</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM0R</name>
- <description>CSGCM0R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM1R</name>
- <displayName>CSGCM1R</displayName>
- <description>context swap register</description>
- <addressOffset>0x74</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM1R</name>
- <description>CSGCM1R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM2R</name>
- <displayName>CSGCM2R</displayName>
- <description>context swap register</description>
- <addressOffset>0x78</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM2R</name>
- <description>CSGCM2R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM3R</name>
- <displayName>CSGCM3R</displayName>
- <description>context swap register</description>
- <addressOffset>0x7C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM3R</name>
- <description>CSGCM3R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM4R</name>
- <displayName>CSGCM4R</displayName>
- <description>context swap register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM4R</name>
- <description>CSGCM4R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM5R</name>
- <displayName>CSGCM5R</displayName>
- <description>context swap register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM5R</name>
- <description>CSGCM5R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM6R</name>
- <displayName>CSGCM6R</displayName>
- <description>context swap register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM6R</name>
- <description>CSGCM6R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSGCM7R</name>
- <displayName>CSGCM7R</displayName>
- <description>context swap register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSGCM7R</name>
- <description>CSGCM7R</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>DCMI</name>
- <description>Digital camera interface</description>
- <groupName>DCMI</groupName>
- <baseAddress>0x50050000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>DCMI</name>
- <description>DCMI global interrupt</description>
- <value>78</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>DCMI enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EDM</name>
- <description>Extended data mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FCRC</name>
- <description>Frame capture rate control</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>VSPOL</name>
- <description>Vertical synchronization polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HSPOL</name>
- <description>Horizontal synchronization polarity</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PCKPOL</name>
- <description>Pixel clock polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ESS</name>
- <description>Embedded synchronization select</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JPEG</name>
- <description>JPEG format</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CROP</name>
- <description>Crop feature</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CM</name>
- <description>Capture mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAPTURE</name>
- <description>Capture enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>FNE</name>
- <description>FIFO not empty</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNC</name>
- <description>VSYNC</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HSYNC</name>
- <description>HSYNC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RIS</name>
- <displayName>RIS</displayName>
- <description>raw interrupt status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>LINE_RIS</name>
- <description>Line raw interrupt status</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNC_RIS</name>
- <description>VSYNC raw interrupt status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERR_RIS</name>
- <description>Synchronization error raw interrupt status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR_RIS</name>
- <description>Overrun raw interrupt status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRAME_RIS</name>
- <description>Capture complete raw interrupt status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IER</name>
- <displayName>IER</displayName>
- <description>interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>LINE_IE</name>
- <description>Line interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNC_IE</name>
- <description>VSYNC interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERR_IE</name>
- <description>Synchronization error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR_IE</name>
- <description>Overrun interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRAME_IE</name>
- <description>Capture complete interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MIS</name>
- <displayName>MIS</displayName>
- <description>masked interrupt status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>LINE_MIS</name>
- <description>Line masked interrupt status</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNC_MIS</name>
- <description>VSYNC masked interrupt status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERR_MIS</name>
- <description>Synchronization error masked interrupt status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR_MIS</name>
- <description>Overrun masked interrupt status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRAME_MIS</name>
- <description>Capture complete masked interrupt status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>interrupt clear register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>LINE_ISC</name>
- <description>line interrupt status clear</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNC_ISC</name>
- <description>Vertical synch interrupt status clear</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERR_ISC</name>
- <description>Synchronization error interrupt status clear</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR_ISC</name>
- <description>Overrun interrupt status clear</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRAME_ISC</name>
- <description>Capture complete interrupt status clear</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ESCR</name>
- <displayName>ESCR</displayName>
- <description>embedded synchronization code register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>FEC</name>
- <description>Frame end delimiter code</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>LEC</name>
- <description>Line end delimiter code</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>LSC</name>
- <description>Line start delimiter code</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>FSC</name>
- <description>Frame start delimiter code</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ESUR</name>
- <displayName>ESUR</displayName>
- <description>embedded synchronization unmask register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>FEU</name>
- <description>Frame end delimiter unmask</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>LEU</name>
- <description>Line end delimiter unmask</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>LSU</name>
- <description>Line start delimiter unmask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>FSU</name>
- <description>Frame start delimiter unmask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CWSTRT</name>
- <displayName>CWSTRT</displayName>
- <description>crop window start</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>VST</name>
- <description>Vertical start line count</description>
- <bitOffset>16</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- <field>
- <name>HOFFCNT</name>
- <description>Horizontal offset count</description>
- <bitOffset>0</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CWSIZE</name>
- <displayName>CWSIZE</displayName>
- <description>crop window size</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>VLINE</name>
- <description>Vertical line count</description>
- <bitOffset>16</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- <field>
- <name>CAPCNT</name>
- <description>Capture count</description>
- <bitOffset>0</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>data register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>Byte3</name>
- <description>Data byte 3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>Byte2</name>
- <description>Data byte 2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>Byte1</name>
- <description>Data byte 1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>Byte0</name>
- <description>Data byte 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>FMC</name>
- <description>Flexible memory controller</description>
- <groupName>FSMC</groupName>
- <baseAddress>0xA0000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x1000</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>FMC</name>
- <description>FMC global interrupt</description>
- <value>48</value>
- </interrupt>
- <registers>
- <register>
- <name>BCR1</name>
- <displayName>BCR1</displayName>
- <description>SRAM/NOR-Flash chip-select control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000030D0</resetValue>
- <fields>
- <field>
- <name>CCLKEN</name>
- <description>CCLKEN</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CBURSTRW</name>
- <description>CBURSTRW</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASYNCWAIT</name>
- <description>ASYNCWAIT</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTMOD</name>
- <description>EXTMOD</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITEN</name>
- <description>WAITEN</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WREN</name>
- <description>WREN</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITCFG</name>
- <description>WAITCFG</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITPOL</name>
- <description>WAITPOL</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BURSTEN</name>
- <description>BURSTEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACCEN</name>
- <description>FACCEN</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>MWID</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MTYP</name>
- <description>MTYP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MUXEN</name>
- <description>MUXEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MBKEN</name>
- <description>MBKEN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BTR1</name>
- <displayName>BTR1</displayName>
- <description>SRAM/NOR-Flash chip-select timing register 1</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BUSTURN</name>
- <description>BUSTURN</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCR2</name>
- <displayName>BCR2</displayName>
- <description>SRAM/NOR-Flash chip-select control register 2</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000030D0</resetValue>
- <fields>
- <field>
- <name>CBURSTRW</name>
- <description>CBURSTRW</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASYNCWAIT</name>
- <description>ASYNCWAIT</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTMOD</name>
- <description>EXTMOD</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITEN</name>
- <description>WAITEN</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WREN</name>
- <description>WREN</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITCFG</name>
- <description>WAITCFG</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WRAPMOD</name>
- <description>WRAPMOD</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITPOL</name>
- <description>WAITPOL</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BURSTEN</name>
- <description>BURSTEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACCEN</name>
- <description>FACCEN</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>MWID</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MTYP</name>
- <description>MTYP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MUXEN</name>
- <description>MUXEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MBKEN</name>
- <description>MBKEN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BTR2</name>
- <displayName>BTR2</displayName>
- <description>SRAM/NOR-Flash chip-select timing register 2</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BUSTURN</name>
- <description>BUSTURN</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCR3</name>
- <displayName>BCR3</displayName>
- <description>SRAM/NOR-Flash chip-select control register 3</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000030D0</resetValue>
- <fields>
- <field>
- <name>CBURSTRW</name>
- <description>CBURSTRW</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASYNCWAIT</name>
- <description>ASYNCWAIT</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTMOD</name>
- <description>EXTMOD</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITEN</name>
- <description>WAITEN</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WREN</name>
- <description>WREN</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITCFG</name>
- <description>WAITCFG</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WRAPMOD</name>
- <description>WRAPMOD</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITPOL</name>
- <description>WAITPOL</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BURSTEN</name>
- <description>BURSTEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACCEN</name>
- <description>FACCEN</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>MWID</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MTYP</name>
- <description>MTYP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MUXEN</name>
- <description>MUXEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MBKEN</name>
- <description>MBKEN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BTR3</name>
- <displayName>BTR3</displayName>
- <description>SRAM/NOR-Flash chip-select timing register 3</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BUSTURN</name>
- <description>BUSTURN</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCR4</name>
- <displayName>BCR4</displayName>
- <description>SRAM/NOR-Flash chip-select control register 4</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000030D0</resetValue>
- <fields>
- <field>
- <name>CBURSTRW</name>
- <description>CBURSTRW</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASYNCWAIT</name>
- <description>ASYNCWAIT</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTMOD</name>
- <description>EXTMOD</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITEN</name>
- <description>WAITEN</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WREN</name>
- <description>WREN</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITCFG</name>
- <description>WAITCFG</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WRAPMOD</name>
- <description>WRAPMOD</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITPOL</name>
- <description>WAITPOL</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BURSTEN</name>
- <description>BURSTEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACCEN</name>
- <description>FACCEN</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>MWID</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MTYP</name>
- <description>MTYP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MUXEN</name>
- <description>MUXEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MBKEN</name>
- <description>MBKEN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BTR4</name>
- <displayName>BTR4</displayName>
- <description>SRAM/NOR-Flash chip-select timing register 4</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BUSTURN</name>
- <description>BUSTURN</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PCR</name>
- <displayName>PCR</displayName>
- <description>PC Card/NAND Flash control register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000018</resetValue>
- <fields>
- <field>
- <name>ECCPS</name>
- <description>ECCPS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TAR</name>
- <description>TAR</description>
- <bitOffset>13</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TCLR</name>
- <description>TCLR</description>
- <bitOffset>9</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ECCEN</name>
- <description>ECCEN</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWID</name>
- <description>PWID</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PTYP</name>
- <description>PTYP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PBKEN</name>
- <description>PBKEN</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWAITEN</name>
- <description>PWAITEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>FIFO status and interrupt register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000040</resetValue>
- <fields>
- <field>
- <name>FEMPT</name>
- <description>FEMPT</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>IFEN</name>
- <description>IFEN</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ILEN</name>
- <description>ILEN</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IREN</name>
- <description>IREN</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IFS</name>
- <description>IFS</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ILS</name>
- <description>ILS</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IRS</name>
- <description>IRS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>PMEM</name>
- <displayName>PMEM</displayName>
- <description>Common memory space timing register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFCFCFCFC</resetValue>
- <fields>
- <field>
- <name>MEMHIZx</name>
- <description>MEMHIZx</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>MEMHOLDx</name>
- <description>MEMHOLDx</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>MEMWAITx</name>
- <description>MEMWAITx</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>MEMSETx</name>
- <description>MEMSETx</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PATT</name>
- <displayName>PATT</displayName>
- <description>Attribute memory space timing register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFCFCFCFC</resetValue>
- <fields>
- <field>
- <name>ATTHIZx</name>
- <description>ATTHIZx</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ATTHOLDx</name>
- <description>ATTHOLDx</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ATTWAITx</name>
- <description>ATTWAITx</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ATTSETx</name>
- <description>ATTSETx</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ECCR</name>
- <displayName>ECCR</displayName>
- <description>ECC result register</description>
- <addressOffset>0x94</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ECCx</name>
- <description>ECCx</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BWTR1</name>
- <displayName>BWTR1</displayName>
- <description>SRAM/NOR-Flash write timing registers 1</description>
- <addressOffset>0x104</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BWTR2</name>
- <displayName>BWTR2</displayName>
- <description>SRAM/NOR-Flash write timing registers 2</description>
- <addressOffset>0x10C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BWTR3</name>
- <displayName>BWTR3</displayName>
- <description>SRAM/NOR-Flash write timing registers 3</description>
- <addressOffset>0x114</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BWTR4</name>
- <displayName>BWTR4</displayName>
- <description>SRAM/NOR-Flash write timing registers 4</description>
- <addressOffset>0x11C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>ACCMOD</name>
- <description>ACCMOD</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DATLAT</name>
- <description>DATLAT</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>CLKDIV</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DATAST</name>
- <description>DATAST</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDHLD</name>
- <description>ADDHLD</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADDSET</name>
- <description>ADDSET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SDCR1</name>
- <displayName>SDCR1</displayName>
- <description>SDRAM Control Register 1</description>
- <addressOffset>0x140</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000002D0</resetValue>
- <fields>
- <field>
- <name>NC</name>
- <description>Number of column address bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NR</name>
- <description>Number of row address bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>Memory data bus width</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NB</name>
- <description>Number of internal banks</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAS</name>
- <description>CAS latency</description>
- <bitOffset>7</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>WP</name>
- <description>Write protection</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDCLK</name>
- <description>SDRAM clock configuration</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>RBURST</name>
- <description>Burst read</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RPIPE</name>
- <description>Read pipe</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SDCR2</name>
- <displayName>SDCR2</displayName>
- <description>SDRAM Control Register 2</description>
- <addressOffset>0x144</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000002D0</resetValue>
- <fields>
- <field>
- <name>NC</name>
- <description>Number of column address bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NR</name>
- <description>Number of row address bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MWID</name>
- <description>Memory data bus width</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NB</name>
- <description>Number of internal banks</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAS</name>
- <description>CAS latency</description>
- <bitOffset>7</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>WP</name>
- <description>Write protection</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDCLK</name>
- <description>SDRAM clock configuration</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>RBURST</name>
- <description>Burst read</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RPIPE</name>
- <description>Read pipe</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SDTR1</name>
- <displayName>SDTR1</displayName>
- <description>SDRAM Timing register 1</description>
- <addressOffset>0x148</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>TMRD</name>
- <description>Load Mode Register to Active</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TXSR</name>
- <description>Exit self-refresh delay</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRAS</name>
- <description>Self refresh time</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRC</name>
- <description>Row cycle delay</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TWR</name>
- <description>Recovery delay</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRP</name>
- <description>Row precharge delay</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRCD</name>
- <description>Row to column delay</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SDTR2</name>
- <displayName>SDTR2</displayName>
- <description>SDRAM Timing register 2</description>
- <addressOffset>0x14C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0FFFFFFF</resetValue>
- <fields>
- <field>
- <name>TMRD</name>
- <description>Load Mode Register to Active</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TXSR</name>
- <description>Exit self-refresh delay</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRAS</name>
- <description>Self refresh time</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRC</name>
- <description>Row cycle delay</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TWR</name>
- <description>Recovery delay</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRP</name>
- <description>Row precharge delay</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>TRCD</name>
- <description>Row to column delay</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SDCMR</name>
- <displayName>SDCMR</displayName>
- <description>SDRAM Command Mode register</description>
- <addressOffset>0x150</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MODE</name>
- <description>Command mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CTB2</name>
- <description>Command target bank 2</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CTB1</name>
- <description>Command target bank 1</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>NRFS</name>
- <description>Number of Auto-refresh</description>
- <bitOffset>5</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MRD</name>
- <description>Mode Register definition</description>
- <bitOffset>9</bitOffset>
- <bitWidth>13</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SDRTR</name>
- <displayName>SDRTR</displayName>
- <description>SDRAM Refresh Timer register</description>
- <addressOffset>0x154</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CRE</name>
- <description>Clear Refresh error flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>COUNT</name>
- <description>Refresh Timer Count</description>
- <bitOffset>1</bitOffset>
- <bitWidth>13</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>REIE</name>
- <description>RES Interrupt Enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SDSR</name>
- <displayName>SDSR</displayName>
- <description>SDRAM Status register</description>
- <addressOffset>0x158</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RE</name>
- <description>Refresh error flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MODES1</name>
- <description>Status Mode for Bank 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODES2</name>
- <description>Status Mode for Bank 2</description>
- <bitOffset>3</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>BUSY</name>
- <description>Busy status</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>DBG</name>
- <description>Debug support</description>
- <groupName>DBG</groupName>
- <baseAddress>0xE0042000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DBGMCU_IDCODE</name>
- <displayName>DBGMCU_IDCODE</displayName>
- <description>IDCODE</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x10006411</resetValue>
- <fields>
- <field>
- <name>DEV_ID</name>
- <description>DEV_ID</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>REV_ID</name>
- <description>REV_ID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DBGMCU_CR</name>
- <displayName>DBGMCU_CR</displayName>
- <description>Control Register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DBG_SLEEP</name>
- <description>DBG_SLEEP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_STOP</name>
- <description>DBG_STOP</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_STANDBY</name>
- <description>DBG_STANDBY</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TRACE_IOEN</name>
- <description>TRACE_IOEN</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TRACE_MODE</name>
- <description>TRACE_MODE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DBGMCU_APB1_FZ</name>
- <displayName>DBGMCU_APB1_FZ</displayName>
- <description>Debug MCU APB1 Freeze registe</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DBG_TIM2_STOP</name>
- <description>DBG_TIM2_STOP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM3_STOP</name>
- <description>DBG_TIM3 _STOP</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM4_STOP</name>
- <description>DBG_TIM4_STOP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM5_STOP</name>
- <description>DBG_TIM5_STOP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM6_STOP</name>
- <description>DBG_TIM6_STOP</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM7_STOP</name>
- <description>DBG_TIM7_STOP</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM12_STOP</name>
- <description>DBG_TIM12_STOP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM13_STOP</name>
- <description>DBG_TIM13_STOP</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM14_STOP</name>
- <description>DBG_TIM14_STOP</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_WWDG_STOP</name>
- <description>DBG_WWDG_STOP</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_IWDEG_STOP</name>
- <description>DBG_IWDEG_STOP</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_J2C1_SMBUS_TIMEOUT</name>
- <description>DBG_J2C1_SMBUS_TIMEOUT</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_J2C2_SMBUS_TIMEOUT</name>
- <description>DBG_J2C2_SMBUS_TIMEOUT</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_J2C3SMBUS_TIMEOUT</name>
- <description>DBG_J2C3SMBUS_TIMEOUT</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_CAN1_STOP</name>
- <description>DBG_CAN1_STOP</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_CAN2_STOP</name>
- <description>DBG_CAN2_STOP</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DBGMCU_APB2_FZ</name>
- <displayName>DBGMCU_APB2_FZ</displayName>
- <description>Debug MCU APB2 Freeze registe</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DBG_TIM1_STOP</name>
- <description>TIM1 counter stopped when core is halted</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM8_STOP</name>
- <description>TIM8 counter stopped when core is halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM9_STOP</name>
- <description>TIM9 counter stopped when core is halted</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM10_STOP</name>
- <description>TIM10 counter stopped when core is halted</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBG_TIM11_STOP</name>
- <description>TIM11 counter stopped when core is halted</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>DMA2</name>
- <description>DMA controller</description>
- <groupName>DMA</groupName>
- <baseAddress>0x40026400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>DMA2_Stream0</name>
- <description>DMA2 Stream0 global interrupt</description>
- <value>56</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream1</name>
- <description>DMA2 Stream1 global interrupt</description>
- <value>57</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream2</name>
- <description>DMA2 Stream2 global interrupt</description>
- <value>58</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream3</name>
- <description>DMA2 Stream3 global interrupt</description>
- <value>59</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream4</name>
- <description>DMA2 Stream4 global interrupt</description>
- <value>60</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream5</name>
- <description>DMA2 Stream5 global interrupt</description>
- <value>68</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream6</name>
- <description>DMA2 Stream6 global interrupt</description>
- <value>69</value>
- </interrupt>
- <interrupt>
- <name>DMA2_Stream7</name>
- <description>DMA2 Stream7 global interrupt</description>
- <value>70</value>
- </interrupt>
- <registers>
- <register>
- <name>LISR</name>
- <displayName>LISR</displayName>
- <description>low interrupt status register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TCIF3</name>
- <description>Stream x transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF3</name>
- <description>Stream x half transfer interrupt flag (x=3..0)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF3</name>
- <description>Stream x transfer error interrupt flag (x=3..0)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF3</name>
- <description>Stream x direct mode error interrupt flag (x=3..0)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF3</name>
- <description>Stream x FIFO error interrupt flag (x=3..0)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF2</name>
- <description>Stream x transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF2</name>
- <description>Stream x half transfer interrupt flag (x=3..0)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF2</name>
- <description>Stream x transfer error interrupt flag (x=3..0)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF2</name>
- <description>Stream x direct mode error interrupt flag (x=3..0)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF2</name>
- <description>Stream x FIFO error interrupt flag (x=3..0)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF1</name>
- <description>Stream x transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF1</name>
- <description>Stream x half transfer interrupt flag (x=3..0)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF1</name>
- <description>Stream x transfer error interrupt flag (x=3..0)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF1</name>
- <description>Stream x direct mode error interrupt flag (x=3..0)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF1</name>
- <description>Stream x FIFO error interrupt flag (x=3..0)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF0</name>
- <description>Stream x transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF0</name>
- <description>Stream x half transfer interrupt flag (x=3..0)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF0</name>
- <description>Stream x transfer error interrupt flag (x=3..0)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF0</name>
- <description>Stream x direct mode error interrupt flag (x=3..0)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF0</name>
- <description>Stream x FIFO error interrupt flag (x=3..0)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HISR</name>
- <displayName>HISR</displayName>
- <description>high interrupt status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TCIF7</name>
- <description>Stream x transfer complete interrupt flag (x=7..4)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF7</name>
- <description>Stream x half transfer interrupt flag (x=7..4)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF7</name>
- <description>Stream x transfer error interrupt flag (x=7..4)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF7</name>
- <description>Stream x direct mode error interrupt flag (x=7..4)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF7</name>
- <description>Stream x FIFO error interrupt flag (x=7..4)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF6</name>
- <description>Stream x transfer complete interrupt flag (x=7..4)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF6</name>
- <description>Stream x half transfer interrupt flag (x=7..4)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF6</name>
- <description>Stream x transfer error interrupt flag (x=7..4)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF6</name>
- <description>Stream x direct mode error interrupt flag (x=7..4)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF6</name>
- <description>Stream x FIFO error interrupt flag (x=7..4)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF5</name>
- <description>Stream x transfer complete interrupt flag (x=7..4)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF5</name>
- <description>Stream x half transfer interrupt flag (x=7..4)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF5</name>
- <description>Stream x transfer error interrupt flag (x=7..4)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF5</name>
- <description>Stream x direct mode error interrupt flag (x=7..4)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF5</name>
- <description>Stream x FIFO error interrupt flag (x=7..4)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF4</name>
- <description>Stream x transfer complete interrupt flag (x=7..4)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIF4</name>
- <description>Stream x half transfer interrupt flag (x=7..4)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF4</name>
- <description>Stream x transfer error interrupt flag (x=7..4)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIF4</name>
- <description>Stream x direct mode error interrupt flag (x=7..4)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEIF4</name>
- <description>Stream x FIFO error interrupt flag (x=7..4)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LIFCR</name>
- <displayName>LIFCR</displayName>
- <description>low interrupt flag clear register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CTCIF3</name>
- <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF3</name>
- <description>Stream x clear half transfer interrupt flag (x = 3..0)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF3</name>
- <description>Stream x clear transfer error interrupt flag (x = 3..0)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF3</name>
- <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF3</name>
- <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF2</name>
- <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF2</name>
- <description>Stream x clear half transfer interrupt flag (x = 3..0)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF2</name>
- <description>Stream x clear transfer error interrupt flag (x = 3..0)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF2</name>
- <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF2</name>
- <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF1</name>
- <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF1</name>
- <description>Stream x clear half transfer interrupt flag (x = 3..0)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF1</name>
- <description>Stream x clear transfer error interrupt flag (x = 3..0)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF1</name>
- <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF1</name>
- <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF0</name>
- <description>Stream x clear transfer complete interrupt flag (x = 3..0)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF0</name>
- <description>Stream x clear half transfer interrupt flag (x = 3..0)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF0</name>
- <description>Stream x clear transfer error interrupt flag (x = 3..0)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF0</name>
- <description>Stream x clear direct mode error interrupt flag (x = 3..0)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF0</name>
- <description>Stream x clear FIFO error interrupt flag (x = 3..0)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HIFCR</name>
- <displayName>HIFCR</displayName>
- <description>high interrupt flag clear register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CTCIF7</name>
- <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF7</name>
- <description>Stream x clear half transfer interrupt flag (x = 7..4)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF7</name>
- <description>Stream x clear transfer error interrupt flag (x = 7..4)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF7</name>
- <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF7</name>
- <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF6</name>
- <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF6</name>
- <description>Stream x clear half transfer interrupt flag (x = 7..4)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF6</name>
- <description>Stream x clear transfer error interrupt flag (x = 7..4)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF6</name>
- <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF6</name>
- <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF5</name>
- <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF5</name>
- <description>Stream x clear half transfer interrupt flag (x = 7..4)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF5</name>
- <description>Stream x clear transfer error interrupt flag (x = 7..4)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF5</name>
- <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF5</name>
- <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF4</name>
- <description>Stream x clear transfer complete interrupt flag (x = 7..4)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHTIF4</name>
- <description>Stream x clear half transfer interrupt flag (x = 7..4)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF4</name>
- <description>Stream x clear transfer error interrupt flag (x = 7..4)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CDMEIF4</name>
- <description>Stream x clear direct mode error interrupt flag (x = 7..4)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFEIF4</name>
- <description>Stream x clear FIFO error interrupt flag (x = 7..4)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0CR</name>
- <displayName>S0CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0NDTR</name>
- <displayName>S0NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0PAR</name>
- <displayName>S0PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0M0AR</name>
- <displayName>S0M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0M1AR</name>
- <displayName>S0M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S0FCR</name>
- <displayName>S0FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S1CR</name>
- <displayName>S1CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S1NDTR</name>
- <displayName>S1NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S1PAR</name>
- <displayName>S1PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S1M0AR</name>
- <displayName>S1M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S1M1AR</name>
- <displayName>S1M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S1FCR</name>
- <displayName>S1FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S2CR</name>
- <displayName>S2CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S2NDTR</name>
- <displayName>S2NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S2PAR</name>
- <displayName>S2PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S2M0AR</name>
- <displayName>S2M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S2M1AR</name>
- <displayName>S2M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S2FCR</name>
- <displayName>S2FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S3CR</name>
- <displayName>S3CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S3NDTR</name>
- <displayName>S3NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x5C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S3PAR</name>
- <displayName>S3PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S3M0AR</name>
- <displayName>S3M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x64</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S3M1AR</name>
- <displayName>S3M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x68</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S3FCR</name>
- <displayName>S3FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x6C</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S4CR</name>
- <displayName>S4CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x70</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S4NDTR</name>
- <displayName>S4NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x74</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S4PAR</name>
- <displayName>S4PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x78</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S4M0AR</name>
- <displayName>S4M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x7C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S4M1AR</name>
- <displayName>S4M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S4FCR</name>
- <displayName>S4FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S5CR</name>
- <displayName>S5CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S5NDTR</name>
- <displayName>S5NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S5PAR</name>
- <displayName>S5PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0x90</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S5M0AR</name>
- <displayName>S5M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0x94</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S5M1AR</name>
- <displayName>S5M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0x98</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S5FCR</name>
- <displayName>S5FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0x9C</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S6CR</name>
- <displayName>S6CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0xA0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S6NDTR</name>
- <displayName>S6NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0xA4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S6PAR</name>
- <displayName>S6PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0xA8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S6M0AR</name>
- <displayName>S6M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0xAC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S6M1AR</name>
- <displayName>S6M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0xB0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S6FCR</name>
- <displayName>S6FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0xB4</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>S7CR</name>
- <displayName>S7CR</displayName>
- <description>stream x configuration register</description>
- <addressOffset>0xB8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHSEL</name>
- <description>Channel selection</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MBURST</name>
- <description>Memory burst transfer configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PBURST</name>
- <description>Peripheral burst transfer configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CT</name>
- <description>Current target (only in double buffer mode)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBM</name>
- <description>Double buffer mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PL</name>
- <description>Priority level</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PINCOS</name>
- <description>Peripheral increment offset size</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSIZE</name>
- <description>Memory data size</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Peripheral data size</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MINC</name>
- <description>Memory increment mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PINC</name>
- <description>Peripheral increment mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CIRC</name>
- <description>Circular mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Data transfer direction</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PFCTRL</name>
- <description>Peripheral flow controller</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HTIE</name>
- <description>Half transfer interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMEIE</name>
- <description>Direct mode error interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Stream enable / flag stream ready when read low</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S7NDTR</name>
- <displayName>S7NDTR</displayName>
- <description>stream x number of data register</description>
- <addressOffset>0xBC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NDT</name>
- <description>Number of data items to transfer</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S7PAR</name>
- <displayName>S7PAR</displayName>
- <description>stream x peripheral address register</description>
- <addressOffset>0xC0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PA</name>
- <description>Peripheral address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S7M0AR</name>
- <displayName>S7M0AR</displayName>
- <description>stream x memory 0 address register</description>
- <addressOffset>0xC4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M0A</name>
- <description>Memory 0 address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S7M1AR</name>
- <displayName>S7M1AR</displayName>
- <description>stream x memory 1 address register</description>
- <addressOffset>0xC8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>M1A</name>
- <description>Memory 1 address (used in case of Double buffer mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>S7FCR</name>
- <displayName>S7FCR</displayName>
- <description>stream x FIFO control register</description>
- <addressOffset>0xCC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000021</resetValue>
- <fields>
- <field>
- <name>FEIE</name>
- <description>FIFO error interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FS</name>
- <description>FIFO status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMDIS</name>
- <description>Direct mode disable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="DMA2">
- <name>DMA1</name>
- <baseAddress>0x40026000</baseAddress>
- <interrupt>
- <name>DMA1_Stream0</name>
- <description>DMA1 Stream0 global interrupt</description>
- <value>11</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream1</name>
- <description>DMA1 Stream1 global interrupt</description>
- <value>12</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream2</name>
- <description>DMA1 Stream2 global interrupt</description>
- <value>13</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream3</name>
- <description>DMA1 Stream3 global interrupt</description>
- <value>14</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream4</name>
- <description>DMA1 Stream4 global interrupt</description>
- <value>15</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream5</name>
- <description>DMA1 Stream5 global interrupt</description>
- <value>16</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream6</name>
- <description>DMA1 Stream6 global interrupt</description>
- <value>17</value>
- </interrupt>
- <interrupt>
- <name>DMA1_Stream7</name>
- <description>DMA1 Stream7 global interrupt</description>
- <value>47</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>RCC</name>
- <description>Reset and clock control</description>
- <groupName>RCC</groupName>
- <baseAddress>0x40023800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>RCC</name>
- <description>RCC global interrupt</description>
- <value>5</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>clock control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000083</resetValue>
- <fields>
- <field>
- <name>PLLI2SRDY</name>
- <description>PLLI2S clock ready flag</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PLLI2SON</name>
- <description>PLLI2S enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PLLRDY</name>
- <description>Main PLL (PLL) clock ready flag</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PLLON</name>
- <description>Main PLL (PLL) enable</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CSSON</name>
- <description>Clock security system enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSEBYP</name>
- <description>HSE clock bypass</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSERDY</name>
- <description>HSE clock ready flag</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HSEON</name>
- <description>HSE clock enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSICAL</name>
- <description>Internal high-speed clock calibration</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HSITRIM</name>
- <description>Internal high-speed clock trimming</description>
- <bitOffset>3</bitOffset>
- <bitWidth>5</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSIRDY</name>
- <description>Internal high-speed clock ready flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HSION</name>
- <description>Internal high-speed clock enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>PLLCFGR</name>
- <displayName>PLLCFGR</displayName>
- <description>PLL configuration register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x24003010</resetValue>
- <fields>
- <field>
- <name>PLLQ3</name>
- <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLQ2</name>
- <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLQ1</name>
- <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLQ0</name>
- <description>Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLSRC</name>
- <description>Main PLL(PLL) and audio PLL (PLLI2S) entry clock source</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLP1</name>
- <description>Main PLL (PLL) division factor for main system clock</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLP0</name>
- <description>Main PLL (PLL) division factor for main system clock</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN8</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN7</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN6</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN5</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN4</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN3</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN2</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN1</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLN0</name>
- <description>Main PLL (PLL) multiplication factor for VCO</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM5</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM4</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM3</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM2</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM1</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLLM0</name>
- <description>Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CFGR</name>
- <displayName>CFGR</displayName>
- <description>clock configuration register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCO2</name>
- <description>Microcontroller clock output 2</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MCO2PRE</name>
- <description>MCO2 prescaler</description>
- <bitOffset>27</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MCO1PRE</name>
- <description>MCO1 prescaler</description>
- <bitOffset>24</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>I2SSRC</name>
- <description>I2S clock selection</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MCO1</name>
- <description>Microcontroller clock output 1</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RTCPRE</name>
- <description>HSE division factor for RTC clock</description>
- <bitOffset>16</bitOffset>
- <bitWidth>5</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PPRE2</name>
- <description>APB high-speed prescaler (APB2)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PPRE1</name>
- <description>APB Low speed prescaler (APB1)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HPRE</name>
- <description>AHB prescaler</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SWS1</name>
- <description>System clock switch status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SWS0</name>
- <description>System clock switch status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SW1</name>
- <description>System clock switch</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SW0</name>
- <description>System clock switch</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CIR</name>
- <displayName>CIR</displayName>
- <description>clock interrupt register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CSSC</name>
- <description>Clock security system interrupt clear</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>PLLSAIRDYC</name>
- <description>PLLSAI Ready Interrupt Clear</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>PLLI2SRDYC</name>
- <description>PLLI2S ready interrupt clear</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>PLLRDYC</name>
- <description>Main PLL(PLL) ready interrupt clear</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>HSERDYC</name>
- <description>HSE ready interrupt clear</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>HSIRDYC</name>
- <description>HSI ready interrupt clear</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>LSERDYC</name>
- <description>LSE ready interrupt clear</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>LSIRDYC</name>
- <description>LSI ready interrupt clear</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>PLLSAIRDYIE</name>
- <description>PLLSAI Ready Interrupt Enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PLLI2SRDYIE</name>
- <description>PLLI2S ready interrupt enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PLLRDYIE</name>
- <description>Main PLL (PLL) ready interrupt enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSERDYIE</name>
- <description>HSE ready interrupt enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSIRDYIE</name>
- <description>HSI ready interrupt enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LSERDYIE</name>
- <description>LSE ready interrupt enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LSIRDYIE</name>
- <description>LSI ready interrupt enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CSSF</name>
- <description>Clock security system interrupt flag</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PLLSAIRDYF</name>
- <description>PLLSAI ready interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PLLI2SRDYF</name>
- <description>PLLI2S ready interrupt flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PLLRDYF</name>
- <description>Main PLL (PLL) ready interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HSERDYF</name>
- <description>HSE ready interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HSIRDYF</name>
- <description>HSI ready interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LSERDYF</name>
- <description>LSE ready interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LSIRDYF</name>
- <description>LSI ready interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB1RSTR</name>
- <displayName>AHB1RSTR</displayName>
- <description>AHB1 peripheral reset register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OTGHSRST</name>
- <description>USB OTG HS module reset</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACRST</name>
- <description>Ethernet MAC reset</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2DRST</name>
- <description>DMA2D reset</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2RST</name>
- <description>DMA2 reset</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA1RST</name>
- <description>DMA2 reset</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCRST</name>
- <description>CRC reset</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOKRST</name>
- <description>IO port K reset</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOJRST</name>
- <description>IO port J reset</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOIRST</name>
- <description>IO port I reset</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOHRST</name>
- <description>IO port H reset</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOGRST</name>
- <description>IO port G reset</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOFRST</name>
- <description>IO port F reset</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOERST</name>
- <description>IO port E reset</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIODRST</name>
- <description>IO port D reset</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOCRST</name>
- <description>IO port C reset</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOBRST</name>
- <description>IO port B reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOARST</name>
- <description>IO port A reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB2RSTR</name>
- <displayName>AHB2RSTR</displayName>
- <description>AHB2 peripheral reset register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OTGFSRST</name>
- <description>USB OTG FS module reset</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RNGRST</name>
- <description>Random number generator module reset</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HSAHRST</name>
- <description>Hash module reset</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRYPRST</name>
- <description>Cryptographic module reset</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCMIRST</name>
- <description>Camera interface reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB3RSTR</name>
- <displayName>AHB3RSTR</displayName>
- <description>AHB3 peripheral reset register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FMCRST</name>
- <description>Flexible memory controller module reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>QSPIRST</name>
- <description>Quad SPI memory controller reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB1RSTR</name>
- <displayName>APB1RSTR</displayName>
- <description>APB1 peripheral reset register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIM2RST</name>
- <description>TIM2 reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM3RST</name>
- <description>TIM3 reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM4RST</name>
- <description>TIM4 reset</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM5RST</name>
- <description>TIM5 reset</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM6RST</name>
- <description>TIM6 reset</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM7RST</name>
- <description>TIM7 reset</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM12RST</name>
- <description>TIM12 reset</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM13RST</name>
- <description>TIM13 reset</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM14RST</name>
- <description>TIM14 reset</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WWDGRST</name>
- <description>Window watchdog reset</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI2RST</name>
- <description>SPI 2 reset</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI3RST</name>
- <description>SPI 3 reset</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART2RST</name>
- <description>USART 2 reset</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART3RST</name>
- <description>USART 3 reset</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART4RST</name>
- <description>USART 4 reset</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART5RST</name>
- <description>USART 5 reset</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C1RST</name>
- <description>I2C 1 reset</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C2RST</name>
- <description>I2C 2 reset</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C3RST</name>
- <description>I2C3 reset</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN1RST</name>
- <description>CAN1 reset</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN2RST</name>
- <description>CAN2 reset</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWRRST</name>
- <description>Power interface reset</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DACRST</name>
- <description>DAC reset</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART7RST</name>
- <description>UART7 reset</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART8RST</name>
- <description>UART8 reset</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPDIFRXRST</name>
- <description>SPDIF-RX reset</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CECRST</name>
- <description>HDMI-CEC reset</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LPTIM1RST</name>
- <description>Low power timer 1 reset</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C4RST</name>
- <description>I2C 4 reset</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB2RSTR</name>
- <displayName>APB2RSTR</displayName>
- <description>APB2 peripheral reset register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIM1RST</name>
- <description>TIM1 reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM8RST</name>
- <description>TIM8 reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART1RST</name>
- <description>USART1 reset</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART6RST</name>
- <description>USART6 reset</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADCRST</name>
- <description>ADC interface reset (common to all ADCs)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI1RST</name>
- <description>SPI 1 reset</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI4RST</name>
- <description>SPI4 reset</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYSCFGRST</name>
- <description>System configuration controller reset</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM9RST</name>
- <description>TIM9 reset</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM10RST</name>
- <description>TIM10 reset</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM11RST</name>
- <description>TIM11 reset</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI5RST</name>
- <description>SPI5 reset</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI6RST</name>
- <description>SPI6 reset</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI1RST</name>
- <description>SAI1 reset</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LTDCRST</name>
- <description>LTDC reset</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI2RST</name>
- <description>SAI2 reset</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDMMC1RST</name>
- <description>SDMMC1 reset</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB1ENR</name>
- <displayName>AHB1ENR</displayName>
- <description>AHB1 peripheral clock register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00100000</resetValue>
- <fields>
- <field>
- <name>OTGHSULPIEN</name>
- <description>USB OTG HSULPI clock enable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTGHSEN</name>
- <description>USB OTG HS clock enable</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACPTPEN</name>
- <description>Ethernet PTP clock enable</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACRXEN</name>
- <description>Ethernet Reception clock enable</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACTXEN</name>
- <description>Ethernet Transmission clock enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACEN</name>
- <description>Ethernet MAC clock enable</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2DEN</name>
- <description>DMA2D clock enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2EN</name>
- <description>DMA2 clock enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA1EN</name>
- <description>DMA1 clock enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCMDATARAMEN</name>
- <description>CCM data RAM clock enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BKPSRAMEN</name>
- <description>Backup SRAM interface clock enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCEN</name>
- <description>CRC clock enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOKEN</name>
- <description>IO port K clock enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOJEN</name>
- <description>IO port J clock enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOIEN</name>
- <description>IO port I clock enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOHEN</name>
- <description>IO port H clock enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOGEN</name>
- <description>IO port G clock enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOFEN</name>
- <description>IO port F clock enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOEEN</name>
- <description>IO port E clock enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIODEN</name>
- <description>IO port D clock enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOCEN</name>
- <description>IO port C clock enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOBEN</name>
- <description>IO port B clock enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOAEN</name>
- <description>IO port A clock enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB2ENR</name>
- <displayName>AHB2ENR</displayName>
- <description>AHB2 peripheral clock enable register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OTGFSEN</name>
- <description>USB OTG FS clock enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RNGEN</name>
- <description>Random number generator clock enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HASHEN</name>
- <description>Hash modules clock enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRYPEN</name>
- <description>Cryptographic modules clock enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCMIEN</name>
- <description>Camera interface enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB3ENR</name>
- <displayName>AHB3ENR</displayName>
- <description>AHB3 peripheral clock enable register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FMCEN</name>
- <description>Flexible memory controller module clock enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>QSPIEN</name>
- <description>Quad SPI memory controller clock enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB1ENR</name>
- <displayName>APB1ENR</displayName>
- <description>APB1 peripheral clock enable register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIM2EN</name>
- <description>TIM2 clock enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM3EN</name>
- <description>TIM3 clock enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM4EN</name>
- <description>TIM4 clock enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM5EN</name>
- <description>TIM5 clock enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM6EN</name>
- <description>TIM6 clock enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM7EN</name>
- <description>TIM7 clock enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM12EN</name>
- <description>TIM12 clock enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM13EN</name>
- <description>TIM13 clock enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM14EN</name>
- <description>TIM14 clock enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WWDGEN</name>
- <description>Window watchdog clock enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI2EN</name>
- <description>SPI2 clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI3EN</name>
- <description>SPI3 clock enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART2EN</name>
- <description>USART 2 clock enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART3EN</name>
- <description>USART3 clock enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART4EN</name>
- <description>UART4 clock enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART5EN</name>
- <description>UART5 clock enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C1EN</name>
- <description>I2C1 clock enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C2EN</name>
- <description>I2C2 clock enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C3EN</name>
- <description>I2C3 clock enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN1EN</name>
- <description>CAN 1 clock enable</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN2EN</name>
- <description>CAN 2 clock enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWREN</name>
- <description>Power interface clock enable</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DACEN</name>
- <description>DAC interface clock enable</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART7ENR</name>
- <description>UART7 clock enable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART8ENR</name>
- <description>UART8 clock enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPDIFRXEN</name>
- <description>SPDIF-RX clock enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CECEN</name>
- <description>HDMI-CEN clock enable</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LPTMI1EN</name>
- <description>Low power timer 1 clock enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C4EN</name>
- <description>I2C4 clock enable</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB2ENR</name>
- <displayName>APB2ENR</displayName>
- <description>APB2 peripheral clock enable register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIM1EN</name>
- <description>TIM1 clock enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM8EN</name>
- <description>TIM8 clock enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART1EN</name>
- <description>USART1 clock enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART6EN</name>
- <description>USART6 clock enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC1EN</name>
- <description>ADC1 clock enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC2EN</name>
- <description>ADC2 clock enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC3EN</name>
- <description>ADC3 clock enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI1EN</name>
- <description>SPI1 clock enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI4ENR</name>
- <description>SPI4 clock enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYSCFGEN</name>
- <description>System configuration controller clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM9EN</name>
- <description>TIM9 clock enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM10EN</name>
- <description>TIM10 clock enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM11EN</name>
- <description>TIM11 clock enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI5ENR</name>
- <description>SPI5 clock enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI6ENR</name>
- <description>SPI6 clock enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI1EN</name>
- <description>SAI1 clock enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LTDCEN</name>
- <description>LTDC clock enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI2EN</name>
- <description>SAI2 clock enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDMMC1EN</name>
- <description>SDMMC1 clock enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB1LPENR</name>
- <displayName>AHB1LPENR</displayName>
- <description>AHB1 peripheral clock enable in low power mode register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x7E6791FF</resetValue>
- <fields>
- <field>
- <name>GPIOALPEN</name>
- <description>IO port A clock enable during sleep mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOBLPEN</name>
- <description>IO port B clock enable during Sleep mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOCLPEN</name>
- <description>IO port C clock enable during Sleep mode</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIODLPEN</name>
- <description>IO port D clock enable during Sleep mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOELPEN</name>
- <description>IO port E clock enable during Sleep mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOFLPEN</name>
- <description>IO port F clock enable during Sleep mode</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOGLPEN</name>
- <description>IO port G clock enable during Sleep mode</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOHLPEN</name>
- <description>IO port H clock enable during Sleep mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOILPEN</name>
- <description>IO port I clock enable during Sleep mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOJLPEN</name>
- <description>IO port J clock enable during Sleep mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GPIOKLPEN</name>
- <description>IO port K clock enable during Sleep mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCLPEN</name>
- <description>CRC clock enable during Sleep mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FLITFLPEN</name>
- <description>Flash interface clock enable during Sleep mode</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SRAM1LPEN</name>
- <description>SRAM 1interface clock enable during Sleep mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SRAM2LPEN</name>
- <description>SRAM 2 interface clock enable during Sleep mode</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BKPSRAMLPEN</name>
- <description>Backup SRAM interface clock enable during Sleep mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SRAM3LPEN</name>
- <description>SRAM 3 interface clock enable during Sleep mode</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA1LPEN</name>
- <description>DMA1 clock enable during Sleep mode</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2LPEN</name>
- <description>DMA2 clock enable during Sleep mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA2DLPEN</name>
- <description>DMA2D clock enable during Sleep mode</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACLPEN</name>
- <description>Ethernet MAC clock enable during Sleep mode</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACTXLPEN</name>
- <description>Ethernet transmission clock enable during Sleep mode</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACRXLPEN</name>
- <description>Ethernet reception clock enable during Sleep mode</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETHMACPTPLPEN</name>
- <description>Ethernet PTP clock enable during Sleep mode</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTGHSLPEN</name>
- <description>USB OTG HS clock enable during Sleep mode</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTGHSULPILPEN</name>
- <description>USB OTG HS ULPI clock enable during Sleep mode</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB2LPENR</name>
- <displayName>AHB2LPENR</displayName>
- <description>AHB2 peripheral clock enable in low power mode register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000000F1</resetValue>
- <fields>
- <field>
- <name>OTGFSLPEN</name>
- <description>USB OTG FS clock enable during Sleep mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RNGLPEN</name>
- <description>Random number generator clock enable during Sleep mode</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HASHLPEN</name>
- <description>Hash modules clock enable during Sleep mode</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRYPLPEN</name>
- <description>Cryptography modules clock enable during Sleep mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCMILPEN</name>
- <description>Camera interface enable during Sleep mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHB3LPENR</name>
- <displayName>AHB3LPENR</displayName>
- <description>AHB3 peripheral clock enable in low power mode register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000001</resetValue>
- <fields>
- <field>
- <name>FMCLPEN</name>
- <description>Flexible memory controller module clock enable during Sleep mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>QSPILPEN</name>
- <description>Quand SPI memory controller clock enable during Sleep mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB1LPENR</name>
- <displayName>APB1LPENR</displayName>
- <description>APB1 peripheral clock enable in low power mode register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x36FEC9FF</resetValue>
- <fields>
- <field>
- <name>TIM2LPEN</name>
- <description>TIM2 clock enable during Sleep mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM3LPEN</name>
- <description>TIM3 clock enable during Sleep mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM4LPEN</name>
- <description>TIM4 clock enable during Sleep mode</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM5LPEN</name>
- <description>TIM5 clock enable during Sleep mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM6LPEN</name>
- <description>TIM6 clock enable during Sleep mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM7LPEN</name>
- <description>TIM7 clock enable during Sleep mode</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM12LPEN</name>
- <description>TIM12 clock enable during Sleep mode</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM13LPEN</name>
- <description>TIM13 clock enable during Sleep mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM14LPEN</name>
- <description>TIM14 clock enable during Sleep mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WWDGLPEN</name>
- <description>Window watchdog clock enable during Sleep mode</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI2LPEN</name>
- <description>SPI2 clock enable during Sleep mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI3LPEN</name>
- <description>SPI3 clock enable during Sleep mode</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART2LPEN</name>
- <description>USART2 clock enable during Sleep mode</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART3LPEN</name>
- <description>USART3 clock enable during Sleep mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART4LPEN</name>
- <description>UART4 clock enable during Sleep mode</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART5LPEN</name>
- <description>UART5 clock enable during Sleep mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C1LPEN</name>
- <description>I2C1 clock enable during Sleep mode</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C2LPEN</name>
- <description>I2C2 clock enable during Sleep mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C3LPEN</name>
- <description>I2C3 clock enable during Sleep mode</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN1LPEN</name>
- <description>CAN 1 clock enable during Sleep mode</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAN2LPEN</name>
- <description>CAN 2 clock enable during Sleep mode</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWRLPEN</name>
- <description>Power interface clock enable during Sleep mode</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DACLPEN</name>
- <description>DAC interface clock enable during Sleep mode</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART7LPEN</name>
- <description>UART7 clock enable during Sleep mode</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UART8LPEN</name>
- <description>UART8 clock enable during Sleep mode</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPDIFRXLPEN</name>
- <description>SPDIF-RX clock enable during sleep mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CECLPEN</name>
- <description>HDMI-CEN clock enable during Sleep mode</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LPTIM1LPEN</name>
- <description>low power timer 1 clock enable during Sleep mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2C4LPEN</name>
- <description>I2C4 clock enable during Sleep mode</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>APB2LPENR</name>
- <displayName>APB2LPENR</displayName>
- <description>APB2 peripheral clock enabled in low power mode register</description>
- <addressOffset>0x64</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00075F33</resetValue>
- <fields>
- <field>
- <name>TIM1LPEN</name>
- <description>TIM1 clock enable during Sleep mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM8LPEN</name>
- <description>TIM8 clock enable during Sleep mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART1LPEN</name>
- <description>USART1 clock enable during Sleep mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USART6LPEN</name>
- <description>USART6 clock enable during Sleep mode</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC1LPEN</name>
- <description>ADC1 clock enable during Sleep mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC2LPEN</name>
- <description>ADC2 clock enable during Sleep mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC3LPEN</name>
- <description>ADC 3 clock enable during Sleep mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI1LPEN</name>
- <description>SPI 1 clock enable during Sleep mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI4LPEN</name>
- <description>SPI 4 clock enable during Sleep mode</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYSCFGLPEN</name>
- <description>System configuration controller clock enable during Sleep mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM9LPEN</name>
- <description>TIM9 clock enable during sleep mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM10LPEN</name>
- <description>TIM10 clock enable during Sleep mode</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIM11LPEN</name>
- <description>TIM11 clock enable during Sleep mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI5LPEN</name>
- <description>SPI 5 clock enable during Sleep mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPI6LPEN</name>
- <description>SPI 6 clock enable during Sleep mode</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI1LPEN</name>
- <description>SAI1 clock enable during sleep mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LTDCLPEN</name>
- <description>LTDC clock enable during sleep mode</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAI2LPEN</name>
- <description>SAI2 clock enable during sleep mode</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDMMC1LPEN</name>
- <description>SDMMC1 clock enable during Sleep mode</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BDCR</name>
- <displayName>BDCR</displayName>
- <description>Backup domain control register</description>
- <addressOffset>0x70</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BDRST</name>
- <description>Backup domain software reset</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RTCEN</name>
- <description>RTC clock enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RTCSEL1</name>
- <description>RTC clock source selection</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RTCSEL0</name>
- <description>RTC clock source selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LSEBYP</name>
- <description>External low-speed oscillator bypass</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LSERDY</name>
- <description>External low-speed oscillator ready</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LSEON</name>
- <description>External low-speed oscillator enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR</name>
- <displayName>CSR</displayName>
- <description>clock control & status register</description>
- <addressOffset>0x74</addressOffset>
- <size>0x20</size>
- <resetValue>0x0E000000</resetValue>
- <fields>
- <field>
- <name>LPWRRSTF</name>
- <description>Low-power reset flag</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WWDGRSTF</name>
- <description>Window watchdog reset flag</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WDGRSTF</name>
- <description>Independent watchdog reset flag</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SFTRSTF</name>
- <description>Software reset flag</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PORRSTF</name>
- <description>POR/PDR reset flag</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PADRSTF</name>
- <description>PIN reset flag</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BORRSTF</name>
- <description>BOR reset flag</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RMVF</name>
- <description>Remove reset flag</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LSIRDY</name>
- <description>Internal low-speed oscillator ready</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LSION</name>
- <description>Internal low-speed oscillator enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SSCGR</name>
- <displayName>SSCGR</displayName>
- <description>spread spectrum clock generation register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SSCGEN</name>
- <description>Spread spectrum modulation enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPREADSEL</name>
- <description>Spread Select</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INCSTEP</name>
- <description>Incrementation step</description>
- <bitOffset>13</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- <field>
- <name>MODPER</name>
- <description>Modulation period</description>
- <bitOffset>0</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PLLI2SCFGR</name>
- <displayName>PLLI2SCFGR</displayName>
- <description>PLLI2S configuration register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x20003000</resetValue>
- <fields>
- <field>
- <name>PLLI2SR</name>
- <description>PLLI2S division factor for I2S clocks</description>
- <bitOffset>28</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>PLLI2SQ</name>
- <description>PLLI2S division factor for SAI1 clock</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PLLI2SN</name>
- <description>PLLI2S multiplication factor for VCO</description>
- <bitOffset>6</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PLLSAICFGR</name>
- <displayName>PLLSAICFGR</displayName>
- <description>PLL configuration register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x20003000</resetValue>
- <fields>
- <field>
- <name>PLLSAIN</name>
- <description>PLLSAI division factor for VCO</description>
- <bitOffset>6</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>PLLSAIP</name>
- <description>PLLSAI division factor for 48MHz clock</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PLLSAIQ</name>
- <description>PLLSAI division factor for SAI clock</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PLLSAIR</name>
- <description>PLLSAI division factor for LCD clock</description>
- <bitOffset>28</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DKCFGR1</name>
- <displayName>DKCFGR1</displayName>
- <description>dedicated clocks configuration register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x20003000</resetValue>
- <fields>
- <field>
- <name>PLLI2SDIV</name>
- <description>PLLI2S division factor for SAI1 clock</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>PLLSAIDIVQ</name>
- <description>PLLSAI division factor for SAI1 clock</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>PLLSAIDIVR</name>
- <description>division factor for LCD_CLK</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>SAI1SEL</name>
- <description>SAI1 clock source selection</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>SAI2SEL</name>
- <description>SAI2 clock source selection</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TIMPRE</name>
- <description>Timers clocks prescalers selection</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DKCFGR2</name>
- <displayName>DKCFGR2</displayName>
- <description>dedicated clocks configuration register</description>
- <addressOffset>0x90</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x20003000</resetValue>
- <fields>
- <field>
- <name>USART1SEL</name>
- <description>USART 1 clock source selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>USART2SEL</name>
- <description>USART 2 clock source selection</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>USART3SEL</name>
- <description>USART 3 clock source selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>UART4SEL</name>
- <description>UART 4 clock source selection</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>UART5SEL</name>
- <description>UART 5 clock source selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>USART6SEL</name>
- <description>USART 6 clock source selection</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>UART7SEL</name>
- <description>UART 7 clock source selection</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>UART8SEL</name>
- <description>UART 8 clock source selection</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>I2C1SEL</name>
- <description>I2C1 clock source selection</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>I2C2SEL</name>
- <description>I2C2 clock source selection</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>I2C3SEL</name>
- <description>I2C3 clock source selection</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>I2C4SEL</name>
- <description>I2C4 clock source selection</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>LPTIM1SEL</name>
- <description>Low power timer 1 clock source selection</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CECSEL</name>
- <description>HDMI-CEC clock source selection</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CK48MSEL</name>
- <description>48MHz clock source selection</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDMMCSEL</name>
- <description>SDMMC clock source selection</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>GPIOD</name>
- <description>General-purpose I/Os</description>
- <groupName>GPIO</groupName>
- <baseAddress>0X40020C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MODER</name>
- <displayName>MODER</displayName>
- <description>GPIO port mode register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MODER15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTYPER</name>
- <displayName>OTYPER</displayName>
- <description>GPIO port output type register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OT15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GPIOB_OSPEEDR</name>
- <displayName>GPIOB_OSPEEDR</displayName>
- <description>GPIO port output speed register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OSPEEDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PUPDR</name>
- <displayName>PUPDR</displayName>
- <description>GPIO port pull-up/pull-down register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PUPDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IDR</name>
- <displayName>IDR</displayName>
- <description>GPIO port input data register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IDR15</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR14</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR13</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR12</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR11</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR10</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR9</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR8</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR7</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR6</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR5</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR4</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR3</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR2</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR1</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR0</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ODR</name>
- <displayName>ODR</displayName>
- <description>GPIO port output data register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ODR15</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR14</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR13</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR12</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR11</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR10</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR9</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR8</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR7</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR6</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR5</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR4</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR3</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR2</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR1</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR0</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BSRR</name>
- <displayName>BSRR</displayName>
- <description>GPIO port bit set/reset register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR15</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS15</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS14</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS13</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS12</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS11</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS10</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS9</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS8</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS7</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS6</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS5</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS4</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS3</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS2</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS1</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LCKR</name>
- <displayName>LCKR</displayName>
- <description>GPIO port configuration lock register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LCKK</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK15</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK14</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK13</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK12</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK11</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK10</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK9</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK8</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK7</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK6</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK5</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK4</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK3</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK2</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK1</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK0</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRL</name>
- <displayName>AFRL</displayName>
- <description>GPIO alternate function lowregister</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRL7</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL6</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL5</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL4</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL3</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL2</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL1</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL0</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRH</name>
- <displayName>AFRH</displayName>
- <description>GPIO alternate function high register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRH15</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH14</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH13</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH12</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH11</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH10</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH9</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH8</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BRR</name>
- <displayName>BRR</displayName>
- <description>GPIO port bit reset register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR0</name>
- <description>Port D Reset bit 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port D Reset bit 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port D Reset bit 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port D Reset bit 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port D Reset bit 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port D Reset bit 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port D Reset bit 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port D Reset bit 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port D Reset bit 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port D Reset bit 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port D Reset bit 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port D Reset bit 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port D Reset bit 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port D Reset bit 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port D Reset bit 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR15</name>
- <description>Port D Reset bit 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOC</name>
- <baseAddress>0x40020800</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOK</name>
- <baseAddress>0X40022800</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOJ</name>
- <baseAddress>0X40022400</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOI</name>
- <baseAddress>0X40022000</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOH</name>
- <baseAddress>0X40021C00</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOG</name>
- <baseAddress>0X40021800</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOF</name>
- <baseAddress>0X40021400</baseAddress>
- </peripheral>
- <peripheral derivedFrom="GPIOD">
- <name>GPIOE</name>
- <baseAddress>0X40021000</baseAddress>
- </peripheral>
- <peripheral>
- <name>GPIOB</name>
- <description>General-purpose I/Os</description>
- <groupName>GPIO</groupName>
- <baseAddress>0x40020400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MODER</name>
- <displayName>MODER</displayName>
- <description>GPIO port mode register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000280</resetValue>
- <fields>
- <field>
- <name>MODER15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTYPER</name>
- <displayName>OTYPER</displayName>
- <description>GPIO port output type register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OT15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GPIOB_OSPEEDR</name>
- <displayName>GPIOB_OSPEEDR</displayName>
- <description>GPIO port output speed register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000000C0</resetValue>
- <fields>
- <field>
- <name>OSPEEDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PUPDR</name>
- <displayName>PUPDR</displayName>
- <description>GPIO port pull-up/pull-down register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000100</resetValue>
- <fields>
- <field>
- <name>PUPDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IDR</name>
- <displayName>IDR</displayName>
- <description>GPIO port input data register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IDR15</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR14</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR13</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR12</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR11</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR10</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR9</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR8</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR7</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR6</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR5</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR4</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR3</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR2</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR1</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR0</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ODR</name>
- <displayName>ODR</displayName>
- <description>GPIO port output data register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ODR15</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR14</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR13</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR12</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR11</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR10</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR9</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR8</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR7</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR6</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR5</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR4</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR3</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR2</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR1</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR0</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BSRR</name>
- <displayName>BSRR</displayName>
- <description>GPIO port bit set/reset register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR15</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS15</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS14</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS13</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS12</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS11</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS10</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS9</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS8</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS7</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS6</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS5</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS4</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS3</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS2</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS1</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LCKR</name>
- <displayName>LCKR</displayName>
- <description>GPIO port configuration lock register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LCKK</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK15</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK14</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK13</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK12</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK11</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK10</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK9</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK8</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK7</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK6</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK5</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK4</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK3</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK2</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK1</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK0</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRL</name>
- <displayName>AFRL</displayName>
- <description>GPIO alternate function low register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRL7</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL6</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL5</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL4</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL3</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL2</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL1</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL0</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRH</name>
- <displayName>AFRH</displayName>
- <description>GPIO alternate function high register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRH15</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH14</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH13</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH12</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH11</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH10</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH9</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH8</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BRR</name>
- <displayName>BRR</displayName>
- <description>GPIO port bit reset register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR0</name>
- <description>Port B Reset bit 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port B Reset bit 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port B Reset bit 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port B Reset bit 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port B Reset bit 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port B Reset bit 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port B Reset bit 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port B Reset bit 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port B Reset bit 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port B Reset bit 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port B Reset bit 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port B Reset bit 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port B Reset bit 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port B Reset bit 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port B Reset bit 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR15</name>
- <description>Port B Reset bit 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>GPIOA</name>
- <description>General-purpose I/Os</description>
- <groupName>GPIO</groupName>
- <baseAddress>0x40020000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MODER</name>
- <displayName>MODER</displayName>
- <description>GPIO port mode register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xA8000000</resetValue>
- <fields>
- <field>
- <name>MODER15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODER0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTYPER</name>
- <displayName>OTYPER</displayName>
- <description>GPIO port output type register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OT15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OT0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GPIOB_OSPEEDR</name>
- <displayName>GPIOB_OSPEEDR</displayName>
- <description>GPIO port output speed register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OSPEEDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OSPEEDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PUPDR</name>
- <displayName>PUPDR</displayName>
- <description>GPIO port pull-up/pull-down register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x64000000</resetValue>
- <fields>
- <field>
- <name>PUPDR15</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR14</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR13</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR12</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR11</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR10</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR9</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR8</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR7</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR6</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR5</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR4</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR3</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR2</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR1</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PUPDR0</name>
- <description>Port x configuration bits (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IDR</name>
- <displayName>IDR</displayName>
- <description>GPIO port input data register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IDR15</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR14</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR13</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR12</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR11</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR10</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR9</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR8</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR7</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR6</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR5</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR4</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR3</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR2</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR1</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDR0</name>
- <description>Port input data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ODR</name>
- <displayName>ODR</displayName>
- <description>GPIO port output data register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ODR15</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR14</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR13</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR12</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR11</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR10</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR9</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR8</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR7</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR6</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR5</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR4</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR3</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR2</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR1</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODR0</name>
- <description>Port output data (y = 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BSRR</name>
- <displayName>BSRR</displayName>
- <description>GPIO port bit set/reset register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR15</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port x reset bit y (y = 0..15)</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS15</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS14</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS13</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS12</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS11</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS10</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS9</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS8</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS7</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS6</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS5</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS4</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS3</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS2</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS1</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BS0</name>
- <description>Port x set bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LCKR</name>
- <displayName>LCKR</displayName>
- <description>GPIO port configuration lock register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LCKK</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK15</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK14</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK13</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK12</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK11</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK10</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK9</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK8</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK7</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK6</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK5</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK4</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK3</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK2</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK1</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LCK0</name>
- <description>Port x lock bit y (y= 0..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRL</name>
- <displayName>AFRL</displayName>
- <description>GPIO alternate function low register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRL7</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL6</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL5</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL4</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL3</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL2</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL1</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRL0</name>
- <description>Alternate function selection for port x bit y (y = 0..7)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRH</name>
- <displayName>AFRH</displayName>
- <description>GPIO alternate function high register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AFRH15</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH14</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH13</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH12</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH11</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH10</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH9</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>AFRH8</name>
- <description>Alternate function selection for port x bit y (y = 8..15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BRR</name>
- <displayName>BRR</displayName>
- <description>GPIO port bit reset register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BR0</name>
- <description>Port A Reset bit 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR1</name>
- <description>Port A Reset bit 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR2</name>
- <description>Port A Reset bit 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR3</name>
- <description>Port A Reset bit 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR4</name>
- <description>Port A Reset bit 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR5</name>
- <description>Port A Reset bit 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR6</name>
- <description>Port A Reset bit 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR7</name>
- <description>Port A Reset bit 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR8</name>
- <description>Port A Reset bit 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR9</name>
- <description>Port A Reset bit 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR10</name>
- <description>Port A Reset bit 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR11</name>
- <description>Port A Reset bit 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR12</name>
- <description>Port A Reset bit 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR13</name>
- <description>Port A Reset bit 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR14</name>
- <description>Port A Reset bit 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR15</name>
- <description>Port A Reset bit 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SYSCFG</name>
- <description>System configuration controller</description>
- <groupName>SYSCFG</groupName>
- <baseAddress>0x40013800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MEMRM</name>
- <displayName>MEMRM</displayName>
- <description>memory remap register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MEM_MODE</name>
- <description>Memory mapping selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>FB_MODE</name>
- <description>Flash bank mode selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWP_FMC</name>
- <description>FMC memory mapping swap</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PMC</name>
- <displayName>PMC</displayName>
- <description>peripheral mode configuration register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MII_RMII_SEL</name>
- <description>Ethernet PHY interface selection</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC1DC2</name>
- <description>ADC1DC2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC2DC2</name>
- <description>ADC2DC2</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADC3DC2</name>
- <description>ADC3DC2</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EXTICR1</name>
- <displayName>EXTICR1</displayName>
- <description>external interrupt configuration register 1</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>EXTI3</name>
- <description>EXTI x configuration (x = 0 to 3)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI2</name>
- <description>EXTI x configuration (x = 0 to 3)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI1</name>
- <description>EXTI x configuration (x = 0 to 3)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI0</name>
- <description>EXTI x configuration (x = 0 to 3)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EXTICR2</name>
- <displayName>EXTICR2</displayName>
- <description>external interrupt configuration register 2</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>EXTI7</name>
- <description>EXTI x configuration (x = 4 to 7)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI6</name>
- <description>EXTI x configuration (x = 4 to 7)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI5</name>
- <description>EXTI x configuration (x = 4 to 7)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI4</name>
- <description>EXTI x configuration (x = 4 to 7)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EXTICR3</name>
- <displayName>EXTICR3</displayName>
- <description>external interrupt configuration register 3</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>EXTI11</name>
- <description>EXTI x configuration (x = 8 to 11)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI10</name>
- <description>EXTI10</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI9</name>
- <description>EXTI x configuration (x = 8 to 11)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI8</name>
- <description>EXTI x configuration (x = 8 to 11)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EXTICR4</name>
- <displayName>EXTICR4</displayName>
- <description>external interrupt configuration register 4</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>EXTI15</name>
- <description>EXTI x configuration (x = 12 to 15)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI14</name>
- <description>EXTI x configuration (x = 12 to 15)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI13</name>
- <description>EXTI x configuration (x = 12 to 15)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EXTI12</name>
- <description>EXTI x configuration (x = 12 to 15)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CMPCR</name>
- <displayName>CMPCR</displayName>
- <description>Compensation cell control register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>READY</name>
- <description>READY</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMP_PD</name>
- <description>Compensation cell power-down</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SPI1</name>
- <description>Serial peripheral interface</description>
- <groupName>SPI</groupName>
- <baseAddress>0x40013000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>SPI1</name>
- <description>SPI1 global interrupt</description>
- <value>35</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>BIDIMODE</name>
- <description>Bidirectional data mode enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BIDIOE</name>
- <description>Output enable in bidirectional mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCEN</name>
- <description>Hardware CRC calculation enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCNEXT</name>
- <description>CRC transfer next</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCL</name>
- <description>CRC length</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXONLY</name>
- <description>Receive only</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSM</name>
- <description>Software slave management</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSI</name>
- <description>Internal slave select</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSBFIRST</name>
- <description>Frame format</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPE</name>
- <description>SPI enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR</name>
- <description>Baud rate control</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MSTR</name>
- <description>Master selection</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPOL</name>
- <description>Clock polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPHA</name>
- <description>Clock phase</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0700</resetValue>
- <fields>
- <field>
- <name>RXDMAEN</name>
- <description>Rx buffer DMA enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXDMAEN</name>
- <description>Tx buffer DMA enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSOE</name>
- <description>SS output enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NSSP</name>
- <description>NSS pulse management</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRF</name>
- <description>Frame format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERRIE</name>
- <description>Error interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXNEIE</name>
- <description>RX buffer not empty interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXEIE</name>
- <description>Tx buffer empty interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DS</name>
- <description>Data size</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRXTH</name>
- <description>FIFO reception threshold</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LDMA_RX</name>
- <description>Last DMA transfer for reception</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LDMA_TX</name>
- <description>Last DMA transfer for transmission</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x0002</resetValue>
- <fields>
- <field>
- <name>FRE</name>
- <description>Frame format error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BSY</name>
- <description>Busy flag</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>OVR</name>
- <description>Overrun flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MODF</name>
- <description>Mode fault</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CRCERR</name>
- <description>CRC error flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>UDR</name>
- <description>Underrun flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CHSIDE</name>
- <description>Channel side</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXE</name>
- <description>Transmit buffer empty</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>RXNE</name>
- <description>Receive buffer not empty</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>FRLVL</name>
- <description>FIFO reception level</description>
- <bitOffset>9</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>FTLVL</name>
- <description>FIFO Transmission Level</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>data register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DR</name>
- <description>Data register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CRCPR</name>
- <displayName>CRCPR</displayName>
- <description>CRC polynomial register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0007</resetValue>
- <fields>
- <field>
- <name>CRCPOLY</name>
- <description>CRC polynomial register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RXCRCR</name>
- <displayName>RXCRCR</displayName>
- <description>RX CRC register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>RxCRC</name>
- <description>Rx CRC register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TXCRCR</name>
- <displayName>TXCRCR</displayName>
- <description>TX CRC register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TxCRC</name>
- <description>Tx CRC register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>I2SCFGR</name>
- <displayName>I2SCFGR</displayName>
- <description>I2S configuration register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>I2SMOD</name>
- <description>I2S mode selection</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SE</name>
- <description>I2S Enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SCFG</name>
- <description>I2S configuration mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PCMSYNC</name>
- <description>PCM frame synchronization</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SSTD</name>
- <description>I2S standard selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKPOL</name>
- <description>Steady state clock polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DATLEN</name>
- <description>Data length to be transferred</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CHLEN</name>
- <description>Channel length (number of bits per audio channel)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASTRTEN</name>
- <description>Asynchronous start enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>I2SPR</name>
- <displayName>I2SPR</displayName>
- <description>I2S prescaler register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>00000010</resetValue>
- <fields>
- <field>
- <name>MCKOE</name>
- <description>Master clock output enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODD</name>
- <description>Odd factor for the prescaler</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SDIV</name>
- <description>I2S Linear prescaler</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="SPI1">
- <name>SPI3</name>
- <baseAddress>0x40003C00</baseAddress>
- <interrupt>
- <name>SPI3</name>
- <description>SPI3 global interrupt</description>
- <value>51</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="SPI1">
- <name>SPI4</name>
- <baseAddress>0x40013400</baseAddress>
- <interrupt>
- <name>SPI4</name>
- <description>SPI 4 global interrupt</description>
- <value>84</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="SPI1">
- <name>SPI5</name>
- <baseAddress>0x40015000</baseAddress>
- <interrupt>
- <name>SPI5</name>
- <description>SPI 5 global interrupt</description>
- <value>85</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="SPI1">
- <name>SPI6</name>
- <baseAddress>0x40015400</baseAddress>
- <interrupt>
- <name>SPI6</name>
- <description>SPI 6 global interrupt</description>
- <value>86</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>SPI2</name>
- <description>Serial peripheral interface</description>
- <groupName>SPI</groupName>
- <baseAddress>0x40003800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>SPI2</name>
- <description>SPI2 global interrupt</description>
- <value>36</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>BIDIMODE</name>
- <description>Bidirectional data mode enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BIDIOE</name>
- <description>Output enable in bidirectional mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCEN</name>
- <description>Hardware CRC calculation enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCNEXT</name>
- <description>CRC transfer next</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CRCL</name>
- <description>CRC length</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXONLY</name>
- <description>Receive only</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSM</name>
- <description>Software slave management</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSI</name>
- <description>Internal slave select</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSBFIRST</name>
- <description>Frame format</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPE</name>
- <description>SPI enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BR</name>
- <description>Baud rate control</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MSTR</name>
- <description>Master selection</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPOL</name>
- <description>Clock polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPHA</name>
- <description>Clock phase</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0700</resetValue>
- <fields>
- <field>
- <name>RXDMAEN</name>
- <description>Rx buffer DMA enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXDMAEN</name>
- <description>Tx buffer DMA enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSOE</name>
- <description>SS output enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NSSP</name>
- <description>NSS pulse management</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRF</name>
- <description>Frame format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERRIE</name>
- <description>Error interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXNEIE</name>
- <description>RX buffer not empty interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXEIE</name>
- <description>Tx buffer empty interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DS</name>
- <description>Data size</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRXTH</name>
- <description>FIFO reception threshold</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LDMA_RX</name>
- <description>Last DMA transfer for reception</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LDMA_TX</name>
- <description>Last DMA transfer for transmission</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x0002</resetValue>
- <fields>
- <field>
- <name>BSY</name>
- <description>Busy flag</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>OVR</name>
- <description>Overrun flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MODF</name>
- <description>Mode fault</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CRCERR</name>
- <description>CRC error flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>UDR</name>
- <description>Underrun flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CHSIDE</name>
- <description>Channel side</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXE</name>
- <description>Transmit buffer empty</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>RXNE</name>
- <description>Receive buffer not empty</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>FRE</name>
- <description>Frame format error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>FRLVL</name>
- <description>FIFO reception level</description>
- <bitOffset>9</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>FTLVL</name>
- <description>FIFO Transmission Level</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>data register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DR</name>
- <description>Data register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CRCPR</name>
- <displayName>CRCPR</displayName>
- <description>CRC polynomial register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0007</resetValue>
- <fields>
- <field>
- <name>CRCPOLY</name>
- <description>CRC polynomial register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RXCRCR</name>
- <displayName>RXCRCR</displayName>
- <description>RX CRC register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>RxCRC</name>
- <description>Rx CRC register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TXCRCR</name>
- <displayName>TXCRCR</displayName>
- <description>TX CRC register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TxCRC</name>
- <description>Tx CRC register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>I2SCFGR</name>
- <displayName>I2SCFGR</displayName>
- <description>I2S configuration register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>I2SMOD</name>
- <description>I2S mode selection</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SE</name>
- <description>I2S Enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SCFG</name>
- <description>I2S configuration mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PCMSYNC</name>
- <description>PCM frame synchronization</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SSTD</name>
- <description>I2S standard selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKPOL</name>
- <description>Steady state clock polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DATLEN</name>
- <description>Data length to be transferred</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CHLEN</name>
- <description>Channel length (number of bits per audio channel)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASTRTEN</name>
- <description>Asynchronous start enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>I2SPR</name>
- <displayName>I2SPR</displayName>
- <description>I2S prescaler register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>00000010</resetValue>
- <fields>
- <field>
- <name>MCKOE</name>
- <description>Master clock output enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODD</name>
- <description>Odd factor for the prescaler</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2SDIV</name>
- <description>I2S Linear prescaler</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>ADC1</name>
- <description>Analog-to-digital converter</description>
- <groupName>ADC</groupName>
- <baseAddress>0x40012000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x100</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OVR</name>
- <description>Overrun</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STRT</name>
- <description>Regular channel start flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JSTRT</name>
- <description>Injected channel start flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEOC</name>
- <description>Injected channel end of conversion</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOC</name>
- <description>Regular channel end of conversion</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWD</name>
- <description>Analog watchdog flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OVRIE</name>
- <description>Overrun interrupt enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RES</name>
- <description>Resolution</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>AWDEN</name>
- <description>Analog watchdog enable on regular channels</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JAWDEN</name>
- <description>Analog watchdog enable on injected channels</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DISCNUM</name>
- <description>Discontinuous mode channel count</description>
- <bitOffset>13</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>JDISCEN</name>
- <description>Discontinuous mode on injected channels</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DISCEN</name>
- <description>Discontinuous mode on regular channels</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JAUTO</name>
- <description>Automatic injected group conversion</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWDSGL</name>
- <description>Enable the watchdog on a single channel in scan mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SCAN</name>
- <description>Scan mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEOCIE</name>
- <description>Interrupt enable for injected channels</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWDIE</name>
- <description>Analog watchdog interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOCIE</name>
- <description>Interrupt enable for EOC</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWDCH</name>
- <description>Analog watchdog channel select bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SWSTART</name>
- <description>Start conversion of regular channels</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTEN</name>
- <description>External trigger enable for regular channels</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>EXTSEL</name>
- <description>External event select for regular group</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>JSWSTART</name>
- <description>Start conversion of injected channels</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEXTEN</name>
- <description>External trigger enable for injected channels</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>JEXTSEL</name>
- <description>External event select for injected group</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ALIGN</name>
- <description>Data alignment</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOCS</name>
- <description>End of conversion selection</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DDS</name>
- <description>DMA disable selection (for single ADC mode)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMA</name>
- <description>Direct memory access mode (for single ADC mode)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CONT</name>
- <description>Continuous conversion</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADON</name>
- <description>A/D Converter ON / OFF</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMPR1</name>
- <displayName>SMPR1</displayName>
- <description>sample time register 1</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SMPx_x</name>
- <description>Sample time bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMPR2</name>
- <displayName>SMPR2</displayName>
- <description>sample time register 2</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SMPx_x</name>
- <description>Sample time bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JOFR1</name>
- <displayName>JOFR1</displayName>
- <description>injected channel data offset register x</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JOFFSET1</name>
- <description>Data offset for injected channel x</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JOFR2</name>
- <displayName>JOFR2</displayName>
- <description>injected channel data offset register x</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JOFFSET2</name>
- <description>Data offset for injected channel x</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JOFR3</name>
- <displayName>JOFR3</displayName>
- <description>injected channel data offset register x</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JOFFSET3</name>
- <description>Data offset for injected channel x</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JOFR4</name>
- <displayName>JOFR4</displayName>
- <description>injected channel data offset register x</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JOFFSET4</name>
- <description>Data offset for injected channel x</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HTR</name>
- <displayName>HTR</displayName>
- <description>watchdog higher threshold register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000FFF</resetValue>
- <fields>
- <field>
- <name>HT</name>
- <description>Analog watchdog higher threshold</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LTR</name>
- <displayName>LTR</displayName>
- <description>watchdog lower threshold register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LT</name>
- <description>Analog watchdog lower threshold</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SQR1</name>
- <displayName>SQR1</displayName>
- <description>regular sequence register 1</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>L</name>
- <description>Regular channel sequence length</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SQ16</name>
- <description>16th conversion in regular sequence</description>
- <bitOffset>15</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ15</name>
- <description>15th conversion in regular sequence</description>
- <bitOffset>10</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ14</name>
- <description>14th conversion in regular sequence</description>
- <bitOffset>5</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ13</name>
- <description>13th conversion in regular sequence</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SQR2</name>
- <displayName>SQR2</displayName>
- <description>regular sequence register 2</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SQ12</name>
- <description>12th conversion in regular sequence</description>
- <bitOffset>25</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ11</name>
- <description>11th conversion in regular sequence</description>
- <bitOffset>20</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ10</name>
- <description>10th conversion in regular sequence</description>
- <bitOffset>15</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ9</name>
- <description>9th conversion in regular sequence</description>
- <bitOffset>10</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ8</name>
- <description>8th conversion in regular sequence</description>
- <bitOffset>5</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ7</name>
- <description>7th conversion in regular sequence</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SQR3</name>
- <displayName>SQR3</displayName>
- <description>regular sequence register 3</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SQ6</name>
- <description>6th conversion in regular sequence</description>
- <bitOffset>25</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ5</name>
- <description>5th conversion in regular sequence</description>
- <bitOffset>20</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ4</name>
- <description>4th conversion in regular sequence</description>
- <bitOffset>15</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ3</name>
- <description>3rd conversion in regular sequence</description>
- <bitOffset>10</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ2</name>
- <description>2nd conversion in regular sequence</description>
- <bitOffset>5</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SQ1</name>
- <description>1st conversion in regular sequence</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JSQR</name>
- <displayName>JSQR</displayName>
- <description>injected sequence register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JL</name>
- <description>Injected sequence length</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>JSQ4</name>
- <description>4th conversion in injected sequence</description>
- <bitOffset>15</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>JSQ3</name>
- <description>3rd conversion in injected sequence</description>
- <bitOffset>10</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>JSQ2</name>
- <description>2nd conversion in injected sequence</description>
- <bitOffset>5</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>JSQ1</name>
- <description>1st conversion in injected sequence</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JDR1</name>
- <displayName>JDR1</displayName>
- <description>injected data register x</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JDATA</name>
- <description>Injected data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JDR2</name>
- <displayName>JDR2</displayName>
- <description>injected data register x</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JDATA</name>
- <description>Injected data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JDR3</name>
- <displayName>JDR3</displayName>
- <description>injected data register x</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JDATA</name>
- <description>Injected data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>JDR4</name>
- <displayName>JDR4</displayName>
- <description>injected data register x</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>JDATA</name>
- <description>Injected data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>regular data register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA</name>
- <description>Regular data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="ADC1">
- <name>ADC2</name>
- <baseAddress>0x40012100</baseAddress>
- </peripheral>
- <peripheral derivedFrom="ADC1">
- <name>ADC3</name>
- <baseAddress>0x40012200</baseAddress>
- </peripheral>
- <peripheral>
- <name>DAC</name>
- <description>Digital-to-analog converter</description>
- <groupName>DAC</groupName>
- <baseAddress>0x40007400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DMAUDRIE2</name>
- <description>DAC channel2 DMA underrun interrupt enable</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAEN2</name>
- <description>DAC channel2 DMA enable</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MAMP2</name>
- <description>DAC channel2 mask/amplitude selector</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>WAVE2</name>
- <description>DAC channel2 noise/triangle wave generation enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TSEL2</name>
- <description>DAC channel2 trigger selection</description>
- <bitOffset>19</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TEN2</name>
- <description>DAC channel2 trigger enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BOFF2</name>
- <description>DAC channel2 output buffer disable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN2</name>
- <description>DAC channel2 enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAUDRIE1</name>
- <description>DAC channel1 DMA Underrun Interrupt enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAEN1</name>
- <description>DAC channel1 DMA enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MAMP1</name>
- <description>DAC channel1 mask/amplitude selector</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>WAVE1</name>
- <description>DAC channel1 noise/triangle wave generation enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TSEL1</name>
- <description>DAC channel1 trigger selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TEN1</name>
- <description>DAC channel1 trigger enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BOFF1</name>
- <description>DAC channel1 output buffer disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN1</name>
- <description>DAC channel1 enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SWTRIGR</name>
- <displayName>SWTRIGR</displayName>
- <description>software trigger register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SWTRIG2</name>
- <description>DAC channel2 software trigger</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWTRIG1</name>
- <description>DAC channel1 software trigger</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12R1</name>
- <displayName>DHR12R1</displayName>
- <description>channel1 12-bit right-aligned data holding register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 12-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12L1</name>
- <displayName>DHR12L1</displayName>
- <description>channel1 12-bit left aligned data holding register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 12-bit left-aligned data</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR8R1</name>
- <displayName>DHR8R1</displayName>
- <description>channel1 8-bit right aligned data holding register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 8-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12R2</name>
- <displayName>DHR12R2</displayName>
- <description>channel2 12-bit right aligned data holding register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 12-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12L2</name>
- <displayName>DHR12L2</displayName>
- <description>channel2 12-bit left aligned data holding register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 12-bit left-aligned data</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR8R2</name>
- <displayName>DHR8R2</displayName>
- <description>channel2 8-bit right-aligned data holding register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 8-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12RD</name>
- <displayName>DHR12RD</displayName>
- <description>Dual DAC 12-bit right-aligned data holding register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 12-bit right-aligned data</description>
- <bitOffset>16</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 12-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR12LD</name>
- <displayName>DHR12LD</displayName>
- <description>DUAL DAC 12-bit left aligned data holding register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 12-bit left-aligned data</description>
- <bitOffset>20</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 12-bit left-aligned data</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DHR8RD</name>
- <displayName>DHR8RD</displayName>
- <description>DUAL DAC 8-bit right aligned data holding register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DHR</name>
- <description>DAC channel2 8-bit right-aligned data</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DACC1DHR</name>
- <description>DAC channel1 8-bit right-aligned data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DOR1</name>
- <displayName>DOR1</displayName>
- <description>channel1 data output register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC1DOR</name>
- <description>DAC channel1 data output</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DOR2</name>
- <displayName>DOR2</displayName>
- <description>channel2 data output register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DACC2DOR</name>
- <description>DAC channel2 data output</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DMAUDR2</name>
- <description>DAC channel2 DMA underrun flag</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAUDR1</name>
- <description>DAC channel1 DMA underrun flag</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>PWR</name>
- <description>Power control</description>
- <groupName>PWR</groupName>
- <baseAddress>0x40007000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>power control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000C000</resetValue>
- <fields>
- <field>
- <name>LPDS</name>
- <description>Low-power deep sleep</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PDDS</name>
- <description>Power down deepsleep</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSBF</name>
- <description>Clear standby flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PVDE</name>
- <description>Power voltage detector enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLS</name>
- <description>PVD level selection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>DBP</name>
- <description>Disable backup domain write protection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FPDS</name>
- <description>Flash power down in Stop mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LPUDS</name>
- <description>Low-power regulator in deepsleep under-drive mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MRUDS</name>
- <description>Main regulator in deepsleep under-drive mode</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADCDC1</name>
- <description>ADCDC1</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VOS</name>
- <description>Regulator voltage scaling output selection</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ODEN</name>
- <description>Over-drive enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ODSWEN</name>
- <description>Over-drive switching enabled</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDEN</name>
- <description>Under-drive enable in stop mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR1</name>
- <displayName>CSR1</displayName>
- <description>power control/status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WUIF</name>
- <description>Wakeup internal flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SBF</name>
- <description>Standby flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PVDO</name>
- <description>PVD output</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BRR</name>
- <description>Backup regulator ready</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BRE</name>
- <description>Backup regulator enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>VOSRDY</name>
- <description>Regulator voltage scaling output selection ready bit</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ODRDY</name>
- <description>Over-drive mode ready</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ODSWRDY</name>
- <description>Over-drive mode switching ready</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>UDRDY</name>
- <description>Under-drive ready flag</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>power control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CWUPF1</name>
- <description>Clear Wakeup Pin flag for PA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CWUPF2</name>
- <description>Clear Wakeup Pin flag for PA2</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CWUPF3</name>
- <description>Clear Wakeup Pin flag for PC1</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CWUPF4</name>
- <description>Clear Wakeup Pin flag for PC13</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CWUPF5</name>
- <description>Clear Wakeup Pin flag for PI8</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CWUPF6</name>
- <description>Clear Wakeup Pin flag for PI11</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPP1</name>
- <description>Wakeup pin polarity bit for PA0</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUPP2</name>
- <description>Wakeup pin polarity bit for PA2</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUPP3</name>
- <description>Wakeup pin polarity bit for PC1</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUPP4</name>
- <description>Wakeup pin polarity bit for PC13</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUPP5</name>
- <description>Wakeup pin polarity bit for PI8</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUPP6</name>
- <description>Wakeup pin polarity bit for PI11</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR2</name>
- <displayName>CSR2</displayName>
- <description>power control/status register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WUPF1</name>
- <description>Wakeup Pin flag for PA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPF2</name>
- <description>Wakeup Pin flag for PA2</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPF3</name>
- <description>Wakeup Pin flag for PC1</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPF4</name>
- <description>Wakeup Pin flag for PC13</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPF5</name>
- <description>Wakeup Pin flag for PI8</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUPF6</name>
- <description>Wakeup Pin flag for PI11</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EWUP1</name>
- <description>Enable Wakeup pin for PA0</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EWUP2</name>
- <description>Enable Wakeup pin for PA2</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EWUP3</name>
- <description>Enable Wakeup pin for PC1</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EWUP4</name>
- <description>Enable Wakeup pin for PC13</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EWUP5</name>
- <description>Enable Wakeup pin for PI8</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EWUP6</name>
- <description>Enable Wakeup pin for PI11</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>IWDG</name>
- <description>Independent watchdog</description>
- <groupName>IWDG</groupName>
- <baseAddress>0x40003000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>KR</name>
- <displayName>KR</displayName>
- <description>Key register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>KEY</name>
- <description>Key value (write only, read 0000h)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PR</name>
- <displayName>PR</displayName>
- <description>Prescaler register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PR</name>
- <description>Prescaler divider</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RLR</name>
- <displayName>RLR</displayName>
- <description>Reload register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000FFF</resetValue>
- <fields>
- <field>
- <name>RL</name>
- <description>Watchdog counter reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>Status register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RVU</name>
- <description>Watchdog counter reload value update</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PVU</name>
- <description>Watchdog prescaler value update</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>WINR</name>
- <displayName>WINR</displayName>
- <description>Window register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WIN</name>
- <description>Watchdog counter window value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>WWDG</name>
- <description>Window watchdog</description>
- <groupName>WWDG</groupName>
- <baseAddress>0x40002C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>WWDG</name>
- <description>Window Watchdog interrupt</description>
- <value>0</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>Control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x7F</resetValue>
- <fields>
- <field>
- <name>WDGA</name>
- <description>Activation bit</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>T</name>
- <description>7-bit counter (MSB to LSB)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CFR</name>
- <displayName>CFR</displayName>
- <description>Configuration register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x7F</resetValue>
- <fields>
- <field>
- <name>EWI</name>
- <description>Early wakeup interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WDGTB1</name>
- <description>Timer base</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WDGTB0</name>
- <description>Timer base</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>W</name>
- <description>7-bit window value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>Status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00</resetValue>
- <fields>
- <field>
- <name>EWIF</name>
- <description>Early wakeup interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>C_ADC</name>
- <description>Common ADC registers</description>
- <groupName>ADC</groupName>
- <baseAddress>0x40012300</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>ADC</name>
- <description>ADC1 global interrupt</description>
- <value>18</value>
- </interrupt>
- <registers>
- <register>
- <name>CSR</name>
- <displayName>CSR</displayName>
- <description>ADC Common status register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OVR3</name>
- <description>Overrun flag of ADC3</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STRT3</name>
- <description>Regular channel Start flag of ADC 3</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JSTRT3</name>
- <description>Injected channel Start flag of ADC 3</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEOC3</name>
- <description>Injected channel end of conversion of ADC 3</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOC3</name>
- <description>End of conversion of ADC 3</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWD3</name>
- <description>Analog watchdog flag of ADC 3</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR2</name>
- <description>Overrun flag of ADC 2</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STRT2</name>
- <description>Regular channel Start flag of ADC 2</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JSTRT2</name>
- <description>Injected channel Start flag of ADC 2</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEOC2</name>
- <description>Injected channel end of conversion of ADC 2</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOC2</name>
- <description>End of conversion of ADC 2</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWD2</name>
- <description>Analog watchdog flag of ADC 2</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR1</name>
- <description>Overrun flag of ADC 1</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STRT1</name>
- <description>Regular channel Start flag of ADC 1</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JSTRT1</name>
- <description>Injected channel Start flag of ADC 1</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>JEOC1</name>
- <description>Injected channel end of conversion of ADC 1</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOC1</name>
- <description>End of conversion of ADC 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWD1</name>
- <description>Analog watchdog flag of ADC 1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR</name>
- <displayName>CCR</displayName>
- <description>ADC common control register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSVREFE</name>
- <description>Temperature sensor and VREFINT enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VBATE</name>
- <description>VBAT enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADCPRE</name>
- <description>ADC prescaler</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DMA</name>
- <description>Direct memory access mode for multi ADC mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DDS</name>
- <description>DMA disable selection for multi-ADC mode</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DELAY</name>
- <description>Delay between 2 sampling phases</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MULT</name>
- <description>Multi ADC mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CDR</name>
- <displayName>CDR</displayName>
- <description>ADC common regular data register for dual and triple modes</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA2</name>
- <description>2nd data item of a pair of regular conversions</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>1st data item of a pair of regular conversions</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>TIM1</name>
- <description>Advanced-timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40010000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TIM1_BRK_TIM9</name>
- <description>TIM1 Break interrupt and TIM9 global
- interrupt</description>
- <value>24</value>
- </interrupt>
- <interrupt>
- <name>TIM1_TRG_COM_TIM11</name>
- <description>TIM1 Trigger and Commutation interrupts and
- TIM11 global interrupt</description>
- <value>26</value>
- </interrupt>
- <interrupt>
- <name>TIM1_UP_TIM10</name>
- <description>TIM1 Update interrupt and TIM10</description>
- <value>25</value>
- </interrupt>
- <interrupt>
- <name>TIM1_CC</name>
- <description>TIM1 Capture Compare interrupt</description>
- <value>27</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMS</name>
- <description>Center-aligned mode selection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Direction</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>OIS4</name>
- <description>Output Idle state 4</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS3N</name>
- <description>Output Idle state 3</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS3</name>
- <description>Output Idle state 3</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS2N</name>
- <description>Output Idle state 2</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS2</name>
- <description>Output Idle state 2</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS1N</name>
- <description>Output Idle state 1</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OIS1</name>
- <description>Output Idle state 1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TI1S</name>
- <description>TI1 selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMS</name>
- <description>Master mode selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CCDS</name>
- <description>Capture/compare DMA selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCUS</name>
- <description>Capture/compare control update selection</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCPC</name>
- <description>Capture/compare preloaded control</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>SMS_3</name>
- <description>Slave model selection - bit[3]</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETP</name>
- <description>External trigger polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ECE</name>
- <description>External clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETPS</name>
- <description>External trigger prescaler</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ETF</name>
- <description>External trigger filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSM</name>
- <description>Master/Slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SMS</name>
- <description>Slave mode selection - bit[2:0]</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TDE</name>
- <description>Trigger DMA request enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COMDE</name>
- <description>COM DMA request enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4DE</name>
- <description>Capture/Compare 4 DMA request enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3DE</name>
- <description>Capture/Compare 3 DMA request enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2DE</name>
- <description>Capture/Compare 2 DMA request enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1DE</name>
- <description>Capture/Compare 1 DMA request enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDE</name>
- <description>Update DMA request enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIE</name>
- <description>Trigger interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IE</name>
- <description>Capture/Compare 4 interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IE</name>
- <description>Capture/Compare 3 interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IE</name>
- <description>Capture/Compare 2 interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BIE</name>
- <description>Break interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COMIE</name>
- <description>COM interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4OF</name>
- <description>Capture/Compare 4 overcapture flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3OF</name>
- <description>Capture/Compare 3 overcapture flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2OF</name>
- <description>Capture/compare 2 overcapture flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BIF</name>
- <description>Break interrupt flag</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIF</name>
- <description>Trigger interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COMIF</name>
- <description>COM interrupt flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IF</name>
- <description>Capture/Compare 4 interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IF</name>
- <description>Capture/Compare 3 interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IF</name>
- <description>Capture/Compare 2 interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>BG</name>
- <description>Break generation</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TG</name>
- <description>Trigger generation</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COMG</name>
- <description>Capture/Compare control update generation</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4G</name>
- <description>Capture/compare 4 generation</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3G</name>
- <description>Capture/compare 3 generation</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2G</name>
- <description>Capture/compare 2 generation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC2CE</name>
- <description>Output Compare 2 clear enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2M</name>
- <description>Output Compare 2 mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC2PE</name>
- <description>Output Compare 2 preload enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2FE</name>
- <description>Output Compare 2 fast enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC1CE</name>
- <description>Output Compare 1 clear enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1M</name>
- <description>Output Compare 1 mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>Output Compare 1 preload enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>Output Compare 1 fast enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC2F</name>
- <description>Input capture 2 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC2PCS</name>
- <description>Input capture 2 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Output</name>
- <displayName>CCMR2_Output</displayName>
- <description>capture/compare mode register 2 (output mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC4CE</name>
- <description>Output compare 4 clear enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4M</name>
- <description>Output compare 4 mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC4PE</name>
- <description>Output compare 4 preload enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4FE</name>
- <description>Output compare 4 fast enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>Capture/Compare 4 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC3CE</name>
- <description>Output compare 3 clear enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3M</name>
- <description>Output compare 3 mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC3PE</name>
- <description>Output compare 3 preload enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3FE</name>
- <description>Output compare 3 fast enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>Capture/Compare 3 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Input</name>
- <displayName>CCMR2_Input</displayName>
- <description>capture/compare mode register 2 (input mode)</description>
- <alternateRegister>CCMR2_Output</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC4F</name>
- <description>Input capture 4 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC4PSC</name>
- <description>Input capture 4 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>Capture/Compare 4 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC3F</name>
- <description>Input capture 3 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC3PSC</name>
- <description>Input capture 3 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>Capture/compare 3 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4E</name>
- <description>Capture/Compare 4 output enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3NP</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3NE</name>
- <description>Capture/Compare 3 complementary output enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3E</name>
- <description>Capture/Compare 3 output enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2NP</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2NE</name>
- <description>Capture/Compare 2 complementary output enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2P</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2E</name>
- <description>Capture/Compare 2 output enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NE</name>
- <description>Capture/Compare 1 complementary output enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT</name>
- <description>counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR</name>
- <description>Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1</name>
- <description>Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR2</name>
- <displayName>CCR2</displayName>
- <description>capture/compare register 2</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR2</name>
- <description>Capture/Compare 2 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR3</name>
- <displayName>CCR3</displayName>
- <description>capture/compare register 3</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR3</name>
- <description>Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR4</name>
- <displayName>CCR4</displayName>
- <description>capture/compare register 4</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR4</name>
- <description>Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCR</name>
- <displayName>DCR</displayName>
- <description>DMA control register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DBL</name>
- <description>DMA burst length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>DBA</name>
- <description>DMA base address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAR</name>
- <displayName>DMAR</displayName>
- <description>DMA address for full transfer</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DMAB</name>
- <description>DMA register for burst accesses</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RCR</name>
- <displayName>RCR</displayName>
- <description>repetition counter register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>REP</name>
- <description>Repetition counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BDTR</name>
- <displayName>BDTR</displayName>
- <description>break and dead-time register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>MOE</name>
- <description>Main output enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AOE</name>
- <description>Automatic output enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BKP</name>
- <description>Break polarity</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BKE</name>
- <description>Break enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OSSR</name>
- <description>Off-state selection for Run mode</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OSSI</name>
- <description>Off-state selection for Idle mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LOCK</name>
- <description>Lock configuration</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DTG</name>
- <description>Dead-time generator setup</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR3_Output</name>
- <displayName>CCMR3_Output</displayName>
- <description>capture/compare mode register 3 (output mode)</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>OC5FE</name>
- <description>Output compare 5 fast enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC5PE</name>
- <description>Output compare 5 preload enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC5M</name>
- <description>Output compare 5 mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC5CE</name>
- <description>Output compare 5 clear enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC6FE</name>
- <description>Output compare 6 fast enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC6PE</name>
- <description>Output compare 6 preload enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC6M</name>
- <description>Output compare 6 mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC6CE</name>
- <description>Output compare 6 clear enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC5M3</name>
- <description>Output Compare 5 mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC6M3</name>
- <description>Output Compare 6 mode</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR5</name>
- <displayName>CCR5</displayName>
- <description>capture/compare register 5</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CCR5</name>
- <description>Capture/Compare 5 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>GC5C1</name>
- <description>Group Channel 5 and Channel 1</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GC5C2</name>
- <description>Group Channel 5 and Channel 2</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GC5C3</name>
- <description>Group Channel 5 and Channel 3</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CRR6</name>
- <displayName>CRR6</displayName>
- <description>capture/compare register 6</description>
- <addressOffset>0x5C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CCR6</name>
- <description>Capture/Compare 6 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="TIM1">
- <name>TIM8</name>
- <baseAddress>0x40010400</baseAddress>
- <interrupt>
- <name>TIM8_BRK_TIM12</name>
- <description>TIM8 Break interrupt and TIM12 global
- interrupt</description>
- <value>43</value>
- </interrupt>
- <interrupt>
- <name>TIM8_UP_TIM13</name>
- <description>TIM8 Update interrupt and TIM13 global
- interrupt</description>
- <value>44</value>
- </interrupt>
- <interrupt>
- <name>TIM8_TRG_COM_TIM14</name>
- <description>TIM8 Trigger and Commutation interrupts and
- TIM14 global interrupt</description>
- <value>45</value>
- </interrupt>
- <interrupt>
- <name>TIM8_CC</name>
- <description>TIM8 Capture Compare interrupt</description>
- <value>46</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>TIM2</name>
- <description>General purpose timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TIM2</name>
- <description>TIM2 global interrupt</description>
- <value>28</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMS</name>
- <description>Center-aligned mode selection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Direction</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TI1S</name>
- <description>TI1 selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMS</name>
- <description>Master mode selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CCDS</name>
- <description>Capture/compare DMA selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>SMS</name>
- <description>Slave mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MSM</name>
- <description>Master/Slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETF</name>
- <description>External trigger filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ETPS</name>
- <description>External trigger prescaler</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ECE</name>
- <description>External clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETP</name>
- <description>External trigger polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMS_3</name>
- <description>Slave model selection - bit[3]</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TDE</name>
- <description>Trigger DMA request enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4DE</name>
- <description>Capture/Compare 4 DMA request enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3DE</name>
- <description>Capture/Compare 3 DMA request enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2DE</name>
- <description>Capture/Compare 2 DMA request enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1DE</name>
- <description>Capture/Compare 1 DMA request enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDE</name>
- <description>Update DMA request enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIE</name>
- <description>Trigger interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IE</name>
- <description>Capture/Compare 4 interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IE</name>
- <description>Capture/Compare 3 interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IE</name>
- <description>Capture/Compare 2 interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4OF</name>
- <description>Capture/Compare 4 overcapture flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3OF</name>
- <description>Capture/Compare 3 overcapture flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2OF</name>
- <description>Capture/compare 2 overcapture flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIF</name>
- <description>Trigger interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IF</name>
- <description>Capture/Compare 4 interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IF</name>
- <description>Capture/Compare 3 interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IF</name>
- <description>Capture/Compare 2 interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TG</name>
- <description>Trigger generation</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4G</name>
- <description>Capture/compare 4 generation</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3G</name>
- <description>Capture/compare 3 generation</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2G</name>
- <description>Capture/compare 2 generation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC2CE</name>
- <description>OC2CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2M</name>
- <description>OC2M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC2PE</name>
- <description>OC2PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2FE</name>
- <description>OC2FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>CC2S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC1CE</name>
- <description>OC1CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1M</name>
- <description>OC1M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>OC1PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>OC1FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>CC1S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC2F</name>
- <description>Input capture 2 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC2PCS</name>
- <description>Input capture 2 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Output</name>
- <displayName>CCMR2_Output</displayName>
- <description>capture/compare mode register 2 (output mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>O24CE</name>
- <description>O24CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4M</name>
- <description>OC4M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC4PE</name>
- <description>OC4PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4FE</name>
- <description>OC4FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>CC4S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC3CE</name>
- <description>OC3CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3M</name>
- <description>OC3M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC3PE</name>
- <description>OC3PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3FE</name>
- <description>OC3FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>CC3S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Input</name>
- <displayName>CCMR2_Input</displayName>
- <description>capture/compare mode register 2 (input mode)</description>
- <alternateRegister>CCMR2_Output</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC4F</name>
- <description>Input capture 4 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC4PSC</name>
- <description>Input capture 4 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>Capture/Compare 4 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC3F</name>
- <description>Input capture 3 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC3PSC</name>
- <description>Input capture 3 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>Capture/compare 3 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4NP</name>
- <description>Capture/Compare 4 output Polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4E</name>
- <description>Capture/Compare 4 output enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3NP</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3E</name>
- <description>Capture/Compare 3 output enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2NP</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2P</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2E</name>
- <description>Capture/Compare 2 output enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT_H</name>
- <description>High counter value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CNT_L</name>
- <description>Low counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR_H</name>
- <description>High Auto-reload value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>ARR_L</name>
- <description>Low Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1_H</name>
- <description>High Capture/Compare 1 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR1_L</name>
- <description>Low Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR2</name>
- <displayName>CCR2</displayName>
- <description>capture/compare register 2</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR2_H</name>
- <description>High Capture/Compare 2 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR2_L</name>
- <description>Low Capture/Compare 2 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR3</name>
- <displayName>CCR3</displayName>
- <description>capture/compare register 3</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR3_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR3_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR4</name>
- <displayName>CCR4</displayName>
- <description>capture/compare register 4</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR4_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR4_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCR</name>
- <displayName>DCR</displayName>
- <description>DMA control register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DBL</name>
- <description>DMA burst length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>DBA</name>
- <description>DMA base address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAR</name>
- <displayName>DMAR</displayName>
- <description>DMA address for full transfer</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DMAB</name>
- <description>DMA register for burst accesses</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR1</name>
- <displayName>OR1</displayName>
- <description>TIM2 option register 1</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TI4_RMP</name>
- <description>Input Capture 4 remap</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ETR1_RMP</name>
- <description>External trigger remap</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ITR1_RMP</name>
- <description>Internal trigger 1 remap</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR2</name>
- <displayName>OR2</displayName>
- <description>TIM2 option register 2</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>ETRSEL</name>
- <description>ETR source selection</description>
- <bitOffset>14</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>TIM3</name>
- <description>General purpose timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40000400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TIM3</name>
- <description>TIM3 global interrupt</description>
- <value>29</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMS</name>
- <description>Center-aligned mode selection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Direction</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TI1S</name>
- <description>TI1 selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMS</name>
- <description>Master mode selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CCDS</name>
- <description>Capture/compare DMA selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>SMS</name>
- <description>Slave mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MSM</name>
- <description>Master/Slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETF</name>
- <description>External trigger filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ETPS</name>
- <description>External trigger prescaler</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ECE</name>
- <description>External clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETP</name>
- <description>External trigger polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMS_3</name>
- <description>Slave model selection - bit[3]</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TDE</name>
- <description>Trigger DMA request enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4DE</name>
- <description>Capture/Compare 4 DMA request enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3DE</name>
- <description>Capture/Compare 3 DMA request enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2DE</name>
- <description>Capture/Compare 2 DMA request enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1DE</name>
- <description>Capture/Compare 1 DMA request enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDE</name>
- <description>Update DMA request enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIE</name>
- <description>Trigger interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IE</name>
- <description>Capture/Compare 4 interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IE</name>
- <description>Capture/Compare 3 interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IE</name>
- <description>Capture/Compare 2 interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4OF</name>
- <description>Capture/Compare 4 overcapture flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3OF</name>
- <description>Capture/Compare 3 overcapture flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2OF</name>
- <description>Capture/compare 2 overcapture flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIF</name>
- <description>Trigger interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IF</name>
- <description>Capture/Compare 4 interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IF</name>
- <description>Capture/Compare 3 interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IF</name>
- <description>Capture/Compare 2 interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TG</name>
- <description>Trigger generation</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4G</name>
- <description>Capture/compare 4 generation</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3G</name>
- <description>Capture/compare 3 generation</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2G</name>
- <description>Capture/compare 2 generation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC2CE</name>
- <description>OC2CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2M</name>
- <description>OC2M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC2PE</name>
- <description>OC2PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2FE</name>
- <description>OC2FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>CC2S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC1CE</name>
- <description>OC1CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1M</name>
- <description>OC1M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>OC1PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>OC1FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>CC1S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC2F</name>
- <description>Input capture 2 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC2PCS</name>
- <description>Input capture 2 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Output</name>
- <displayName>CCMR2_Output</displayName>
- <description>capture/compare mode register 2 (output mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>O24CE</name>
- <description>O24CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4M</name>
- <description>OC4M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC4PE</name>
- <description>OC4PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4FE</name>
- <description>OC4FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>CC4S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC3CE</name>
- <description>OC3CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3M</name>
- <description>OC3M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC3PE</name>
- <description>OC3PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3FE</name>
- <description>OC3FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>CC3S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Input</name>
- <displayName>CCMR2_Input</displayName>
- <description>capture/compare mode register 2 (input mode)</description>
- <alternateRegister>CCMR2_Output</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC4F</name>
- <description>Input capture 4 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC4PSC</name>
- <description>Input capture 4 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>Capture/Compare 4 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC3F</name>
- <description>Input capture 3 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC3PSC</name>
- <description>Input capture 3 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>Capture/compare 3 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4NP</name>
- <description>Capture/Compare 4 output Polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4E</name>
- <description>Capture/Compare 4 output enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3NP</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3E</name>
- <description>Capture/Compare 3 output enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2NP</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2P</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2E</name>
- <description>Capture/Compare 2 output enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT_H</name>
- <description>High counter value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CNT_L</name>
- <description>Low counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR_H</name>
- <description>High Auto-reload value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>ARR_L</name>
- <description>Low Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1_H</name>
- <description>High Capture/Compare 1 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR1_L</name>
- <description>Low Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR2</name>
- <displayName>CCR2</displayName>
- <description>capture/compare register 2</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR2_H</name>
- <description>High Capture/Compare 2 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR2_L</name>
- <description>Low Capture/Compare 2 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR3</name>
- <displayName>CCR3</displayName>
- <description>capture/compare register 3</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR3_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR3_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR4</name>
- <displayName>CCR4</displayName>
- <description>capture/compare register 4</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR4_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR4_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCR</name>
- <displayName>DCR</displayName>
- <description>DMA control register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DBL</name>
- <description>DMA burst length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>DBA</name>
- <description>DMA base address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAR</name>
- <displayName>DMAR</displayName>
- <description>DMA address for full transfer</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DMAB</name>
- <description>DMA register for burst accesses</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR1</name>
- <displayName>OR1</displayName>
- <description>TIM3 option register 1</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TI1_RMP</name>
- <description>Input Capture 1 remap</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR2</name>
- <displayName>OR2</displayName>
- <description>TIM3 option register 2</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>ETRSEL</name>
- <description>ETR source selection</description>
- <bitOffset>14</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>TIM4</name>
- <description>General purpose timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40000800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TIM4</name>
- <description>TIM4 global interrupt</description>
- <value>30</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMS</name>
- <description>Center-aligned mode selection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DIR</name>
- <description>Direction</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TI1S</name>
- <description>TI1 selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMS</name>
- <description>Master mode selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CCDS</name>
- <description>Capture/compare DMA selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>SMS</name>
- <description>Slave mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MSM</name>
- <description>Master/Slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETF</name>
- <description>External trigger filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ETPS</name>
- <description>External trigger prescaler</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ECE</name>
- <description>External clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETP</name>
- <description>External trigger polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMS_3</name>
- <description>Slave model selection - bit[3]</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TDE</name>
- <description>Trigger DMA request enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4DE</name>
- <description>Capture/Compare 4 DMA request enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3DE</name>
- <description>Capture/Compare 3 DMA request enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2DE</name>
- <description>Capture/Compare 2 DMA request enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1DE</name>
- <description>Capture/Compare 1 DMA request enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDE</name>
- <description>Update DMA request enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIE</name>
- <description>Trigger interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IE</name>
- <description>Capture/Compare 4 interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IE</name>
- <description>Capture/Compare 3 interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IE</name>
- <description>Capture/Compare 2 interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4OF</name>
- <description>Capture/Compare 4 overcapture flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3OF</name>
- <description>Capture/Compare 3 overcapture flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2OF</name>
- <description>Capture/compare 2 overcapture flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIF</name>
- <description>Trigger interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4IF</name>
- <description>Capture/Compare 4 interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3IF</name>
- <description>Capture/Compare 3 interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IF</name>
- <description>Capture/Compare 2 interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TG</name>
- <description>Trigger generation</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4G</name>
- <description>Capture/compare 4 generation</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3G</name>
- <description>Capture/compare 3 generation</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2G</name>
- <description>Capture/compare 2 generation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC2CE</name>
- <description>OC2CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2M</name>
- <description>OC2M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC2PE</name>
- <description>OC2PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2FE</name>
- <description>OC2FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>CC2S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC1CE</name>
- <description>OC1CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1M</name>
- <description>OC1M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>OC1PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>OC1FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>CC1S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC2F</name>
- <description>Input capture 2 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC2PCS</name>
- <description>Input capture 2 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Output</name>
- <displayName>CCMR2_Output</displayName>
- <description>capture/compare mode register 2 (output mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>O24CE</name>
- <description>O24CE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4M</name>
- <description>OC4M</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC4PE</name>
- <description>OC4PE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC4FE</name>
- <description>OC4FE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>CC4S</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC3CE</name>
- <description>OC3CE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3M</name>
- <description>OC3M</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC3PE</name>
- <description>OC3PE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC3FE</name>
- <description>OC3FE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>CC3S</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR2_Input</name>
- <displayName>CCMR2_Input</displayName>
- <description>capture/compare mode register 2 (input mode)</description>
- <alternateRegister>CCMR2_Output</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC4F</name>
- <description>Input capture 4 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC4PSC</name>
- <description>Input capture 4 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC4S</name>
- <description>Capture/Compare 4 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC3F</name>
- <description>Input capture 3 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>IC3PSC</name>
- <description>Input capture 3 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC3S</name>
- <description>Capture/compare 3 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC4NP</name>
- <description>Capture/Compare 4 output Polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC4E</name>
- <description>Capture/Compare 4 output enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3NP</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3P</name>
- <description>Capture/Compare 3 output Polarity</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC3E</name>
- <description>Capture/Compare 3 output enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2NP</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2P</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2E</name>
- <description>Capture/Compare 2 output enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT_H</name>
- <description>High counter value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CNT_L</name>
- <description>Low counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR_H</name>
- <description>High Auto-reload value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>ARR_L</name>
- <description>Low Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1_H</name>
- <description>High Capture/Compare 1 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR1_L</name>
- <description>Low Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR2</name>
- <displayName>CCR2</displayName>
- <description>capture/compare register 2</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR2_H</name>
- <description>High Capture/Compare 2 value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR2_L</name>
- <description>Low Capture/Compare 2 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR3</name>
- <displayName>CCR3</displayName>
- <description>capture/compare register 3</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR3_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR3_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR4</name>
- <displayName>CCR4</displayName>
- <description>capture/compare register 4</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR4_H</name>
- <description>High Capture/Compare value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CCR4_L</name>
- <description>Low Capture/Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCR</name>
- <displayName>DCR</displayName>
- <description>DMA control register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DBL</name>
- <description>DMA burst length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>DBA</name>
- <description>DMA base address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAR</name>
- <displayName>DMAR</displayName>
- <description>DMA address for full transfer</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DMAB</name>
- <description>DMA register for burst accesses</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="TIM4">
- <name>TIM5</name>
- <baseAddress>0x40000C00</baseAddress>
- <interrupt>
- <name>TIM5</name>
- <description>TIM5 global interrupt</description>
- <value>50</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>TIM9</name>
- <description>General purpose timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40014000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>MSM</name>
- <description>Master/Slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SMS</name>
- <description>Slave mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TIE</name>
- <description>Trigger interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IE</name>
- <description>Capture/Compare 2 interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC2OF</name>
- <description>Capture/compare 2 overcapture flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIF</name>
- <description>Trigger interrupt flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2IF</name>
- <description>Capture/Compare 2 interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TG</name>
- <description>Trigger generation</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2G</name>
- <description>Capture/compare 2 generation</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC2M</name>
- <description>Output Compare 2 mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC2PE</name>
- <description>Output Compare 2 preload enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC2FE</name>
- <description>Output Compare 2 fast enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>OC1M</name>
- <description>Output Compare 1 mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>Output Compare 1 preload enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>Output Compare 1 fast enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC2F</name>
- <description>Input capture 2 filter</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>IC2PCS</name>
- <description>Input capture 2 prescaler</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC2S</name>
- <description>Capture/Compare 2 selection</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC2NP</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2P</name>
- <description>Capture/Compare 2 output Polarity</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC2E</name>
- <description>Capture/Compare 2 output enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT</name>
- <description>counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR</name>
- <description>Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1</name>
- <description>Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR2</name>
- <displayName>CCR2</displayName>
- <description>capture/compare register 2</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR2</name>
- <description>Capture/Compare 2 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="TIM9">
- <name>TIM12</name>
- <baseAddress>0x40001800</baseAddress>
- </peripheral>
- <peripheral>
- <name>TIM10</name>
- <description>General-purpose-timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40014400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CKD</name>
- <description>Clock division</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC1IE</name>
- <description>Capture/Compare 1 interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC1OF</name>
- <description>Capture/Compare 1 overcapture flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1IF</name>
- <description>Capture/compare 1 interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC1G</name>
- <description>Capture/compare 1 generation</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Output</name>
- <displayName>CCMR1_Output</displayName>
- <description>capture/compare mode register 1 (output mode)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OC1M</name>
- <description>Output Compare 1 mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OC1PE</name>
- <description>Output Compare 1 preload enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OC1FE</name>
- <description>Output Compare 1 fast enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCMR1_Input</name>
- <displayName>CCMR1_Input</displayName>
- <description>capture/compare mode register 1 (input mode)</description>
- <alternateRegister>CCMR1_Output</alternateRegister>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IC1F</name>
- <description>Input capture 1 filter</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ICPCS</name>
- <description>Input capture 1 prescaler</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CC1S</name>
- <description>Capture/Compare 1 selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCER</name>
- <displayName>CCER</displayName>
- <description>capture/compare enable register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>CC1NP</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1P</name>
- <description>Capture/Compare 1 output Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CC1E</name>
- <description>Capture/Compare 1 output enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT</name>
- <description>counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR</name>
- <description>Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR1</name>
- <displayName>CCR1</displayName>
- <description>capture/compare register 1</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCR1</name>
- <description>Capture/Compare 1 value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SMCR</name>
- <displayName>SMCR</displayName>
- <description>slave mode control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SMS3</name>
- <description>Slave mode selection</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETP</name>
- <description>External trigger polarity</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ECE</name>
- <description>External clock enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETPS</name>
- <description>External trigger prescaler</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ETF</name>
- <description>External trigger filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSM</name>
- <description>Master/slave mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TS</name>
- <description>Trigger selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SMS</name>
- <description>Slave mode selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR</name>
- <displayName>OR</displayName>
- <description>option register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TI1_RMP</name>
- <description>TIM11 Input 1 remapping capability</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="TIM10">
- <name>TIM11</name>
- <baseAddress>0x40014800</baseAddress>
- </peripheral>
- <peripheral derivedFrom="TIM10">
- <name>TIM13</name>
- <baseAddress>0x40001C00</baseAddress>
- </peripheral>
- <peripheral derivedFrom="TIM10">
- <name>TIM14</name>
- <baseAddress>0x40002000</baseAddress>
- </peripheral>
- <peripheral>
- <name>TIM6</name>
- <description>Basic timers</description>
- <groupName>TIM</groupName>
- <baseAddress>0x40001000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TIM6_DAC</name>
- <description>TIM6 global interrupt, DAC1 and DAC2 underrun
- error interrupt</description>
- <value>54</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>ARPE</name>
- <description>Auto-reload preload enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPM</name>
- <description>One-pulse mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>URS</name>
- <description>Update request source</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UDIS</name>
- <description>Update disable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CEN</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>MMS</name>
- <description>Master mode selection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIER</name>
- <displayName>DIER</displayName>
- <description>DMA/Interrupt enable register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>UDE</name>
- <description>Update DMA request enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UIE</name>
- <description>Update interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>UIF</name>
- <description>Update interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EGR</name>
- <displayName>EGR</displayName>
- <description>event generation register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>UG</name>
- <description>Update generation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>counter</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT</name>
- <description>Low counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSC</name>
- <displayName>PSC</displayName>
- <description>prescaler</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>auto-reload register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ARR</name>
- <description>Low Auto-reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="TIM6">
- <name>TIM7</name>
- <baseAddress>0x40001400</baseAddress>
- <interrupt>
- <name>TIM7</name>
- <description>TIM7 global interrupt</description>
- <value>55</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>Ethernet_MAC</name>
- <description>Ethernet: media access control (MAC)</description>
- <groupName>Ethernet</groupName>
- <baseAddress>0x40028000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x100</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MACCR</name>
- <displayName>MACCR</displayName>
- <description>Ethernet MAC configuration register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0008000</resetValue>
- <fields>
- <field>
- <name>RE</name>
- <description>RE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TE</name>
- <description>TE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DC</name>
- <description>DC</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BL</name>
- <description>BL</description>
- <bitOffset>5</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>APCS</name>
- <description>APCS</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RD</name>
- <description>RD</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IPCO</name>
- <description>IPCO</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DM</name>
- <description>DM</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LM</name>
- <description>LM</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ROD</name>
- <description>ROD</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FES</name>
- <description>FES</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSD</name>
- <description>CSD</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IFG</name>
- <description>IFG</description>
- <bitOffset>17</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>JD</name>
- <description>JD</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WD</name>
- <description>WD</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSTF</name>
- <description>CSTF</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACFFR</name>
- <displayName>MACFFR</displayName>
- <description>Ethernet MAC frame filter register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PM</name>
- <description>PM</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HU</name>
- <description>HU</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HM</name>
- <description>HM</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DAIF</name>
- <description>DAIF</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RAM</name>
- <description>RAM</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BFD</name>
- <description>BFD</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PCF</name>
- <description>PCF</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAIF</name>
- <description>SAIF</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAF</name>
- <description>SAF</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HPF</name>
- <description>HPF</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RA</name>
- <description>RA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACHTHR</name>
- <displayName>MACHTHR</displayName>
- <description>Ethernet MAC hash table high register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HTH</name>
- <description>HTH</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACHTLR</name>
- <displayName>MACHTLR</displayName>
- <description>Ethernet MAC hash table low register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HTL</name>
- <description>HTL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACMIIAR</name>
- <displayName>MACMIIAR</displayName>
- <description>Ethernet MAC MII address register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MB</name>
- <description>MB</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MW</name>
- <description>MW</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CR</name>
- <description>CR</description>
- <bitOffset>2</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MR</name>
- <description>MR</description>
- <bitOffset>6</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>PA</name>
- <description>PA</description>
- <bitOffset>11</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACMIIDR</name>
- <displayName>MACMIIDR</displayName>
- <description>Ethernet MAC MII data register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TD</name>
- <description>TD</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACFCR</name>
- <displayName>MACFCR</displayName>
- <description>Ethernet MAC flow control register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FCB</name>
- <description>FCB</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TFCE</name>
- <description>TFCE</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RFCE</name>
- <description>RFCE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UPFD</name>
- <description>UPFD</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PLT</name>
- <description>PLT</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ZQPD</name>
- <description>ZQPD</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PT</name>
- <description>PT</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACVLANTR</name>
- <displayName>MACVLANTR</displayName>
- <description>Ethernet MAC VLAN tag register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>VLANTI</name>
- <description>VLANTI</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>VLANTC</name>
- <description>VLANTC</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACPMTCSR</name>
- <displayName>MACPMTCSR</displayName>
- <description>Ethernet MAC PMT control and status register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PD</name>
- <description>PD</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MPE</name>
- <description>MPE</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WFE</name>
- <description>WFE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MPR</name>
- <description>MPR</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WFR</name>
- <description>WFR</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GU</name>
- <description>GU</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WFFRPR</name>
- <description>WFFRPR</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACDBGR</name>
- <displayName>MACDBGR</displayName>
- <description>Ethernet MAC debug register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CR</name>
- <description>CR</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSR</name>
- <description>CSR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ROR</name>
- <description>ROR</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCF</name>
- <description>MCF</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCP</name>
- <description>MCP</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCFHP</name>
- <description>MCFHP</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACSR</name>
- <displayName>MACSR</displayName>
- <description>Ethernet MAC interrupt status register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PMTS</name>
- <description>PMTS</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMCS</name>
- <description>MMCS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMCRS</name>
- <description>MMCRS</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMCTS</name>
- <description>MMCTS</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TSTS</name>
- <description>TSTS</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>MACIMR</name>
- <displayName>MACIMR</displayName>
- <description>Ethernet MAC interrupt mask register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PMTIM</name>
- <description>PMTIM</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSTIM</name>
- <description>TSTIM</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA0HR</name>
- <displayName>MACA0HR</displayName>
- <description>Ethernet MAC address 0 high register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <resetValue>0x0010FFFF</resetValue>
- <fields>
- <field>
- <name>MACA0H</name>
- <description>MAC address0 high</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MO</name>
- <description>Always 1</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA0LR</name>
- <displayName>MACA0LR</displayName>
- <description>Ethernet MAC address 0 low register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>MACA0L</name>
- <description>0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA1HR</name>
- <displayName>MACA1HR</displayName>
- <description>Ethernet MAC address 1 high register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000FFFF</resetValue>
- <fields>
- <field>
- <name>MACA1H</name>
- <description>MACA1H</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>MBC</name>
- <description>MBC</description>
- <bitOffset>24</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>SA</name>
- <description>SA</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AE</name>
- <description>AE</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA1LR</name>
- <displayName>MACA1LR</displayName>
- <description>Ethernet MAC address1 low register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>MACA1LR</name>
- <description>MACA1LR</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA2HR</name>
- <displayName>MACA2HR</displayName>
- <description>Ethernet MAC address 2 high register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000FFFF</resetValue>
- <fields>
- <field>
- <name>MAC2AH</name>
- <description>MAC2AH</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>MBC</name>
- <description>MBC</description>
- <bitOffset>24</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>SA</name>
- <description>SA</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AE</name>
- <description>AE</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA2LR</name>
- <displayName>MACA2LR</displayName>
- <description>Ethernet MAC address 2 low register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>MACA2L</name>
- <description>MACA2L</description>
- <bitOffset>0</bitOffset>
- <bitWidth>31</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA3HR</name>
- <displayName>MACA3HR</displayName>
- <description>Ethernet MAC address 3 high register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000FFFF</resetValue>
- <fields>
- <field>
- <name>MACA3H</name>
- <description>MACA3H</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>MBC</name>
- <description>MBC</description>
- <bitOffset>24</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>SA</name>
- <description>SA</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AE</name>
- <description>AE</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACA3LR</name>
- <displayName>MACA3LR</displayName>
- <description>Ethernet MAC address 3 low register</description>
- <addressOffset>0x5C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>MBCA3L</name>
- <description>MBCA3L</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MACRWUFFER</name>
- <displayName>MACRWUFFER</displayName>
- <description>Ethernet MAC remote wakeup frame filter register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>Ethernet_MMC</name>
- <description>Ethernet: MAC management counters</description>
- <groupName>Ethernet</groupName>
- <baseAddress>0x40028100</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MMCCR</name>
- <displayName>MMCCR</displayName>
- <description>Ethernet MMC control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CR</name>
- <description>CR</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSR</name>
- <description>CSR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ROR</name>
- <description>ROR</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCF</name>
- <description>MCF</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCP</name>
- <description>MCP</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MCFHP</name>
- <description>MCFHP</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCRIR</name>
- <displayName>MMCRIR</displayName>
- <description>Ethernet MMC receive interrupt register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFCES</name>
- <description>RFCES</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RFAES</name>
- <description>RFAES</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RGUFS</name>
- <description>RGUFS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCTIR</name>
- <displayName>MMCTIR</displayName>
- <description>Ethernet MMC transmit interrupt register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TGFSCS</name>
- <description>TGFSCS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TGFMSCS</name>
- <description>TGFMSCS</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TGFS</name>
- <description>TGFS</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCRIMR</name>
- <displayName>MMCRIMR</displayName>
- <description>Ethernet MMC receive interrupt mask register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFCEM</name>
- <description>RFCEM</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RFAEM</name>
- <description>RFAEM</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RGUFM</name>
- <description>RGUFM</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCTIMR</name>
- <displayName>MMCTIMR</displayName>
- <description>Ethernet MMC transmit interrupt mask register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TGFSCM</name>
- <description>TGFSCM</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TGFMSCM</name>
- <description>TGFMSCM</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TGFM</name>
- <description>TGFM</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCTGFSCCR</name>
- <displayName>MMCTGFSCCR</displayName>
- <description>Ethernet MMC transmitted good frames after a single collision counter</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TGFSCC</name>
- <description>TGFSCC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCTGFMSCCR</name>
- <displayName>MMCTGFMSCCR</displayName>
- <description>Ethernet MMC transmitted good frames after more than a single collision</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TGFMSCC</name>
- <description>TGFMSCC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCTGFCR</name>
- <displayName>MMCTGFCR</displayName>
- <description>Ethernet MMC transmitted good frames counter register</description>
- <addressOffset>0x68</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TGFC</name>
- <description>HTL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCRFCECR</name>
- <displayName>MMCRFCECR</displayName>
- <description>Ethernet MMC received frames with CRC error counter register</description>
- <addressOffset>0x94</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFCFC</name>
- <description>RFCFC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCRFAECR</name>
- <displayName>MMCRFAECR</displayName>
- <description>Ethernet MMC received frames with alignment error counter register</description>
- <addressOffset>0x98</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFAEC</name>
- <description>RFAEC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMCRGUFCR</name>
- <displayName>MMCRGUFCR</displayName>
- <description>MMC received good unicast frames counter register</description>
- <addressOffset>0xC4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RGUFC</name>
- <description>RGUFC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>Ethernet_PTP</name>
- <description>Ethernet: Precision time protocol</description>
- <groupName>Ethernet</groupName>
- <baseAddress>0x40028700</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>PTPTSCR</name>
- <displayName>PTPTSCR</displayName>
- <description>Ethernet PTP time stamp control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00002000</resetValue>
- <fields>
- <field>
- <name>TSE</name>
- <description>TSE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSFCU</name>
- <description>TSFCU</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSPTPPSV2E</name>
- <description>TSPTPPSV2E</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSPTPOEFE</name>
- <description>TSSPTPOEFE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSIPV6FE</name>
- <description>TSSIPV6FE</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSIPV4FE</name>
- <description>TSSIPV4FE</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSEME</name>
- <description>TSSEME</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSMRME</name>
- <description>TSSMRME</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSCNT</name>
- <description>TSCNT</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TSPFFMAE</name>
- <description>TSPFFMAE</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSTI</name>
- <description>TSSTI</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSTU</name>
- <description>TSSTU</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSITE</name>
- <description>TSITE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TTSARU</name>
- <description>TTSARU</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSARFE</name>
- <description>TSSARFE</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSSSR</name>
- <description>TSSSR</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPSSIR</name>
- <displayName>PTPSSIR</displayName>
- <description>Ethernet PTP subsecond increment register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STSSI</name>
- <description>STSSI</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSHR</name>
- <displayName>PTPTSHR</displayName>
- <description>Ethernet PTP time stamp high register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STS</name>
- <description>STS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSLR</name>
- <displayName>PTPTSLR</displayName>
- <description>Ethernet PTP time stamp low register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STSS</name>
- <description>STSS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>31</bitWidth>
- </field>
- <field>
- <name>STPNS</name>
- <description>STPNS</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSHUR</name>
- <displayName>PTPTSHUR</displayName>
- <description>Ethernet PTP time stamp high update register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSUS</name>
- <description>TSUS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSLUR</name>
- <displayName>PTPTSLUR</displayName>
- <description>Ethernet PTP time stamp low update register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSUSS</name>
- <description>TSUSS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>31</bitWidth>
- </field>
- <field>
- <name>TSUPNS</name>
- <description>TSUPNS</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSAR</name>
- <displayName>PTPTSAR</displayName>
- <description>Ethernet PTP time stamp addend register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSA</name>
- <description>TSA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTTHR</name>
- <displayName>PTPTTHR</displayName>
- <description>Ethernet PTP target time high register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TTSH</name>
- <description>0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTTLR</name>
- <displayName>PTPTTLR</displayName>
- <description>Ethernet PTP target time low register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TTSL</name>
- <description>TTSL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPTSSR</name>
- <displayName>PTPTSSR</displayName>
- <description>Ethernet PTP time stamp status register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSSO</name>
- <description>TSSO</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSTTR</name>
- <description>TSTTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PTPPPSCR</name>
- <displayName>PTPPPSCR</displayName>
- <description>Ethernet PTP PPS control register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TSSO</name>
- <description>TSSO</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSTTR</name>
- <description>TSTTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>Ethernet_DMA</name>
- <description>Ethernet: DMA controller operation</description>
- <groupName>Ethernet</groupName>
- <baseAddress>0x40029000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>ETH</name>
- <description>Ethernet global interrupt</description>
- <value>61</value>
- </interrupt>
- <interrupt>
- <name>ETH_WKUP</name>
- <description>Ethernet Wakeup through EXTI line
- interrupt</description>
- <value>62</value>
- </interrupt>
- <registers>
- <register>
- <name>DMABMR</name>
- <displayName>DMABMR</displayName>
- <description>Ethernet DMA bus mode register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00002101</resetValue>
- <fields>
- <field>
- <name>SR</name>
- <description>SR</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DA</name>
- <description>DA</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DSL</name>
- <description>DSL</description>
- <bitOffset>2</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>EDFE</name>
- <description>EDFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PBL</name>
- <description>PBL</description>
- <bitOffset>8</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>RTPR</name>
- <description>RTPR</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FB</name>
- <description>FB</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RDP</name>
- <description>RDP</description>
- <bitOffset>17</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>USP</name>
- <description>USP</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FPM</name>
- <description>FPM</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AAB</name>
- <description>AAB</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MB</name>
- <description>MB</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMATPDR</name>
- <displayName>DMATPDR</displayName>
- <description>Ethernet DMA transmit poll demand register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TPD</name>
- <description>TPD</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMARPDR</name>
- <displayName>DMARPDR</displayName>
- <description>EHERNET DMA receive poll demand register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RPD</name>
- <description>RPD</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMARDLAR</name>
- <displayName>DMARDLAR</displayName>
- <description>Ethernet DMA receive descriptor list address register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SRL</name>
- <description>SRL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMATDLAR</name>
- <displayName>DMATDLAR</displayName>
- <description>Ethernet DMA transmit descriptor list address register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STL</name>
- <description>STL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMASR</name>
- <displayName>DMASR</displayName>
- <description>Ethernet DMA status register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TS</name>
- <description>TS</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TPSS</name>
- <description>TPSS</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TBUS</name>
- <description>TBUS</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TJTS</name>
- <description>TJTS</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ROS</name>
- <description>ROS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TUS</name>
- <description>TUS</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RS</name>
- <description>RS</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RBUS</name>
- <description>RBUS</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RPSS</name>
- <description>RPSS</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PWTS</name>
- <description>PWTS</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ETS</name>
- <description>ETS</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FBES</name>
- <description>FBES</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ERS</name>
- <description>ERS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AIS</name>
- <description>AIS</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NIS</name>
- <description>NIS</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RPS</name>
- <description>RPS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TPS</name>
- <description>TPS</description>
- <bitOffset>20</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EBS</name>
- <description>EBS</description>
- <bitOffset>23</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMCS</name>
- <description>MMCS</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PMTS</name>
- <description>PMTS</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TSTS</name>
- <description>TSTS</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAOMR</name>
- <displayName>DMAOMR</displayName>
- <description>Ethernet DMA operation mode register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SR</name>
- <description>SR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OSF</name>
- <description>OSF</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTC</name>
- <description>RTC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FUGF</name>
- <description>FUGF</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FEF</name>
- <description>FEF</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ST</name>
- <description>ST</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TTC</name>
- <description>TTC</description>
- <bitOffset>14</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>FTF</name>
- <description>FTF</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSF</name>
- <description>TSF</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DFRF</name>
- <description>DFRF</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RSF</name>
- <description>RSF</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTCEFD</name>
- <description>DTCEFD</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAIER</name>
- <displayName>DMAIER</displayName>
- <description>Ethernet DMA interrupt enable register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIE</name>
- <description>TIE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TPSIE</name>
- <description>TPSIE</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TBUIE</name>
- <description>TBUIE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TJTIE</name>
- <description>TJTIE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ROIE</name>
- <description>ROIE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TUIE</name>
- <description>TUIE</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RIE</name>
- <description>RIE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RBUIE</name>
- <description>RBUIE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RPSIE</name>
- <description>RPSIE</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RWTIE</name>
- <description>RWTIE</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ETIE</name>
- <description>ETIE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBEIE</name>
- <description>FBEIE</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERIE</name>
- <description>ERIE</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AISE</name>
- <description>AISE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NISE</name>
- <description>NISE</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMAMFBOCR</name>
- <displayName>DMAMFBOCR</displayName>
- <description>Ethernet DMA missed frame and buffer overflow counter register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MFC</name>
- <description>MFC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>OMFC</name>
- <description>OMFC</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MFA</name>
- <description>MFA</description>
- <bitOffset>17</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>OFOC</name>
- <description>OFOC</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMARSWTR</name>
- <displayName>DMARSWTR</displayName>
- <description>Ethernet DMA receive status watchdog timer register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RSWTC</name>
- <description>RSWTC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMACHTDR</name>
- <displayName>DMACHTDR</displayName>
- <description>Ethernet DMA current host transmit descriptor register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HTDAP</name>
- <description>HTDAP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMACHRDR</name>
- <displayName>DMACHRDR</displayName>
- <description>Ethernet DMA current host receive descriptor register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HRDAP</name>
- <description>HRDAP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMACHTBAR</name>
- <displayName>DMACHTBAR</displayName>
- <description>Ethernet DMA current host transmit buffer address register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HTBAP</name>
- <description>HTBAP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DMACHRBAR</name>
- <displayName>DMACHRBAR</displayName>
- <description>Ethernet DMA current host receive buffer address register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HRBAP</name>
- <description>HRBAP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>CRC</name>
- <description>Cryptographic processor</description>
- <groupName>CRC</groupName>
- <baseAddress>0x40023000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>Data register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xFFFFFFFF</resetValue>
- <fields>
- <field>
- <name>DR</name>
- <description>Data Register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IDR</name>
- <displayName>IDR</displayName>
- <description>Independent Data register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IDR</name>
- <description>Independent Data register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>Control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CR</name>
- <description>Control regidter</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>INIT</name>
- <displayName>INIT</displayName>
- <description>Initial CRC value</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CRC_INIT</name>
- <description>Programmable initial CRC value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>POL</name>
- <displayName>POL</displayName>
- <description>CRC polynomial</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>POL</name>
- <description>Programmable polynomial</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>CAN1</name>
- <description>Controller area network</description>
- <groupName>CAN</groupName>
- <baseAddress>0x40006400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>CAN1_TX</name>
- <description>CAN1 TX interrupts</description>
- <value>19</value>
- </interrupt>
- <interrupt>
- <name>CAN1_RX0</name>
- <description>CAN1 RX0 interrupts</description>
- <value>20</value>
- </interrupt>
- <interrupt>
- <name>CAN1_RX1</name>
- <description>CAN1 RX1 interrupts</description>
- <value>21</value>
- </interrupt>
- <interrupt>
- <name>CAN1_SCE</name>
- <description>CAN1 SCE interrupt</description>
- <value>22</value>
- </interrupt>
- <registers>
- <register>
- <name>MCR</name>
- <displayName>MCR</displayName>
- <description>master control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00010002</resetValue>
- <fields>
- <field>
- <name>DBF</name>
- <description>DBF</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RESET</name>
- <description>RESET</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TTCM</name>
- <description>TTCM</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABOM</name>
- <description>ABOM</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AWUM</name>
- <description>AWUM</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NART</name>
- <description>NART</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RFLM</name>
- <description>RFLM</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFP</name>
- <description>TXFP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SLEEP</name>
- <description>SLEEP</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INRQ</name>
- <description>INRQ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MSR</name>
- <displayName>MSR</displayName>
- <description>master status register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000C02</resetValue>
- <fields>
- <field>
- <name>RX</name>
- <description>RX</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SAMP</name>
- <description>SAMP</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>RXM</name>
- <description>RXM</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXM</name>
- <description>TXM</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SLAKI</name>
- <description>SLAKI</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WKUI</name>
- <description>WKUI</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ERRI</name>
- <description>ERRI</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SLAK</name>
- <description>SLAK</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INAK</name>
- <description>INAK</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>TSR</name>
- <displayName>TSR</displayName>
- <description>transmit status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <resetValue>0x1C000000</resetValue>
- <fields>
- <field>
- <name>LOW2</name>
- <description>Lowest priority flag for mailbox 2</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LOW1</name>
- <description>Lowest priority flag for mailbox 1</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LOW0</name>
- <description>Lowest priority flag for mailbox 0</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TME2</name>
- <description>Lowest priority flag for mailbox 2</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TME1</name>
- <description>Lowest priority flag for mailbox 1</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TME0</name>
- <description>Lowest priority flag for mailbox 0</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CODE</name>
- <description>CODE</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ABRQ2</name>
- <description>ABRQ2</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TERR2</name>
- <description>TERR2</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALST2</name>
- <description>ALST2</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXOK2</name>
- <description>TXOK2</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RQCP2</name>
- <description>RQCP2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ABRQ1</name>
- <description>ABRQ1</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TERR1</name>
- <description>TERR1</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALST1</name>
- <description>ALST1</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXOK1</name>
- <description>TXOK1</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RQCP1</name>
- <description>RQCP1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ABRQ0</name>
- <description>ABRQ0</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TERR0</name>
- <description>TERR0</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALST0</name>
- <description>ALST0</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXOK0</name>
- <description>TXOK0</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RQCP0</name>
- <description>RQCP0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RF0R</name>
- <displayName>RF0R</displayName>
- <description>receive FIFO 0 register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFOM0</name>
- <description>RFOM0</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FOVR0</name>
- <description>FOVR0</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FULL0</name>
- <description>FULL0</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FMP0</name>
- <description>FMP0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>RF1R</name>
- <displayName>RF1R</displayName>
- <description>receive FIFO 1 register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RFOM1</name>
- <description>RFOM1</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FOVR1</name>
- <description>FOVR1</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FULL1</name>
- <description>FULL1</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FMP1</name>
- <description>FMP1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>IER</name>
- <displayName>IER</displayName>
- <description>interrupt enable register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SLKIE</name>
- <description>SLKIE</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WKUIE</name>
- <description>WKUIE</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERRIE</name>
- <description>ERRIE</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LECIE</name>
- <description>LECIE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BOFIE</name>
- <description>BOFIE</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPVIE</name>
- <description>EPVIE</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EWGIE</name>
- <description>EWGIE</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FOVIE1</name>
- <description>FOVIE1</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFIE1</name>
- <description>FFIE1</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FMPIE1</name>
- <description>FMPIE1</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FOVIE0</name>
- <description>FOVIE0</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFIE0</name>
- <description>FFIE0</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FMPIE0</name>
- <description>FMPIE0</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TMEIE</name>
- <description>TMEIE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ESR</name>
- <displayName>ESR</displayName>
- <description>interrupt enable register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>REC</name>
- <description>REC</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TEC</name>
- <description>TEC</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LEC</name>
- <description>LEC</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BOFF</name>
- <description>BOFF</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPVF</name>
- <description>EPVF</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EWGF</name>
- <description>EWGF</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>BTR</name>
- <displayName>BTR</displayName>
- <description>bit timing register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SILM</name>
- <description>SILM</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBKM</name>
- <description>LBKM</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SJW</name>
- <description>SJW</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TS2</name>
- <description>TS2</description>
- <bitOffset>20</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TS1</name>
- <description>TS1</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BRP</name>
- <description>BRP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TI0R</name>
- <displayName>TI0R</displayName>
- <description>TX mailbox identifier register</description>
- <addressOffset>0x180</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STID</name>
- <description>STID</description>
- <bitOffset>21</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EXID</name>
- <description>EXID</description>
- <bitOffset>3</bitOffset>
- <bitWidth>18</bitWidth>
- </field>
- <field>
- <name>IDE</name>
- <description>IDE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTR</name>
- <description>RTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXRQ</name>
- <description>TXRQ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDT0R</name>
- <displayName>TDT0R</displayName>
- <description>mailbox data length control and time stamp register</description>
- <addressOffset>0x184</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIME</name>
- <description>TIME</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>TGT</name>
- <description>TGT</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DLC</name>
- <description>DLC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDL0R</name>
- <displayName>TDL0R</displayName>
- <description>mailbox data low register</description>
- <addressOffset>0x188</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA3</name>
- <description>DATA3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA2</name>
- <description>DATA2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>DATA1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA0</name>
- <description>DATA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDH0R</name>
- <displayName>TDH0R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x18C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA7</name>
- <description>DATA7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA6</name>
- <description>DATA6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA5</name>
- <description>DATA5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA4</name>
- <description>DATA4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TI1R</name>
- <displayName>TI1R</displayName>
- <description>mailbox identifier register</description>
- <addressOffset>0x190</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STID</name>
- <description>STID</description>
- <bitOffset>21</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EXID</name>
- <description>EXID</description>
- <bitOffset>3</bitOffset>
- <bitWidth>18</bitWidth>
- </field>
- <field>
- <name>IDE</name>
- <description>IDE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTR</name>
- <description>RTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXRQ</name>
- <description>TXRQ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDT1R</name>
- <displayName>TDT1R</displayName>
- <description>mailbox data length control and time stamp register</description>
- <addressOffset>0x194</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIME</name>
- <description>TIME</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>TGT</name>
- <description>TGT</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DLC</name>
- <description>DLC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDL1R</name>
- <displayName>TDL1R</displayName>
- <description>mailbox data low register</description>
- <addressOffset>0x198</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA3</name>
- <description>DATA3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA2</name>
- <description>DATA2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>DATA1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA0</name>
- <description>DATA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDH1R</name>
- <displayName>TDH1R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x19C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA7</name>
- <description>DATA7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA6</name>
- <description>DATA6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA5</name>
- <description>DATA5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA4</name>
- <description>DATA4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TI2R</name>
- <displayName>TI2R</displayName>
- <description>mailbox identifier register</description>
- <addressOffset>0x1A0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STID</name>
- <description>STID</description>
- <bitOffset>21</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EXID</name>
- <description>EXID</description>
- <bitOffset>3</bitOffset>
- <bitWidth>18</bitWidth>
- </field>
- <field>
- <name>IDE</name>
- <description>IDE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTR</name>
- <description>RTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXRQ</name>
- <description>TXRQ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDT2R</name>
- <displayName>TDT2R</displayName>
- <description>mailbox data length control and time stamp register</description>
- <addressOffset>0x1A4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIME</name>
- <description>TIME</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>TGT</name>
- <description>TGT</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DLC</name>
- <description>DLC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDL2R</name>
- <displayName>TDL2R</displayName>
- <description>mailbox data low register</description>
- <addressOffset>0x1A8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA3</name>
- <description>DATA3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA2</name>
- <description>DATA2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>DATA1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA0</name>
- <description>DATA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDH2R</name>
- <displayName>TDH2R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1AC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA7</name>
- <description>DATA7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA6</name>
- <description>DATA6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA5</name>
- <description>DATA5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA4</name>
- <description>DATA4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RI0R</name>
- <displayName>RI0R</displayName>
- <description>receive FIFO mailbox identifier register</description>
- <addressOffset>0x1B0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STID</name>
- <description>STID</description>
- <bitOffset>21</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EXID</name>
- <description>EXID</description>
- <bitOffset>3</bitOffset>
- <bitWidth>18</bitWidth>
- </field>
- <field>
- <name>IDE</name>
- <description>IDE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTR</name>
- <description>RTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDT0R</name>
- <displayName>RDT0R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1B4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIME</name>
- <description>TIME</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>FMI</name>
- <description>FMI</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DLC</name>
- <description>DLC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDL0R</name>
- <displayName>RDL0R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1B8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA3</name>
- <description>DATA3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA2</name>
- <description>DATA2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>DATA1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA0</name>
- <description>DATA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDH0R</name>
- <displayName>RDH0R</displayName>
- <description>receive FIFO mailbox data high register</description>
- <addressOffset>0x1BC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA7</name>
- <description>DATA7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA6</name>
- <description>DATA6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA5</name>
- <description>DATA5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA4</name>
- <description>DATA4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RI1R</name>
- <displayName>RI1R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1C0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STID</name>
- <description>STID</description>
- <bitOffset>21</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EXID</name>
- <description>EXID</description>
- <bitOffset>3</bitOffset>
- <bitWidth>18</bitWidth>
- </field>
- <field>
- <name>IDE</name>
- <description>IDE</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTR</name>
- <description>RTR</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDT1R</name>
- <displayName>RDT1R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1C4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIME</name>
- <description>TIME</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>FMI</name>
- <description>FMI</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DLC</name>
- <description>DLC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDL1R</name>
- <displayName>RDL1R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1C8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA3</name>
- <description>DATA3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA2</name>
- <description>DATA2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA1</name>
- <description>DATA1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA0</name>
- <description>DATA0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDH1R</name>
- <displayName>RDH1R</displayName>
- <description>mailbox data high register</description>
- <addressOffset>0x1CC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA7</name>
- <description>DATA7</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA6</name>
- <description>DATA6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA5</name>
- <description>DATA5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DATA4</name>
- <description>DATA4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FMR</name>
- <displayName>FMR</displayName>
- <description>filter master register</description>
- <addressOffset>0x200</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x2A1C0E01</resetValue>
- <fields>
- <field>
- <name>CAN2SB</name>
- <description>CAN2SB</description>
- <bitOffset>8</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>FINIT</name>
- <description>FINIT</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FM1R</name>
- <displayName>FM1R</displayName>
- <description>filter mode register</description>
- <addressOffset>0x204</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FBM0</name>
- <description>Filter mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM1</name>
- <description>Filter mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM2</name>
- <description>Filter mode</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM3</name>
- <description>Filter mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM4</name>
- <description>Filter mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM5</name>
- <description>Filter mode</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM6</name>
- <description>Filter mode</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM7</name>
- <description>Filter mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM8</name>
- <description>Filter mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM9</name>
- <description>Filter mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM10</name>
- <description>Filter mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM11</name>
- <description>Filter mode</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM12</name>
- <description>Filter mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM13</name>
- <description>Filter mode</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM14</name>
- <description>Filter mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM15</name>
- <description>Filter mode</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM16</name>
- <description>Filter mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM17</name>
- <description>Filter mode</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM18</name>
- <description>Filter mode</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM19</name>
- <description>Filter mode</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM20</name>
- <description>Filter mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM21</name>
- <description>Filter mode</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM22</name>
- <description>Filter mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM23</name>
- <description>Filter mode</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM24</name>
- <description>Filter mode</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM25</name>
- <description>Filter mode</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM26</name>
- <description>Filter mode</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FBM27</name>
- <description>Filter mode</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FS1R</name>
- <displayName>FS1R</displayName>
- <description>filter scale register</description>
- <addressOffset>0x20C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FSC0</name>
- <description>Filter scale configuration</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC1</name>
- <description>Filter scale configuration</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC2</name>
- <description>Filter scale configuration</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC3</name>
- <description>Filter scale configuration</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC4</name>
- <description>Filter scale configuration</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC5</name>
- <description>Filter scale configuration</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC6</name>
- <description>Filter scale configuration</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC7</name>
- <description>Filter scale configuration</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC8</name>
- <description>Filter scale configuration</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC9</name>
- <description>Filter scale configuration</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC10</name>
- <description>Filter scale configuration</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC11</name>
- <description>Filter scale configuration</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC12</name>
- <description>Filter scale configuration</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC13</name>
- <description>Filter scale configuration</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC14</name>
- <description>Filter scale configuration</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC15</name>
- <description>Filter scale configuration</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC16</name>
- <description>Filter scale configuration</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC17</name>
- <description>Filter scale configuration</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC18</name>
- <description>Filter scale configuration</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC19</name>
- <description>Filter scale configuration</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC20</name>
- <description>Filter scale configuration</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC21</name>
- <description>Filter scale configuration</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC22</name>
- <description>Filter scale configuration</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC23</name>
- <description>Filter scale configuration</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC24</name>
- <description>Filter scale configuration</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC25</name>
- <description>Filter scale configuration</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC26</name>
- <description>Filter scale configuration</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSC27</name>
- <description>Filter scale configuration</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FFA1R</name>
- <displayName>FFA1R</displayName>
- <description>filter FIFO assignment register</description>
- <addressOffset>0x214</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FFA0</name>
- <description>Filter FIFO assignment for filter 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA1</name>
- <description>Filter FIFO assignment for filter 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA2</name>
- <description>Filter FIFO assignment for filter 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA3</name>
- <description>Filter FIFO assignment for filter 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA4</name>
- <description>Filter FIFO assignment for filter 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA5</name>
- <description>Filter FIFO assignment for filter 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA6</name>
- <description>Filter FIFO assignment for filter 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA7</name>
- <description>Filter FIFO assignment for filter 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA8</name>
- <description>Filter FIFO assignment for filter 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA9</name>
- <description>Filter FIFO assignment for filter 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA10</name>
- <description>Filter FIFO assignment for filter 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA11</name>
- <description>Filter FIFO assignment for filter 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA12</name>
- <description>Filter FIFO assignment for filter 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA13</name>
- <description>Filter FIFO assignment for filter 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA14</name>
- <description>Filter FIFO assignment for filter 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA15</name>
- <description>Filter FIFO assignment for filter 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA16</name>
- <description>Filter FIFO assignment for filter 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA17</name>
- <description>Filter FIFO assignment for filter 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA18</name>
- <description>Filter FIFO assignment for filter 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA19</name>
- <description>Filter FIFO assignment for filter 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA20</name>
- <description>Filter FIFO assignment for filter 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA21</name>
- <description>Filter FIFO assignment for filter 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA22</name>
- <description>Filter FIFO assignment for filter 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA23</name>
- <description>Filter FIFO assignment for filter 23</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA24</name>
- <description>Filter FIFO assignment for filter 24</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA25</name>
- <description>Filter FIFO assignment for filter 25</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA26</name>
- <description>Filter FIFO assignment for filter 26</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFA27</name>
- <description>Filter FIFO assignment for filter 27</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FA1R</name>
- <displayName>FA1R</displayName>
- <description>filter activation register</description>
- <addressOffset>0x21C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FACT0</name>
- <description>Filter active</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT1</name>
- <description>Filter active</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT2</name>
- <description>Filter active</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT3</name>
- <description>Filter active</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT4</name>
- <description>Filter active</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT5</name>
- <description>Filter active</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT6</name>
- <description>Filter active</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT7</name>
- <description>Filter active</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT8</name>
- <description>Filter active</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT9</name>
- <description>Filter active</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT10</name>
- <description>Filter active</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT11</name>
- <description>Filter active</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT12</name>
- <description>Filter active</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT13</name>
- <description>Filter active</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT14</name>
- <description>Filter active</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT15</name>
- <description>Filter active</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT16</name>
- <description>Filter active</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT17</name>
- <description>Filter active</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT18</name>
- <description>Filter active</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT19</name>
- <description>Filter active</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT20</name>
- <description>Filter active</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT21</name>
- <description>Filter active</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT22</name>
- <description>Filter active</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT23</name>
- <description>Filter active</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT24</name>
- <description>Filter active</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT25</name>
- <description>Filter active</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT26</name>
- <description>Filter active</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FACT27</name>
- <description>Filter active</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F0R1</name>
- <displayName>F0R1</displayName>
- <description>Filter bank 0 register 1</description>
- <addressOffset>0x240</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F0R2</name>
- <displayName>F0R2</displayName>
- <description>Filter bank 0 register 2</description>
- <addressOffset>0x244</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F1R1</name>
- <displayName>F1R1</displayName>
- <description>Filter bank 1 register 1</description>
- <addressOffset>0x248</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F1R2</name>
- <displayName>F1R2</displayName>
- <description>Filter bank 1 register 2</description>
- <addressOffset>0x24C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F2R1</name>
- <displayName>F2R1</displayName>
- <description>Filter bank 2 register 1</description>
- <addressOffset>0x250</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F2R2</name>
- <displayName>F2R2</displayName>
- <description>Filter bank 2 register 2</description>
- <addressOffset>0x254</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F3R1</name>
- <displayName>F3R1</displayName>
- <description>Filter bank 3 register 1</description>
- <addressOffset>0x258</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F3R2</name>
- <displayName>F3R2</displayName>
- <description>Filter bank 3 register 2</description>
- <addressOffset>0x25C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F4R1</name>
- <displayName>F4R1</displayName>
- <description>Filter bank 4 register 1</description>
- <addressOffset>0x260</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F4R2</name>
- <displayName>F4R2</displayName>
- <description>Filter bank 4 register 2</description>
- <addressOffset>0x264</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F5R1</name>
- <displayName>F5R1</displayName>
- <description>Filter bank 5 register 1</description>
- <addressOffset>0x268</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F5R2</name>
- <displayName>F5R2</displayName>
- <description>Filter bank 5 register 2</description>
- <addressOffset>0x26C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F6R1</name>
- <displayName>F6R1</displayName>
- <description>Filter bank 6 register 1</description>
- <addressOffset>0x270</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F6R2</name>
- <displayName>F6R2</displayName>
- <description>Filter bank 6 register 2</description>
- <addressOffset>0x274</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F7R1</name>
- <displayName>F7R1</displayName>
- <description>Filter bank 7 register 1</description>
- <addressOffset>0x278</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F7R2</name>
- <displayName>F7R2</displayName>
- <description>Filter bank 7 register 2</description>
- <addressOffset>0x27C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F8R1</name>
- <displayName>F8R1</displayName>
- <description>Filter bank 8 register 1</description>
- <addressOffset>0x280</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F8R2</name>
- <displayName>F8R2</displayName>
- <description>Filter bank 8 register 2</description>
- <addressOffset>0x284</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F9R1</name>
- <displayName>F9R1</displayName>
- <description>Filter bank 9 register 1</description>
- <addressOffset>0x288</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F9R2</name>
- <displayName>F9R2</displayName>
- <description>Filter bank 9 register 2</description>
- <addressOffset>0x28C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F10R1</name>
- <displayName>F10R1</displayName>
- <description>Filter bank 10 register 1</description>
- <addressOffset>0x290</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F10R2</name>
- <displayName>F10R2</displayName>
- <description>Filter bank 10 register 2</description>
- <addressOffset>0x294</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F11R1</name>
- <displayName>F11R1</displayName>
- <description>Filter bank 11 register 1</description>
- <addressOffset>0x298</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F11R2</name>
- <displayName>F11R2</displayName>
- <description>Filter bank 11 register 2</description>
- <addressOffset>0x29C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F12R1</name>
- <displayName>F12R1</displayName>
- <description>Filter bank 4 register 1</description>
- <addressOffset>0x2A0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F12R2</name>
- <displayName>F12R2</displayName>
- <description>Filter bank 12 register 2</description>
- <addressOffset>0x2A4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F13R1</name>
- <displayName>F13R1</displayName>
- <description>Filter bank 13 register 1</description>
- <addressOffset>0x2A8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F13R2</name>
- <displayName>F13R2</displayName>
- <description>Filter bank 13 register 2</description>
- <addressOffset>0x2AC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F14R1</name>
- <displayName>F14R1</displayName>
- <description>Filter bank 14 register 1</description>
- <addressOffset>0x2B0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F14R2</name>
- <displayName>F14R2</displayName>
- <description>Filter bank 14 register 2</description>
- <addressOffset>0x2B4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F15R1</name>
- <displayName>F15R1</displayName>
- <description>Filter bank 15 register 1</description>
- <addressOffset>0x2B8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F15R2</name>
- <displayName>F15R2</displayName>
- <description>Filter bank 15 register 2</description>
- <addressOffset>0x2BC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F16R1</name>
- <displayName>F16R1</displayName>
- <description>Filter bank 16 register 1</description>
- <addressOffset>0x2C0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F16R2</name>
- <displayName>F16R2</displayName>
- <description>Filter bank 16 register 2</description>
- <addressOffset>0x2C4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F17R1</name>
- <displayName>F17R1</displayName>
- <description>Filter bank 17 register 1</description>
- <addressOffset>0x2C8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F17R2</name>
- <displayName>F17R2</displayName>
- <description>Filter bank 17 register 2</description>
- <addressOffset>0x2CC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F18R1</name>
- <displayName>F18R1</displayName>
- <description>Filter bank 18 register 1</description>
- <addressOffset>0x2D0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F18R2</name>
- <displayName>F18R2</displayName>
- <description>Filter bank 18 register 2</description>
- <addressOffset>0x2D4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F19R1</name>
- <displayName>F19R1</displayName>
- <description>Filter bank 19 register 1</description>
- <addressOffset>0x2D8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F19R2</name>
- <displayName>F19R2</displayName>
- <description>Filter bank 19 register 2</description>
- <addressOffset>0x2DC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F20R1</name>
- <displayName>F20R1</displayName>
- <description>Filter bank 20 register 1</description>
- <addressOffset>0x2E0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F20R2</name>
- <displayName>F20R2</displayName>
- <description>Filter bank 20 register 2</description>
- <addressOffset>0x2E4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F21R1</name>
- <displayName>F21R1</displayName>
- <description>Filter bank 21 register 1</description>
- <addressOffset>0x2E8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F21R2</name>
- <displayName>F21R2</displayName>
- <description>Filter bank 21 register 2</description>
- <addressOffset>0x2EC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F22R1</name>
- <displayName>F22R1</displayName>
- <description>Filter bank 22 register 1</description>
- <addressOffset>0x2F0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F22R2</name>
- <displayName>F22R2</displayName>
- <description>Filter bank 22 register 2</description>
- <addressOffset>0x2F4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F23R1</name>
- <displayName>F23R1</displayName>
- <description>Filter bank 23 register 1</description>
- <addressOffset>0x2F8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F23R2</name>
- <displayName>F23R2</displayName>
- <description>Filter bank 23 register 2</description>
- <addressOffset>0x2FC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F24R1</name>
- <displayName>F24R1</displayName>
- <description>Filter bank 24 register 1</description>
- <addressOffset>0x300</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F24R2</name>
- <displayName>F24R2</displayName>
- <description>Filter bank 24 register 2</description>
- <addressOffset>0x304</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F25R1</name>
- <displayName>F25R1</displayName>
- <description>Filter bank 25 register 1</description>
- <addressOffset>0x308</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F25R2</name>
- <displayName>F25R2</displayName>
- <description>Filter bank 25 register 2</description>
- <addressOffset>0x30C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F26R1</name>
- <displayName>F26R1</displayName>
- <description>Filter bank 26 register 1</description>
- <addressOffset>0x310</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F26R2</name>
- <displayName>F26R2</displayName>
- <description>Filter bank 26 register 2</description>
- <addressOffset>0x314</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F27R1</name>
- <displayName>F27R1</displayName>
- <description>Filter bank 27 register 1</description>
- <addressOffset>0x318</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>F27R2</name>
- <displayName>F27R2</displayName>
- <description>Filter bank 27 register 2</description>
- <addressOffset>0x31C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FB0</name>
- <description>Filter bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB1</name>
- <description>Filter bits</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB2</name>
- <description>Filter bits</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB3</name>
- <description>Filter bits</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB4</name>
- <description>Filter bits</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB5</name>
- <description>Filter bits</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB6</name>
- <description>Filter bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB7</name>
- <description>Filter bits</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB8</name>
- <description>Filter bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB9</name>
- <description>Filter bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB10</name>
- <description>Filter bits</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB11</name>
- <description>Filter bits</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB12</name>
- <description>Filter bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB13</name>
- <description>Filter bits</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB14</name>
- <description>Filter bits</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB15</name>
- <description>Filter bits</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB16</name>
- <description>Filter bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB17</name>
- <description>Filter bits</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB18</name>
- <description>Filter bits</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB19</name>
- <description>Filter bits</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB20</name>
- <description>Filter bits</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB21</name>
- <description>Filter bits</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB22</name>
- <description>Filter bits</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB23</name>
- <description>Filter bits</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB24</name>
- <description>Filter bits</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB25</name>
- <description>Filter bits</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB26</name>
- <description>Filter bits</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB27</name>
- <description>Filter bits</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB28</name>
- <description>Filter bits</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB29</name>
- <description>Filter bits</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB30</name>
- <description>Filter bits</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FB31</name>
- <description>Filter bits</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="CAN1">
- <name>CAN2</name>
- <baseAddress>0x40006800</baseAddress>
- <interrupt>
- <name>CAN2_TX</name>
- <description>CAN2 TX interrupts</description>
- <value>63</value>
- </interrupt>
- <interrupt>
- <name>CAN2_RX0</name>
- <description>CAN2 RX0 interrupts</description>
- <value>64</value>
- </interrupt>
- <interrupt>
- <name>CAN2_RX1</name>
- <description>CAN2 RX1 interrupts</description>
- <value>65</value>
- </interrupt>
- <interrupt>
- <name>CAN2_SCE</name>
- <description>CAN2 SCE interrupt</description>
- <value>66</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>FLASH</name>
- <description>FLASH</description>
- <groupName>FLASH</groupName>
- <baseAddress>0x40023C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>FLASH</name>
- <description>Flash global interrupt</description>
- <value>4</value>
- </interrupt>
- <registers>
- <register>
- <name>ACR</name>
- <displayName>ACR</displayName>
- <description>Flash access control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LATENCY</name>
- <description>Latency</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PRFTEN</name>
- <description>Prefetch enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARTEN</name>
- <description>ART Accelerator Enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARTRST</name>
- <description>ART Accelerator reset</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>KEYR</name>
- <displayName>KEYR</displayName>
- <description>Flash key register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>KEY</name>
- <description>FPEC key</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OPTKEYR</name>
- <displayName>OPTKEYR</displayName>
- <description>Flash option key register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OPTKEY</name>
- <description>Option byte key</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>Status register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EOP</name>
- <description>End of operation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OPERR</name>
- <description>Operation error</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WRPERR</name>
- <description>Write protection error</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PGAERR</name>
- <description>Programming alignment error</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PGPERR</name>
- <description>Programming parallelism error</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ERSERR</name>
- <description>Programming sequence error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BSY</name>
- <description>Busy</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>Control register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x80000000</resetValue>
- <fields>
- <field>
- <name>PG</name>
- <description>Programming</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SER</name>
- <description>Sector Erase</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MER</name>
- <description>Mass Erase of sectors 0 to 11</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SNB</name>
- <description>Sector number</description>
- <bitOffset>3</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PSIZE</name>
- <description>Program size</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>STRT</name>
- <description>Start</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOPIE</name>
- <description>End of operation interrupt enable</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERRIE</name>
- <description>Error interrupt enable</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LOCK</name>
- <description>Lock</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OPTCR</name>
- <displayName>OPTCR</displayName>
- <description>Flash option control register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0xC0FFAAFD</resetValue>
- <fields>
- <field>
- <name>OPTLOCK</name>
- <description>Option lock</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPTSTRT</name>
- <description>Option start</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BOR_LEV</name>
- <description>BOR reset Level</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>WWDG_SW</name>
- <description>User option bytes</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IWDG_SW</name>
- <description>User option bytes</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>nRST_STOP</name>
- <description>User option bytes</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>nRST_STDBY</name>
- <description>User option bytes</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RDP</name>
- <description>Read protect</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>nWRP</name>
- <description>Not write protect</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IWDG_STDBY</name>
- <description>Independent watchdog counter freeze in standby mode</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IWDG_STOP</name>
- <description>Independent watchdog counter freeze in Stop mode</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OPTCR1</name>
- <displayName>OPTCR1</displayName>
- <description>Flash option control register 1</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00400080</resetValue>
- <fields>
- <field>
- <name>BOOT_ADD0</name>
- <description>Boot base address when Boot pin =0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>BOOT_ADD1</name>
- <description>Boot base address when Boot pin =1</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>EXTI</name>
- <description>External interrupt/event controller</description>
- <groupName>EXTI</groupName>
- <baseAddress>0x40013C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>TAMP_STAMP</name>
- <description>Tamper and TimeStamp interrupts through the
- EXTI line</description>
- <value>2</value>
- </interrupt>
- <interrupt>
- <name>EXTI0</name>
- <description>EXTI Line0 interrupt</description>
- <value>6</value>
- </interrupt>
- <interrupt>
- <name>EXTI1</name>
- <description>EXTI Line1 interrupt</description>
- <value>7</value>
- </interrupt>
- <interrupt>
- <name>EXTI2</name>
- <description>EXTI Line2 interrupt</description>
- <value>8</value>
- </interrupt>
- <interrupt>
- <name>EXTI3</name>
- <description>EXTI Line3 interrupt</description>
- <value>9</value>
- </interrupt>
- <interrupt>
- <name>EXTI4</name>
- <description>EXTI Line4 interrupt</description>
- <value>10</value>
- </interrupt>
- <interrupt>
- <name>EXTI9_5</name>
- <description>EXTI Line[9:5] interrupts</description>
- <value>23</value>
- </interrupt>
- <interrupt>
- <name>EXTI15_10</name>
- <description>EXTI Line[15:10] interrupts</description>
- <value>40</value>
- </interrupt>
- <interrupt>
- <name>PVD</name>
- <description>PVD through EXTI line detection INTERRUPT</description>
- <value>1</value>
- </interrupt>
- <registers>
- <register>
- <name>IMR</name>
- <displayName>IMR</displayName>
- <description>Interrupt mask register (EXTI_IMR)</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MR0</name>
- <description>Interrupt Mask on line 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR1</name>
- <description>Interrupt Mask on line 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR2</name>
- <description>Interrupt Mask on line 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR3</name>
- <description>Interrupt Mask on line 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR4</name>
- <description>Interrupt Mask on line 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR5</name>
- <description>Interrupt Mask on line 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR6</name>
- <description>Interrupt Mask on line 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR7</name>
- <description>Interrupt Mask on line 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR8</name>
- <description>Interrupt Mask on line 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR9</name>
- <description>Interrupt Mask on line 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR10</name>
- <description>Interrupt Mask on line 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR11</name>
- <description>Interrupt Mask on line 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR12</name>
- <description>Interrupt Mask on line 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR13</name>
- <description>Interrupt Mask on line 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR14</name>
- <description>Interrupt Mask on line 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR15</name>
- <description>Interrupt Mask on line 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR16</name>
- <description>Interrupt Mask on line 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR17</name>
- <description>Interrupt Mask on line 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR18</name>
- <description>Interrupt Mask on line 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR19</name>
- <description>Interrupt Mask on line 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR20</name>
- <description>Interrupt Mask on line 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR21</name>
- <description>Interrupt Mask on line 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR22</name>
- <description>Interrupt Mask on line 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>EMR</name>
- <displayName>EMR</displayName>
- <description>Event mask register (EXTI_EMR)</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MR0</name>
- <description>Event Mask on line 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR1</name>
- <description>Event Mask on line 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR2</name>
- <description>Event Mask on line 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR3</name>
- <description>Event Mask on line 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR4</name>
- <description>Event Mask on line 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR5</name>
- <description>Event Mask on line 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR6</name>
- <description>Event Mask on line 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR7</name>
- <description>Event Mask on line 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR8</name>
- <description>Event Mask on line 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR9</name>
- <description>Event Mask on line 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR10</name>
- <description>Event Mask on line 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR11</name>
- <description>Event Mask on line 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR12</name>
- <description>Event Mask on line 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR13</name>
- <description>Event Mask on line 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR14</name>
- <description>Event Mask on line 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR15</name>
- <description>Event Mask on line 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR16</name>
- <description>Event Mask on line 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR17</name>
- <description>Event Mask on line 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR18</name>
- <description>Event Mask on line 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR19</name>
- <description>Event Mask on line 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR20</name>
- <description>Event Mask on line 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR21</name>
- <description>Event Mask on line 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MR22</name>
- <description>Event Mask on line 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RTSR</name>
- <displayName>RTSR</displayName>
- <description>Rising Trigger selection register (EXTI_RTSR)</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TR0</name>
- <description>Rising trigger event configuration of line 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR1</name>
- <description>Rising trigger event configuration of line 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR2</name>
- <description>Rising trigger event configuration of line 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR3</name>
- <description>Rising trigger event configuration of line 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR4</name>
- <description>Rising trigger event configuration of line 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR5</name>
- <description>Rising trigger event configuration of line 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR6</name>
- <description>Rising trigger event configuration of line 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR7</name>
- <description>Rising trigger event configuration of line 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR8</name>
- <description>Rising trigger event configuration of line 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR9</name>
- <description>Rising trigger event configuration of line 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR10</name>
- <description>Rising trigger event configuration of line 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR11</name>
- <description>Rising trigger event configuration of line 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR12</name>
- <description>Rising trigger event configuration of line 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR13</name>
- <description>Rising trigger event configuration of line 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR14</name>
- <description>Rising trigger event configuration of line 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR15</name>
- <description>Rising trigger event configuration of line 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR16</name>
- <description>Rising trigger event configuration of line 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR17</name>
- <description>Rising trigger event configuration of line 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR18</name>
- <description>Rising trigger event configuration of line 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR19</name>
- <description>Rising trigger event configuration of line 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR20</name>
- <description>Rising trigger event configuration of line 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR21</name>
- <description>Rising trigger event configuration of line 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR22</name>
- <description>Rising trigger event configuration of line 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FTSR</name>
- <displayName>FTSR</displayName>
- <description>Falling Trigger selection register (EXTI_FTSR)</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TR0</name>
- <description>Falling trigger event configuration of line 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR1</name>
- <description>Falling trigger event configuration of line 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR2</name>
- <description>Falling trigger event configuration of line 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR3</name>
- <description>Falling trigger event configuration of line 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR4</name>
- <description>Falling trigger event configuration of line 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR5</name>
- <description>Falling trigger event configuration of line 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR6</name>
- <description>Falling trigger event configuration of line 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR7</name>
- <description>Falling trigger event configuration of line 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR8</name>
- <description>Falling trigger event configuration of line 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR9</name>
- <description>Falling trigger event configuration of line 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR10</name>
- <description>Falling trigger event configuration of line 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR11</name>
- <description>Falling trigger event configuration of line 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR12</name>
- <description>Falling trigger event configuration of line 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR13</name>
- <description>Falling trigger event configuration of line 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR14</name>
- <description>Falling trigger event configuration of line 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR15</name>
- <description>Falling trigger event configuration of line 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR16</name>
- <description>Falling trigger event configuration of line 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR17</name>
- <description>Falling trigger event configuration of line 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR18</name>
- <description>Falling trigger event configuration of line 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR19</name>
- <description>Falling trigger event configuration of line 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR20</name>
- <description>Falling trigger event configuration of line 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR21</name>
- <description>Falling trigger event configuration of line 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TR22</name>
- <description>Falling trigger event configuration of line 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SWIER</name>
- <displayName>SWIER</displayName>
- <description>Software interrupt event register (EXTI_SWIER)</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SWIER0</name>
- <description>Software Interrupt on line 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER1</name>
- <description>Software Interrupt on line 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER2</name>
- <description>Software Interrupt on line 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER3</name>
- <description>Software Interrupt on line 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER4</name>
- <description>Software Interrupt on line 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER5</name>
- <description>Software Interrupt on line 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER6</name>
- <description>Software Interrupt on line 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER7</name>
- <description>Software Interrupt on line 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER8</name>
- <description>Software Interrupt on line 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER9</name>
- <description>Software Interrupt on line 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER10</name>
- <description>Software Interrupt on line 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER11</name>
- <description>Software Interrupt on line 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER12</name>
- <description>Software Interrupt on line 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER13</name>
- <description>Software Interrupt on line 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER14</name>
- <description>Software Interrupt on line 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER15</name>
- <description>Software Interrupt on line 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER16</name>
- <description>Software Interrupt on line 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER17</name>
- <description>Software Interrupt on line 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER18</name>
- <description>Software Interrupt on line 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER19</name>
- <description>Software Interrupt on line 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER20</name>
- <description>Software Interrupt on line 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER21</name>
- <description>Software Interrupt on line 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWIER22</name>
- <description>Software Interrupt on line 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PR</name>
- <displayName>PR</displayName>
- <description>Pending register (EXTI_PR)</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PR0</name>
- <description>Pending bit 0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR1</name>
- <description>Pending bit 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR2</name>
- <description>Pending bit 2</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR3</name>
- <description>Pending bit 3</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR4</name>
- <description>Pending bit 4</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR5</name>
- <description>Pending bit 5</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR6</name>
- <description>Pending bit 6</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR7</name>
- <description>Pending bit 7</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR8</name>
- <description>Pending bit 8</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR9</name>
- <description>Pending bit 9</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR10</name>
- <description>Pending bit 10</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR11</name>
- <description>Pending bit 11</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR12</name>
- <description>Pending bit 12</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR13</name>
- <description>Pending bit 13</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR14</name>
- <description>Pending bit 14</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR15</name>
- <description>Pending bit 15</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR16</name>
- <description>Pending bit 16</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR17</name>
- <description>Pending bit 17</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR18</name>
- <description>Pending bit 18</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR19</name>
- <description>Pending bit 19</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR20</name>
- <description>Pending bit 20</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR21</name>
- <description>Pending bit 21</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PR22</name>
- <description>Pending bit 22</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>LTDC</name>
- <description>LCD-TFT Controller</description>
- <groupName>LTDC</groupName>
- <baseAddress>0x40016800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>LCD_TFT</name>
- <description>LTDC global interrupt</description>
- <value>88</value>
- </interrupt>
- <interrupt>
- <name>LTDC_ER</name>
- <description>LTDC Error global interrupt</description>
- <value>89</value>
- </interrupt>
- <registers>
- <register>
- <name>SSCR</name>
- <displayName>SSCR</displayName>
- <description>Synchronization Size Configuration Register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HSW</name>
- <description>Horizontal Synchronization Width (in units of pixel clock period)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>VSH</name>
- <description>Vertical Synchronization Height (in units of horizontal scan line)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BPCR</name>
- <displayName>BPCR</displayName>
- <description>Back Porch Configuration Register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AHBP</name>
- <description>Accumulated Horizontal back porch (in units of pixel clock period)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>AVBP</name>
- <description>Accumulated Vertical back porch (in units of horizontal scan line)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AWCR</name>
- <displayName>AWCR</displayName>
- <description>Active Width Configuration Register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>AAV</name>
- <description>AAV</description>
- <bitOffset>16</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>AAH</name>
- <description>Accumulated Active Height (in units of horizontal scan line)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TWCR</name>
- <displayName>TWCR</displayName>
- <description>Total Width Configuration Register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TOTALW</name>
- <description>Total Width (in units of pixel clock period)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>TOTALH</name>
- <description>Total Height (in units of horizontal scan line)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GCR</name>
- <displayName>GCR</displayName>
- <description>Global Control Register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <resetValue>0x00002220</resetValue>
- <fields>
- <field>
- <name>HSPOL</name>
- <description>Horizontal Synchronization Polarity</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>VSPOL</name>
- <description>Vertical Synchronization Polarity</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DEPOL</name>
- <description>Data Enable Polarity</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PCPOL</name>
- <description>Pixel Clock Polarity</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DEN</name>
- <description>Dither Enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DRW</name>
- <description>Dither Red Width</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DGW</name>
- <description>Dither Green Width</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DBW</name>
- <description>Dither Blue Width</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LTDCEN</name>
- <description>LCD-TFT controller enable bit</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SRCR</name>
- <displayName>SRCR</displayName>
- <description>Shadow Reload Configuration Register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>VBR</name>
- <description>Vertical Blanking Reload</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IMR</name>
- <description>Immediate Reload</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCCR</name>
- <displayName>BCCR</displayName>
- <description>Background Color Configuration Register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BC</name>
- <description>Background Color Red value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IER</name>
- <displayName>IER</displayName>
- <description>Interrupt Enable Register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RRIE</name>
- <description>Register Reload interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TERRIE</name>
- <description>Transfer Error Interrupt Enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FUIE</name>
- <description>FIFO Underrun Interrupt Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LIE</name>
- <description>Line Interrupt Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt Status Register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RRIF</name>
- <description>Register Reload Interrupt Flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TERRIF</name>
- <description>Transfer Error interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FUIF</name>
- <description>FIFO Underrun Interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LIF</name>
- <description>Line Interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>Interrupt Clear Register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CRRIF</name>
- <description>Clears Register Reload Interrupt Flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTERRIF</name>
- <description>Clears the Transfer Error Interrupt Flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CFUIF</name>
- <description>Clears the FIFO Underrun Interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CLIF</name>
- <description>Clears the Line Interrupt Flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LIPCR</name>
- <displayName>LIPCR</displayName>
- <description>Line Interrupt Position Configuration Register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LIPOS</name>
- <description>Line Interrupt Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CPSR</name>
- <displayName>CPSR</displayName>
- <description>Current Position Status Register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CXPOS</name>
- <description>Current X Position</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CYPOS</name>
- <description>Current Y Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CDSR</name>
- <displayName>CDSR</displayName>
- <description>Current Display Status Register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000000F</resetValue>
- <fields>
- <field>
- <name>HSYNCS</name>
- <description>Horizontal Synchronization display Status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VSYNCS</name>
- <description>Vertical Synchronization display Status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HDES</name>
- <description>Horizontal Data Enable display Status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VDES</name>
- <description>Vertical Data Enable display Status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CR</name>
- <displayName>L1CR</displayName>
- <description>Layerx Control Register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLUTEN</name>
- <description>Color Look-Up Table Enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COLKEN</name>
- <description>Color Keying Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LEN</name>
- <description>Layer Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1WHPCR</name>
- <displayName>L1WHPCR</displayName>
- <description>Layerx Window Horizontal Position Configuration Register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WHSPPOS</name>
- <description>Window Horizontal Stop Position</description>
- <bitOffset>16</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>WHSTPOS</name>
- <description>Window Horizontal Start Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1WVPCR</name>
- <displayName>L1WVPCR</displayName>
- <description>Layerx Window Vertical Position Configuration Register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WVSPPOS</name>
- <description>Window Vertical Stop Position</description>
- <bitOffset>16</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>WVSTPOS</name>
- <description>Window Vertical Start Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CKCR</name>
- <displayName>L1CKCR</displayName>
- <description>Layerx Color Keying Configuration Register</description>
- <addressOffset>0x90</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CKRED</name>
- <description>Color Key Red value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>CKGREEN</name>
- <description>Color Key Green value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>CKBLUE</name>
- <description>Color Key Blue value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1PFCR</name>
- <displayName>L1PFCR</displayName>
- <description>Layerx Pixel Format Configuration Register</description>
- <addressOffset>0x94</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PF</name>
- <description>Pixel Format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CACR</name>
- <displayName>L1CACR</displayName>
- <description>Layerx Constant Alpha Configuration Register</description>
- <addressOffset>0x98</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CONSTA</name>
- <description>Constant Alpha</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1DCCR</name>
- <displayName>L1DCCR</displayName>
- <description>Layerx Default Color Configuration Register</description>
- <addressOffset>0x9C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DCALPHA</name>
- <description>Default Color Alpha</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCRED</name>
- <description>Default Color Red</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCGREEN</name>
- <description>Default Color Green</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCBLUE</name>
- <description>Default Color Blue</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1BFCR</name>
- <displayName>L1BFCR</displayName>
- <description>Layerx Blending Factors Configuration Register</description>
- <addressOffset>0xA0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000607</resetValue>
- <fields>
- <field>
- <name>BF1</name>
- <description>Blending Factor 1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>BF2</name>
- <description>Blending Factor 2</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CFBAR</name>
- <displayName>L1CFBAR</displayName>
- <description>Layerx Color Frame Buffer Address Register</description>
- <addressOffset>0xAC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBADD</name>
- <description>Color Frame Buffer Start Address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CFBLR</name>
- <displayName>L1CFBLR</displayName>
- <description>Layerx Color Frame Buffer Length Register</description>
- <addressOffset>0xB0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBP</name>
- <description>Color Frame Buffer Pitch in bytes</description>
- <bitOffset>16</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- <field>
- <name>CFBLL</name>
- <description>Color Frame Buffer Line Length</description>
- <bitOffset>0</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CFBLNR</name>
- <displayName>L1CFBLNR</displayName>
- <description>Layerx ColorFrame Buffer Line Number Register</description>
- <addressOffset>0xB4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBLNBR</name>
- <description>Frame Buffer Line Number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L1CLUTWR</name>
- <displayName>L1CLUTWR</displayName>
- <description>Layerx CLUT Write Register</description>
- <addressOffset>0xC4</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLUTADD</name>
- <description>CLUT Address</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RED</name>
- <description>Red value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>Green value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>Blue value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CR</name>
- <displayName>L2CR</displayName>
- <description>Layerx Control Register</description>
- <addressOffset>0x104</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLUTEN</name>
- <description>Color Look-Up Table Enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COLKEN</name>
- <description>Color Keying Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LEN</name>
- <description>Layer Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2WHPCR</name>
- <displayName>L2WHPCR</displayName>
- <description>Layerx Window Horizontal Position Configuration Register</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WHSPPOS</name>
- <description>Window Horizontal Stop Position</description>
- <bitOffset>16</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>WHSTPOS</name>
- <description>Window Horizontal Start Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2WVPCR</name>
- <displayName>L2WVPCR</displayName>
- <description>Layerx Window Vertical Position Configuration Register</description>
- <addressOffset>0x10C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WVSPPOS</name>
- <description>Window Vertical Stop Position</description>
- <bitOffset>16</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>WVSTPOS</name>
- <description>Window Vertical Start Position</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CKCR</name>
- <displayName>L2CKCR</displayName>
- <description>Layerx Color Keying Configuration Register</description>
- <addressOffset>0x110</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CKRED</name>
- <description>Color Key Red value</description>
- <bitOffset>15</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>CKGREEN</name>
- <description>Color Key Green value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>CKBLUE</name>
- <description>Color Key Blue value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2PFCR</name>
- <displayName>L2PFCR</displayName>
- <description>Layerx Pixel Format Configuration Register</description>
- <addressOffset>0x114</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PF</name>
- <description>Pixel Format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CACR</name>
- <displayName>L2CACR</displayName>
- <description>Layerx Constant Alpha Configuration Register</description>
- <addressOffset>0x118</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CONSTA</name>
- <description>Constant Alpha</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2DCCR</name>
- <displayName>L2DCCR</displayName>
- <description>Layerx Default Color Configuration Register</description>
- <addressOffset>0x11C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DCALPHA</name>
- <description>Default Color Alpha</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCRED</name>
- <description>Default Color Red</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCGREEN</name>
- <description>Default Color Green</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>DCBLUE</name>
- <description>Default Color Blue</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2BFCR</name>
- <displayName>L2BFCR</displayName>
- <description>Layerx Blending Factors Configuration Register</description>
- <addressOffset>0x120</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000607</resetValue>
- <fields>
- <field>
- <name>BF1</name>
- <description>Blending Factor 1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>BF2</name>
- <description>Blending Factor 2</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CFBAR</name>
- <displayName>L2CFBAR</displayName>
- <description>Layerx Color Frame Buffer Address Register</description>
- <addressOffset>0x12C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBADD</name>
- <description>Color Frame Buffer Start Address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CFBLR</name>
- <displayName>L2CFBLR</displayName>
- <description>Layerx Color Frame Buffer Length Register</description>
- <addressOffset>0x130</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBP</name>
- <description>Color Frame Buffer Pitch in bytes</description>
- <bitOffset>16</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- <field>
- <name>CFBLL</name>
- <description>Color Frame Buffer Line Length</description>
- <bitOffset>0</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CFBLNR</name>
- <displayName>L2CFBLNR</displayName>
- <description>Layerx ColorFrame Buffer Line Number Register</description>
- <addressOffset>0x134</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CFBLNBR</name>
- <description>Frame Buffer Line Number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>L2CLUTWR</name>
- <displayName>L2CLUTWR</displayName>
- <description>Layerx CLUT Write Register</description>
- <addressOffset>0x144</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLUTADD</name>
- <description>CLUT Address</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RED</name>
- <description>Red value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>Green value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>Blue value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SAI1</name>
- <description>Serial audio interface</description>
- <groupName>SAI</groupName>
- <baseAddress>0x40015800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>SAI1</name>
- <description>SAI1 global interrupt</description>
- <value>87</value>
- </interrupt>
- <registers>
- <register>
- <name>BCR1</name>
- <displayName>BCR1</displayName>
- <description>BConfiguration register 1</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000040</resetValue>
- <fields>
- <field>
- <name>MCJDIV</name>
- <description>Master clock divider</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>NODIV</name>
- <description>No divider</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAEN</name>
- <description>DMA enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAIBEN</name>
- <description>Audio block B enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OutDri</name>
- <description>Output drive</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MONO</name>
- <description>Mono mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYNCEN</name>
- <description>Synchronization enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKSTR</name>
- <description>Clock strobing edge</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSBFIRST</name>
- <description>Least significant bit first</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DS</name>
- <description>Data size</description>
- <bitOffset>5</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>PRTCFG</name>
- <description>Protocol configuration</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODE</name>
- <description>Audio block mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCR2</name>
- <displayName>BCR2</displayName>
- <description>BConfiguration register 2</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>COMP</name>
- <description>Companding mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CPL</name>
- <description>Complement bit</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTECN</name>
- <description>Mute counter</description>
- <bitOffset>7</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>MUTEVAL</name>
- <description>Mute value</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTE</name>
- <description>Mute</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TRIS</name>
- <description>Tristate management on data line</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFLUS</name>
- <description>FIFO flush</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BFRCR</name>
- <displayName>BFRCR</displayName>
- <description>BFRCR</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000007</resetValue>
- <fields>
- <field>
- <name>FSOFF</name>
- <description>Frame synchronization offset</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSPOL</name>
- <description>Frame synchronization polarity</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSDEF</name>
- <description>Frame synchronization definition</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSALL</name>
- <description>Frame synchronization active level length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>FRL</name>
- <description>Frame length</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BSLOTR</name>
- <displayName>BSLOTR</displayName>
- <description>BSlot register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SLOTEN</name>
- <description>Slot enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NBSLOT</name>
- <description>Number of slots in an audio frame</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SLOTSZ</name>
- <description>Slot size</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FBOFF</name>
- <description>First bit offset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BIM</name>
- <displayName>BIM</displayName>
- <description>BInterrupt mask register2</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LFSDETIE</name>
- <description>Late frame synchronization detection interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AFSDETIE</name>
- <description>Anticipated frame synchronization detection interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDYIE</name>
- <description>Codec not ready interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FREQIE</name>
- <description>FIFO request interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Wrong clock configuration interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDRIE</name>
- <description>Overrun/underrun interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BSR</name>
- <displayName>BSR</displayName>
- <description>BStatus register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FLVL</name>
- <description>FIFO level threshold</description>
- <bitOffset>16</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>LFSDET</name>
- <description>Late frame synchronization detection</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AFSDET</name>
- <description>Anticipated frame synchronization detection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDY</name>
- <description>Codec not ready</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FREQ</name>
- <description>FIFO request</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Wrong clock configuration flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDR</name>
- <description>Overrun / underrun</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BCLRFR</name>
- <displayName>BCLRFR</displayName>
- <description>BClear flag register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LFSDET</name>
- <description>Clear late frame synchronization detection flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAFSDET</name>
- <description>Clear anticipated frame synchronization detection flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDY</name>
- <description>Clear codec not ready flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Clear wrong clock configuration flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDR</name>
- <description>Clear overrun / underrun</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BDR</name>
- <displayName>BDR</displayName>
- <description>BData register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA</name>
- <description>Data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ACR1</name>
- <displayName>ACR1</displayName>
- <description>AConfiguration register 1</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000040</resetValue>
- <fields>
- <field>
- <name>MCJDIV</name>
- <description>Master clock divider</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>NODIV</name>
- <description>No divider</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAEN</name>
- <description>DMA enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SAIAEN</name>
- <description>Audio block A enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OutDri</name>
- <description>Output drive</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MONO</name>
- <description>Mono mode</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYNCEN</name>
- <description>Synchronization enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKSTR</name>
- <description>Clock strobing edge</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSBFIRST</name>
- <description>Least significant bit first</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DS</name>
- <description>Data size</description>
- <bitOffset>5</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>PRTCFG</name>
- <description>Protocol configuration</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MODE</name>
- <description>Audio block mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ACR2</name>
- <displayName>ACR2</displayName>
- <description>AConfiguration register 2</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>COMP</name>
- <description>Companding mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CPL</name>
- <description>Complement bit</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTECN</name>
- <description>Mute counter</description>
- <bitOffset>7</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>MUTEVAL</name>
- <description>Mute value</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTE</name>
- <description>Mute</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TRIS</name>
- <description>Tristate management on data line</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FFLUS</name>
- <description>FIFO flush</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FTH</name>
- <description>FIFO threshold</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AFRCR</name>
- <displayName>AFRCR</displayName>
- <description>AFRCR</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000007</resetValue>
- <fields>
- <field>
- <name>FSOFF</name>
- <description>Frame synchronization offset</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSPOL</name>
- <description>Frame synchronization polarity</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSDEF</name>
- <description>Frame synchronization definition</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FSALL</name>
- <description>Frame synchronization active level length</description>
- <bitOffset>8</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>FRL</name>
- <description>Frame length</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ASLOTR</name>
- <displayName>ASLOTR</displayName>
- <description>ASlot register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SLOTEN</name>
- <description>Slot enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NBSLOT</name>
- <description>Number of slots in an audio frame</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SLOTSZ</name>
- <description>Slot size</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FBOFF</name>
- <description>First bit offset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AIM</name>
- <displayName>AIM</displayName>
- <description>AInterrupt mask register2</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LFSDET</name>
- <description>Late frame synchronization detection interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AFSDETIE</name>
- <description>Anticipated frame synchronization detection interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDYIE</name>
- <description>Codec not ready interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FREQIE</name>
- <description>FIFO request interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Wrong clock configuration interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDRIE</name>
- <description>Overrun/underrun interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ASR</name>
- <displayName>ASR</displayName>
- <description>AStatus register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FLVL</name>
- <description>FIFO level threshold</description>
- <bitOffset>16</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>LFSDET</name>
- <description>Late frame synchronization detection</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AFSDET</name>
- <description>Anticipated frame synchronization detection</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDY</name>
- <description>Codec not ready</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FREQ</name>
- <description>FIFO request</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Wrong clock configuration flag. This bit is read only.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDR</name>
- <description>Overrun / underrun</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ACLRFR</name>
- <displayName>ACLRFR</displayName>
- <description>AClear flag register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LFSDET</name>
- <description>Clear late frame synchronization detection flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAFSDET</name>
- <description>Clear anticipated frame synchronization detection flag.</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CNRDY</name>
- <description>Clear codec not ready flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WCKCFG</name>
- <description>Clear wrong clock configuration flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUTEDET</name>
- <description>Mute detection flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRUDR</name>
- <description>Clear overrun / underrun</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ADR</name>
- <displayName>ADR</displayName>
- <description>AData register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA</name>
- <description>Data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GCR</name>
- <displayName>GCR</displayName>
- <description>Global configuration register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SYNCIN</name>
- <description>Synchronization inputs</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>SYNCOUT</name>
- <description>Synchronization outputs</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="SAI1">
- <name>SAI2</name>
- <baseAddress>0x40015C00</baseAddress>
- <interrupt>
- <name>SAI2</name>
- <description>SAI2 global interrupt</description>
- <value>91</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>DMA2D</name>
- <description>DMA2D controller</description>
- <groupName>DMA2D</groupName>
- <baseAddress>0x4002B000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0xC00</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>DMA2D</name>
- <description>DMA2D global interrupt</description>
- <value>90</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MODE</name>
- <description>DMA2D mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CEIE</name>
- <description>Configuration Error Interrupt Enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIE</name>
- <description>CLUT transfer complete interrupt enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAEIE</name>
- <description>CLUT access error interrupt enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TWIE</name>
- <description>Transfer watermark interrupt enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABORT</name>
- <description>Abort</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SUSP</name>
- <description>Suspend</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>START</name>
- <description>Start</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt Status Register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CEIF</name>
- <description>Configuration error interrupt flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF</name>
- <description>CLUT transfer complete interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAEIF</name>
- <description>CLUT access error interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TWIF</name>
- <description>Transfer watermark interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIF</name>
- <description>Transfer complete interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIF</name>
- <description>Transfer error interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IFCR</name>
- <displayName>IFCR</displayName>
- <description>interrupt flag clear register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CCEIF</name>
- <description>Clear configuration error interrupt flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCTCIF</name>
- <description>Clear CLUT transfer complete interrupt flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CAECIF</name>
- <description>Clear CLUT access error interrupt flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTWIF</name>
- <description>Clear transfer watermark interrupt flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCIF</name>
- <description>Clear transfer complete interrupt flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEIF</name>
- <description>Clear Transfer error interrupt flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGMAR</name>
- <displayName>FGMAR</displayName>
- <description>foreground memory address register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MA</name>
- <description>Memory address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGOR</name>
- <displayName>FGOR</displayName>
- <description>foreground offset register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LO</name>
- <description>Line offset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGMAR</name>
- <displayName>BGMAR</displayName>
- <description>background memory address register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MA</name>
- <description>Memory address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGOR</name>
- <displayName>BGOR</displayName>
- <description>background offset register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LO</name>
- <description>Line offset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGPFCCR</name>
- <displayName>FGPFCCR</displayName>
- <description>foreground PFC control register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ALPHA</name>
- <description>Alpha value</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>AM</name>
- <description>Alpha mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CS</name>
- <description>CLUT size</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>START</name>
- <description>Start</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCM</name>
- <description>CLUT color mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CM</name>
- <description>Color mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGCOLR</name>
- <displayName>FGCOLR</displayName>
- <description>foreground color register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RED</name>
- <description>Red Value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>Green Value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>Blue Value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGPFCCR</name>
- <displayName>BGPFCCR</displayName>
- <description>background PFC control register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ALPHA</name>
- <description>Alpha value</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>AM</name>
- <description>Alpha mode</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CS</name>
- <description>CLUT size</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>START</name>
- <description>Start</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCM</name>
- <description>CLUT Color mode</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CM</name>
- <description>Color mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGCOLR</name>
- <displayName>BGCOLR</displayName>
- <description>background color register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RED</name>
- <description>Red Value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>Green Value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>Blue Value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGCMAR</name>
- <displayName>FGCMAR</displayName>
- <description>foreground CLUT memory address register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MA</name>
- <description>Memory Address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGCMAR</name>
- <displayName>BGCMAR</displayName>
- <description>background CLUT memory address register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MA</name>
- <description>Memory address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OPFCCR</name>
- <displayName>OPFCCR</displayName>
- <description>output PFC control register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CM</name>
- <description>Color mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OCOLR</name>
- <displayName>OCOLR</displayName>
- <description>output color register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>APLHA</name>
- <description>Alpha Channel Value</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RED</name>
- <description>Red Value</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>Green Value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>Blue Value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OMAR</name>
- <displayName>OMAR</displayName>
- <description>output memory address register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MA</name>
- <description>Memory Address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OOR</name>
- <displayName>OOR</displayName>
- <description>output offset register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LO</name>
- <description>Line Offset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>NLR</name>
- <displayName>NLR</displayName>
- <description>number of line register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PL</name>
- <description>Pixel per lines</description>
- <bitOffset>16</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- <field>
- <name>NL</name>
- <description>Number of lines</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LWR</name>
- <displayName>LWR</displayName>
- <description>line watermark register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LW</name>
- <description>Line watermark</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AMTCR</name>
- <displayName>AMTCR</displayName>
- <description>AHB master timer configuration register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DT</name>
- <description>Dead Time</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FGCLUT</name>
- <displayName>FGCLUT</displayName>
- <description>FGCLUT</description>
- <addressOffset>0x400</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>APLHA</name>
- <description>APLHA</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RED</name>
- <description>RED</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>GREEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>BLUE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BGCLUT</name>
- <displayName>BGCLUT</displayName>
- <description>BGCLUT</description>
- <addressOffset>0x800</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>APLHA</name>
- <description>APLHA</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RED</name>
- <description>RED</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>GREEN</name>
- <description>GREEN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>BLUE</name>
- <description>BLUE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>QUADSPI</name>
- <description>QuadSPI interface</description>
- <groupName>QUADSPI</groupName>
- <baseAddress>0xA0001000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x1000</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>QuadSPI</name>
- <description>QuadSPI global interrupt</description>
- <value>92</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PRESCALER</name>
- <description>Clock prescaler</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>PMM</name>
- <description>Polling match mode</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>APMS</name>
- <description>Automatic poll mode stop</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TOIE</name>
- <description>TimeOut interrupt enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMIE</name>
- <description>Status match interrupt enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FTIE</name>
- <description>FIFO threshold interrupt enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer complete interrupt enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEIE</name>
- <description>Transfer error interrupt enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FTHRES</name>
- <description>IFO threshold level</description>
- <bitOffset>8</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>FSEL</name>
- <description>FLASH memory selection</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DFM</name>
- <description>Dual-flash mode</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SSHIFT</name>
- <description>Sample shift</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCEN</name>
- <description>Timeout counter enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAEN</name>
- <description>DMA enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABORT</name>
- <description>Abort request</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EN</name>
- <description>Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCR</name>
- <displayName>DCR</displayName>
- <description>device configuration register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FSIZE</name>
- <description>FLASH memory size</description>
- <bitOffset>16</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>CSHT</name>
- <description>Chip select high time</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CKMODE</name>
- <description>Mode 0 / mode 3</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FLEVEL</name>
- <description>FIFO level</description>
- <bitOffset>8</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>BUSY</name>
- <description>Busy</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TOF</name>
- <description>Timeout flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMF</name>
- <description>Status match flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FTF</name>
- <description>FIFO threshold flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCF</name>
- <description>Transfer complete flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEF</name>
- <description>Transfer error flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FCR</name>
- <displayName>FCR</displayName>
- <description>flag clear register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CTOF</name>
- <description>Clear timeout flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSMF</name>
- <description>Clear status match flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTCF</name>
- <description>Clear transfer complete flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTEF</name>
- <description>Clear transfer error flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DLR</name>
- <displayName>DLR</displayName>
- <description>data length register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DL</name>
- <description>Data length</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR</name>
- <displayName>CCR</displayName>
- <description>communication configuration register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DDRM</name>
- <description>Double data rate mode</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DHHC</name>
- <description>DDR hold half cycle</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SIOO</name>
- <description>Send instruction only once mode</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FMODE</name>
- <description>Functional mode</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DMODE</name>
- <description>Data mode</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DCYC</name>
- <description>Number of dummy cycles</description>
- <bitOffset>18</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>ABSIZE</name>
- <description>Alternate bytes size</description>
- <bitOffset>16</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ABMODE</name>
- <description>Alternate bytes mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ADSIZE</name>
- <description>Address size</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>ADMODE</name>
- <description>Address mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>IMODE</name>
- <description>Instruction mode</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>INSTRUCTION</name>
- <description>Instruction</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AR</name>
- <displayName>AR</displayName>
- <description>address register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ADDRESS</name>
- <description>Address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ABR</name>
- <displayName>ABR</displayName>
- <description>ABR</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ALTERNATE</name>
- <description>ALTERNATE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>data register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATA</name>
- <description>Data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSMKR</name>
- <displayName>PSMKR</displayName>
- <description>polling status mask register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MASK</name>
- <description>Status mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PSMAR</name>
- <displayName>PSMAR</displayName>
- <description>polling status match register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MATCH</name>
- <description>Status match</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PIR</name>
- <displayName>PIR</displayName>
- <description>polling interval register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INTERVAL</name>
- <description>Polling interval</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>LPTR</name>
- <displayName>LPTR</displayName>
- <description>low-power timeout register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIMEOUT</name>
- <description>Timeout period</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>CEC</name>
- <description>HDMI-CEC controller</description>
- <groupName>CEC</groupName>
- <baseAddress>0x40006C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>HDMI_CEC</name>
- <description>HDMI-CEC global interrupt</description>
- <value>94</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXEOM</name>
- <description>Tx End Of Message</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXSOM</name>
- <description>Tx start of message</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CECEN</name>
- <description>CEC Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CFGR</name>
- <displayName>CFGR</displayName>
- <description>configuration register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SFT</name>
- <description>Signal Free Time</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>RXTOL</name>
- <description>Rx-Tolerance</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BRESTP</name>
- <description>Rx-stop on bit rising error</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BREGEN</name>
- <description>Generate error-bit on bit rising error</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBPEGEN</name>
- <description>Generate Error-Bit on Long Bit Period Error</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BRDNOGEN</name>
- <description>Avoid Error-Bit Generation in Broadcast</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SFTOP</name>
- <description>SFT Option Bit</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OAR</name>
- <description>Own addresses configuration</description>
- <bitOffset>16</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- <field>
- <name>LSTN</name>
- <description>Listen mode</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TXDR</name>
- <displayName>TXDR</displayName>
- <description>Tx data register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXD</name>
- <description>Tx Data register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RXDR</name>
- <displayName>RXDR</displayName>
- <description>Rx Data Register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDR</name>
- <description>CEC Rx Data Register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt and Status Register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXACKE</name>
- <description>Tx-Missing acknowledge error</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Tx-Error</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXUDR</name>
- <description>Tx-Buffer Underrun</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXEND</name>
- <description>End of Transmission</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXBR</name>
- <description>Tx-Byte Request</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARBLST</name>
- <description>Arbitration Lost</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXACKE</name>
- <description>Rx-Missing Acknowledge</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBPE</name>
- <description>Rx-Long Bit Period Error</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBPE</name>
- <description>Rx-Short Bit period error</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BRE</name>
- <description>Rx-Bit rising error</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXOVR</name>
- <description>Rx-Overrun</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXEND</name>
- <description>End Of Reception</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXBR</name>
- <description>Rx-Byte Received</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IER</name>
- <displayName>IER</displayName>
- <description>interrupt enable register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXACKIE</name>
- <description>Tx-Missing Acknowledge Error Interrupt Enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRIE</name>
- <description>Tx-Error Interrupt Enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXUDRIE</name>
- <description>Tx-Underrun interrupt enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXENDIE</name>
- <description>Tx-End of message interrupt enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXBRIE</name>
- <description>Tx-Byte Request Interrupt Enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARBLSTIE</name>
- <description>Arbitration Lost Interrupt Enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXACKIE</name>
- <description>Rx-Missing Acknowledge Error Interrupt Enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBPEIE</name>
- <description>Long Bit Period Error Interrupt Enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBPEIE</name>
- <description>Short Bit Period Error Interrupt Enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BREIE</name>
- <description>Bit Rising Error Interrupt Enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXOVRIE</name>
- <description>Rx-Buffer Overrun Interrupt Enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXENDIE</name>
- <description>End Of Reception Interrupt Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXBRIE</name>
- <description>Rx-Byte Received Interrupt Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SPDIF_RX</name>
- <description>Receiver Interface</description>
- <groupName>SPDIF_RX</groupName>
- <baseAddress>0x40004000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>SPDIFRX</name>
- <description>SPDIFRX global interrupt</description>
- <value>97</value>
- </interrupt>
- <registers>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>Control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SPDIFEN</name>
- <description>Peripheral Block Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>RXDMAEN</name>
- <description>Receiver DMA ENable for data flow</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXSTEO</name>
- <description>STerEO Mode</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DRFMT</name>
- <description>RX Data format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PMSK</name>
- <description>Mask Parity error bit</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VMSK</name>
- <description>Mask of Validity bit</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CUMSK</name>
- <description>Mask of channel status and user bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PTMSK</name>
- <description>Mask of Preamble Type bits</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CBDMAEN</name>
- <description>Control Buffer DMA ENable for control flow</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHSEL</name>
- <description>Channel Selection</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NBTR</name>
- <description>Maximum allowed re-tries during synchronization phase</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>WFA</name>
- <description>Wait For Activity</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INSEL</name>
- <description>input selection</description>
- <bitOffset>16</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IMR</name>
- <displayName>IMR</displayName>
- <description>Interrupt mask register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXNEIE</name>
- <description>RXNE interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSRNEIE</name>
- <description>Control Buffer Ready Interrupt Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PERRIE</name>
- <description>Parity error interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRIE</name>
- <description>Overrun error Interrupt Enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBLKIE</name>
- <description>Synchronization Block Detected Interrupt Enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYNCDIE</name>
- <description>Synchronization Done</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IFEIE</name>
- <description>Serial Interface Error Interrupt Enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SR</name>
- <displayName>SR</displayName>
- <description>Status register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXNE</name>
- <description>Read data register not empty</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CSRNE</name>
- <description>Control Buffer register is not empty</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PERR</name>
- <description>Parity error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVR</name>
- <description>Overrun error</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBD</name>
- <description>Synchronization Block Detected</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYNCD</name>
- <description>Synchronization Done</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FERR</name>
- <description>Framing error</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SERR</name>
- <description>Synchronization error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TERR</name>
- <description>Time-out error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WIDTH5</name>
- <description>Duration of 5 symbols counted with SPDIF_CLK</description>
- <bitOffset>16</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IFCR</name>
- <displayName>IFCR</displayName>
- <description>Interrupt Flag Clear register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PERRCF</name>
- <description>Clears the Parity error flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRCF</name>
- <description>Clears the Overrun error flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBDCF</name>
- <description>Clears the Synchronization Block Detected flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYNCDCF</name>
- <description>Clears the Synchronization Done flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>Data input register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DR</name>
- <description>Parity Error bit</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- <field>
- <name>PE</name>
- <description>Parity Error bit</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>V</name>
- <description>Validity bit</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>U</name>
- <description>User bit</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>C</name>
- <description>Channel Status bit</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PT</name>
- <description>Preamble Type</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CSR</name>
- <displayName>CSR</displayName>
- <description>Channel Status register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>USR</name>
- <description>User data information</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>CS</name>
- <description>Channel A status information</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>SOB</name>
- <description>Start Of Block</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DIR</name>
- <displayName>DIR</displayName>
- <description>Debug Information register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>THI</name>
- <description>Threshold HIGH</description>
- <bitOffset>0</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- <field>
- <name>TLO</name>
- <description>Threshold LOW</description>
- <bitOffset>16</bitOffset>
- <bitWidth>13</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SDMMC1</name>
- <description>Secure digital input/output interface</description>
- <groupName>SDMMC</groupName>
- <baseAddress>0x40012C00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>SDMMC1</name>
- <description>SDMMC1 global interrupt</description>
- <value>49</value>
- </interrupt>
- <registers>
- <register>
- <name>POWER</name>
- <displayName>POWER</displayName>
- <description>power control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PWRCTRL</name>
- <description>PWRCTRL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CLKCR</name>
- <displayName>CLKCR</displayName>
- <description>SDI clock control register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HWFC_EN</name>
- <description>HW Flow Control enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NEGEDGE</name>
- <description>SDIO_CK dephasing selection bit</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WIDBUS</name>
- <description>Wide bus mode enable bit</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>BYPASS</name>
- <description>Clock divider bypass enable bit</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PWRSAV</name>
- <description>Power saving configuration bit</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CLKEN</name>
- <description>Clock enable bit</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CLKDIV</name>
- <description>Clock divide factor</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARG</name>
- <displayName>ARG</displayName>
- <description>argument register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CMDARG</name>
- <description>Command argument</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CMD</name>
- <displayName>CMD</displayName>
- <description>command register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CE_ATACMD</name>
- <description>CE-ATA command</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>nIEN</name>
- <description>not Interrupt Enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ENCMDcompl</name>
- <description>Enable CMD completion</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDIOSuspend</name>
- <description>SD I/O suspend command</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPSMEN</name>
- <description>Command path state machine (CPSM) Enable bit</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITPEND</name>
- <description>CPSM Waits for ends of data transfer (CmdPend internal signal)</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITINT</name>
- <description>CPSM waits for interrupt request</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAITRESP</name>
- <description>Wait for response bits</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CMDINDEX</name>
- <description>Command index</description>
- <bitOffset>0</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RESPCMD</name>
- <displayName>RESPCMD</displayName>
- <description>command response register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RESPCMD</name>
- <description>Response command index</description>
- <bitOffset>0</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RESP1</name>
- <displayName>RESP1</displayName>
- <description>response 1..4 register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CARDSTATUS1</name>
- <description>see Table 132</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RESP2</name>
- <displayName>RESP2</displayName>
- <description>response 1..4 register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CARDSTATUS2</name>
- <description>see Table 132</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RESP3</name>
- <displayName>RESP3</displayName>
- <description>response 1..4 register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CARDSTATUS3</name>
- <description>see Table 132</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RESP4</name>
- <displayName>RESP4</displayName>
- <description>response 1..4 register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CARDSTATUS4</name>
- <description>see Table 132</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DTIMER</name>
- <displayName>DTIMER</displayName>
- <description>data timer register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATATIME</name>
- <description>Data timeout period</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DLEN</name>
- <displayName>DLEN</displayName>
- <description>data length register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATALENGTH</name>
- <description>Data length value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>25</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCTRL</name>
- <displayName>DCTRL</displayName>
- <description>data control register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SDIOEN</name>
- <description>SD I/O enable functions</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RWMOD</name>
- <description>Read wait mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RWSTOP</name>
- <description>Read wait stop</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RWSTART</name>
- <description>Read wait start</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBLOCKSIZE</name>
- <description>Data block size</description>
- <bitOffset>4</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DMAEN</name>
- <description>DMA enable bit</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTMODE</name>
- <description>Data transfer mode selection 1: Stream or SDIO multibyte data transfer</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTDIR</name>
- <description>Data transfer direction selection</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTEN</name>
- <description>DTEN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DCOUNT</name>
- <displayName>DCOUNT</displayName>
- <description>data counter register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DATACOUNT</name>
- <description>Data count value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>25</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>STA</name>
- <displayName>STA</displayName>
- <description>status register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CEATAEND</name>
- <description>CE-ATA command completion signal received for CMD61</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDIOIT</name>
- <description>SDIO interrupt received</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXDAVL</name>
- <description>Data available in receive FIFO</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXDAVL</name>
- <description>Data available in transmit FIFO</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOE</name>
- <description>Receive FIFO empty</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOF</name>
- <description>Receive FIFO full</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOF</name>
- <description>Transmit FIFO full</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOHF</name>
- <description>Receive FIFO half full: there are at least 8 words in the FIFO</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOHE</name>
- <description>Transmit FIFO half empty: at least 8 words can be written into the FIFO</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXACT</name>
- <description>Data receive in progress</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXACT</name>
- <description>Data transmit in progress</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDACT</name>
- <description>Command transfer in progress</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBCKEND</name>
- <description>Data block sent/received (CRC check passed)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STBITERR</name>
- <description>Start bit not detected on all data signals in wide bus mode</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DATAEND</name>
- <description>Data end (data counter, SDIDCOUNT, is zero)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDSENT</name>
- <description>Command sent (no response required)</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDREND</name>
- <description>Command response received (CRC check passed)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXOVERR</name>
- <description>Received FIFO overrun error</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXUNDERR</name>
- <description>Transmit FIFO underrun error</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTIMEOUT</name>
- <description>Data timeout</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTIMEOUT</name>
- <description>Command response timeout</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCRCFAIL</name>
- <description>Data block sent/received (CRC check failed)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCRCFAIL</name>
- <description>Command response received (CRC check failed)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>interrupt clear register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CEATAENDC</name>
- <description>CEATAEND flag clear bit</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDIOITC</name>
- <description>SDIOIT flag clear bit</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBCKENDC</name>
- <description>DBCKEND flag clear bit</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STBITERRC</name>
- <description>STBITERR flag clear bit</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DATAENDC</name>
- <description>DATAEND flag clear bit</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDSENTC</name>
- <description>CMDSENT flag clear bit</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDRENDC</name>
- <description>CMDREND flag clear bit</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXOVERRC</name>
- <description>RXOVERR flag clear bit</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXUNDERRC</name>
- <description>TXUNDERR flag clear bit</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTIMEOUTC</name>
- <description>DTIMEOUT flag clear bit</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTIMEOUTC</name>
- <description>CTIMEOUT flag clear bit</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCRCFAILC</name>
- <description>DCRCFAIL flag clear bit</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCRCFAILC</name>
- <description>CCRCFAIL flag clear bit</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MASK</name>
- <displayName>MASK</displayName>
- <description>mask register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CEATAENDIE</name>
- <description>CE-ATA command completion signal received interrupt enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDIOITIE</name>
- <description>SDIO mode interrupt received interrupt enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXDAVLIE</name>
- <description>Data available in Rx FIFO interrupt enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXDAVLIE</name>
- <description>Data available in Tx FIFO interrupt enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOEIE</name>
- <description>Rx FIFO empty interrupt enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOEIE</name>
- <description>Tx FIFO empty interrupt enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOFIE</name>
- <description>Rx FIFO full interrupt enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOFIE</name>
- <description>Tx FIFO full interrupt enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFIFOHFIE</name>
- <description>Rx FIFO half full interrupt enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFIFOHEIE</name>
- <description>Tx FIFO half empty interrupt enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXACTIE</name>
- <description>Data receive acting interrupt enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXACTIE</name>
- <description>Data transmit acting interrupt enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDACTIE</name>
- <description>Command acting interrupt enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBCKENDIE</name>
- <description>Data block end interrupt enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STBITERRIE</name>
- <description>Start bit error interrupt enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DATAENDIE</name>
- <description>Data end interrupt enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDSENTIE</name>
- <description>Command sent interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMDRENDIE</name>
- <description>Command response received interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXOVERRIE</name>
- <description>Rx FIFO overrun error interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXUNDERRIE</name>
- <description>Tx FIFO underrun error interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTIMEOUTIE</name>
- <description>Data timeout interrupt enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTIMEOUTIE</name>
- <description>Command timeout interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCRCFAILIE</name>
- <description>Data CRC fail interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CCRCFAILIE</name>
- <description>Command CRC fail interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FIFOCNT</name>
- <displayName>FIFOCNT</displayName>
- <description>FIFO counter register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FIFOCOUNT</name>
- <description>Remaining number of words to be written to or read from the FIFO</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FIFO</name>
- <displayName>FIFO</displayName>
- <description>data FIFO register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FIFOData</name>
- <description>Receive and transmit FIFO data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>LPTIM1</name>
- <description>Low power timer</description>
- <groupName>LPTIM</groupName>
- <baseAddress>0x40002400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>LPTIMER1</name>
- <description>LP Timer1 global interrupt</description>
- <value>93</value>
- </interrupt>
- <registers>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt and Status Register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DOWN</name>
- <description>Counter direction change up to down</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UP</name>
- <description>Counter direction change down to up</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARROK</name>
- <description>Autoreload register update OK</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPOK</name>
- <description>Compare register update OK</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTTRIG</name>
- <description>External trigger edge event</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARRM</name>
- <description>Autoreload match</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPM</name>
- <description>Compare match</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>Interrupt Clear Register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DOWNCF</name>
- <description>Direction change to down Clear Flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UPCF</name>
- <description>Direction change to UP Clear Flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARROKCF</name>
- <description>Autoreload register update OK Clear Flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPOKCF</name>
- <description>Compare register update OK Clear Flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTTRIGCF</name>
- <description>External trigger valid edge Clear Flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARRMCF</name>
- <description>Autoreload match Clear Flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPMCF</name>
- <description>compare match Clear Flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IER</name>
- <displayName>IER</displayName>
- <description>Interrupt Enable Register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DOWNIE</name>
- <description>Direction change to down Interrupt Enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UPIE</name>
- <description>Direction change to UP Interrupt Enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARROKIE</name>
- <description>Autoreload register update OK Interrupt Enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPOKIE</name>
- <description>Compare register update OK Interrupt Enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EXTTRIGIE</name>
- <description>External trigger valid edge Interrupt Enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARRMIE</name>
- <description>Autoreload match Interrupt Enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMPMIE</name>
- <description>Compare match Interrupt Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CFGR</name>
- <displayName>CFGR</displayName>
- <description>Configuration Register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ENC</name>
- <description>Encoder mode enable</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COUNTMODE</name>
- <description>counter mode enabled</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PRELOAD</name>
- <description>Registers update mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAVPOL</name>
- <description>Waveform shape polarity</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAVE</name>
- <description>Waveform shape</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIMOUT</name>
- <description>Timeout enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TRIGEN</name>
- <description>Trigger enable and polarity</description>
- <bitOffset>17</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TRIGSEL</name>
- <description>Trigger selector</description>
- <bitOffset>13</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>PRESC</name>
- <description>Clock prescaler</description>
- <bitOffset>9</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TRGFLT</name>
- <description>Configurable digital filter for trigger</description>
- <bitOffset>6</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKFLT</name>
- <description>Configurable digital filter for external clock</description>
- <bitOffset>3</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKPOL</name>
- <description>Clock Polarity</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CKSEL</name>
- <description>Clock selector</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>Control Register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNTSTRT</name>
- <description>Timer start in continuous mode</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SNGSTRT</name>
- <description>LPTIM start in single mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ENABLE</name>
- <description>LPTIM Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CMP</name>
- <displayName>CMP</displayName>
- <description>Compare Register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CMP</name>
- <description>Compare value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ARR</name>
- <displayName>ARR</displayName>
- <description>Autoreload Register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000001</resetValue>
- <fields>
- <field>
- <name>ARR</name>
- <description>Auto reload value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CNT</name>
- <displayName>CNT</displayName>
- <description>Counter Register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CNT</name>
- <description>Counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>I2C1</name>
- <description>Inter-integrated circuit</description>
- <groupName>I2C</groupName>
- <baseAddress>0x40005400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>I2C1_EV</name>
- <description>I2C1 event interrupt</description>
- <value>31</value>
- </interrupt>
- <interrupt>
- <name>I2C1_ER</name>
- <description>I2C1 error interrupt</description>
- <value>32</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>Control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PE</name>
- <description>Peripheral enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXIE</name>
- <description>TX Interrupt enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXIE</name>
- <description>RX Interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADDRIE</name>
- <description>Address match interrupt enable (slave only)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NACKIE</name>
- <description>Not acknowledge received interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STOPIE</name>
- <description>STOP detection Interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transfer Complete interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ERRIE</name>
- <description>Error interrupts enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DNF</name>
- <description>Digital noise filter</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ANFOFF</name>
- <description>Analog noise filter OFF</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXDMAEN</name>
- <description>DMA transmission requests enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXDMAEN</name>
- <description>DMA reception requests enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBC</name>
- <description>Slave byte control</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NOSTRETCH</name>
- <description>Clock stretching disable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WUPEN</name>
- <description>Wakeup from STOP enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GCEN</name>
- <description>General call enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMBHEN</name>
- <description>SMBus Host address enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SMBDEN</name>
- <description>SMBus Device Default address enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ALERTEN</name>
- <description>SMBUS alert enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PECEN</name>
- <description>PEC enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>Control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PECBYTE</name>
- <description>Packet error checking byte</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AUTOEND</name>
- <description>Automatic end mode (master mode)</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RELOAD</name>
- <description>NBYTES reload mode</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NBYTES</name>
- <description>Number of bytes</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>NACK</name>
- <description>NACK generation (slave mode)</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STOP</name>
- <description>Stop generation (master mode)</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>START</name>
- <description>Start generation</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HEAD10R</name>
- <description>10-bit address header only read direction (master receiver mode)</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADD10</name>
- <description>10-bit addressing mode (master mode)</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RD_WRN</name>
- <description>Transfer direction (master mode)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SADD</name>
- <description>Slave address bit (master mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OAR1</name>
- <displayName>OAR1</displayName>
- <description>Own address register 1</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OA1</name>
- <description>Interface address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>OA1MODE</name>
- <description>Own Address 1 10-bit mode</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OA1EN</name>
- <description>Own Address 1 enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OAR2</name>
- <displayName>OAR2</displayName>
- <description>Own address register 2</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>OA2</name>
- <description>Interface address</description>
- <bitOffset>1</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>OA2MSK</name>
- <description>Own Address 2 masks</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>OA2EN</name>
- <description>Own Address 2 enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TIMINGR</name>
- <displayName>TIMINGR</displayName>
- <description>Timing register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SCLL</name>
- <description>SCL low period (master mode)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>SCLH</name>
- <description>SCL high period (master mode)</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>SDADEL</name>
- <description>Data hold time</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SCLDEL</name>
- <description>Data setup time</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PRESC</name>
- <description>Timing prescaler</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TIMEOUTR</name>
- <displayName>TIMEOUTR</displayName>
- <description>Status register 1</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TIMEOUTA</name>
- <description>Bus timeout A</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>TIDLE</name>
- <description>Idle clock timeout detection</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIMOUTEN</name>
- <description>Clock timeout enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIMEOUTB</name>
- <description>Bus timeout B</description>
- <bitOffset>16</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>TEXTEN</name>
- <description>Extended clock timeout enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt and Status register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000001</resetValue>
- <fields>
- <field>
- <name>ADDCODE</name>
- <description>Address match code (Slave mode)</description>
- <bitOffset>17</bitOffset>
- <bitWidth>7</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DIR</name>
- <description>Transfer direction (Slave mode)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BUSY</name>
- <description>Bus busy</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ALERT</name>
- <description>SMBus alert</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TIMEOUT</name>
- <description>Timeout or t_low detection flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PECERR</name>
- <description>PEC Error in reception</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>OVR</name>
- <description>Overrun/Underrun (slave mode)</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ARLO</name>
- <description>Arbitration lost</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Bus error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TCR</name>
- <description>Transfer Complete Reload</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TC</name>
- <description>Transfer Complete (master mode)</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>STOPF</name>
- <description>Stop detection flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NACKF</name>
- <description>Not acknowledge received flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ADDR</name>
- <description>Address matched (slave mode)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>RXNE</name>
- <description>Receive data register not empty (receivers)</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXIS</name>
- <description>Transmit interrupt status (transmitters)</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXE</name>
- <description>Transmit data register empty (transmitters)</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>Interrupt clear register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ALERTCF</name>
- <description>Alert flag clear</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TIMOUTCF</name>
- <description>Timeout detection flag clear</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PECCF</name>
- <description>PEC Error flag clear</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRCF</name>
- <description>Overrun/Underrun flag clear</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ARLOCF</name>
- <description>Arbitration lost flag clear</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BERRCF</name>
- <description>Bus error flag clear</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STOPCF</name>
- <description>Stop detection flag clear</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NACKCF</name>
- <description>Not Acknowledge flag clear</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADDRCF</name>
- <description>Address Matched flag clear</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>PECR</name>
- <displayName>PECR</displayName>
- <description>PEC register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PEC</name>
- <description>Packet error checking register</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RXDR</name>
- <displayName>RXDR</displayName>
- <description>Receive data register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDATA</name>
- <description>8-bit receive data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TXDR</name>
- <displayName>TXDR</displayName>
- <description>Transmit data register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXDATA</name>
- <description>8-bit transmit data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="I2C1">
- <name>I2C2</name>
- <baseAddress>0x40005800</baseAddress>
- <interrupt>
- <name>I2C2_EV</name>
- <description>I2C2 event interrupt</description>
- <value>33</value>
- </interrupt>
- <interrupt>
- <name>I2C2_ER</name>
- <description>I2C2 error interrupt</description>
- <value>34</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="I2C1">
- <name>I2C3</name>
- <baseAddress>0x40005C00</baseAddress>
- <interrupt>
- <name>I2C3_EV</name>
- <description>I2C3 event interrupt</description>
- <value>72</value>
- </interrupt>
- <interrupt>
- <name>I2C3_ER</name>
- <description>I2C3 error interrupt</description>
- <value>73</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="I2C1">
- <name>I2C4</name>
- <baseAddress>0x40006000</baseAddress>
- <interrupt>
- <name>I2C4_EV</name>
- <description>I2C4 event interrupt</description>
- <value>95</value>
- </interrupt>
- <interrupt>
- <name>I2C4_ER</name>
- <description>I2C4 Error interrupt</description>
- <value>96</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>RTC</name>
- <description>Real-time clock</description>
- <groupName>RTC</groupName>
- <baseAddress>0x40002800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>RTC_WKUP</name>
- <description>RTC Tamper or TimeStamp /CSS on LSE through
- EXTI line 19 interrupts</description>
- <value>3</value>
- </interrupt>
- <interrupt>
- <name>RTC_ALARM</name>
- <description>RTC alarms through EXTI line 18
- interrupts</description>
- <value>41</value>
- </interrupt>
- <registers>
- <register>
- <name>TR</name>
- <displayName>TR</displayName>
- <description>time register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PM</name>
- <description>AM/PM notation</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HT</name>
- <description>Hour tens in BCD format</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>HU</name>
- <description>Hour units in BCD format</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MNT</name>
- <description>Minute tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MNU</name>
- <description>Minute units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ST</name>
- <description>Second tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SU</name>
- <description>Second units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DR</name>
- <displayName>DR</displayName>
- <description>date register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00002101</resetValue>
- <fields>
- <field>
- <name>YT</name>
- <description>Year tens in BCD format</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>YU</name>
- <description>Year units in BCD format</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>WDU</name>
- <description>Week day units</description>
- <bitOffset>13</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MT</name>
- <description>Month tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MU</name>
- <description>Month units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DT</name>
- <description>Date tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DU</name>
- <description>Date units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR</name>
- <displayName>CR</displayName>
- <description>control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WCKSEL</name>
- <description>Wakeup clock selection</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TSEDGE</name>
- <description>Time-stamp event active edge</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>REFCKON</name>
- <description>Reference clock detection enable (50 or 60 Hz)</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BYPSHAD</name>
- <description>Bypass the shadow registers</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FMT</name>
- <description>Hour format</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ALRAE</name>
- <description>Alarm A enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ALRBE</name>
- <description>Alarm B enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WUTE</name>
- <description>Wakeup timer enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSE</name>
- <description>Time stamp enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ALRAIE</name>
- <description>Alarm A interrupt enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ALRBIE</name>
- <description>Alarm B interrupt enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WUTIE</name>
- <description>Wakeup timer interrupt enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TSIE</name>
- <description>Time-stamp interrupt enable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADD1H</name>
- <description>Add 1 hour (summer time change)</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SUB1H</name>
- <description>Subtract 1 hour (winter time change)</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BKP</name>
- <description>Backup</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COSEL</name>
- <description>Calibration output selection</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>POL</name>
- <description>Output polarity</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OSEL</name>
- <description>Output selection</description>
- <bitOffset>21</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COE</name>
- <description>Calibration output enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ITSE</name>
- <description>timestamp on internal event enable</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>initialization and status register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000007</resetValue>
- <fields>
- <field>
- <name>ALRAWF</name>
- <description>Alarm A write flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ALRBWF</name>
- <description>Alarm B write flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>WUTWF</name>
- <description>Wakeup timer write flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SHPF</name>
- <description>Shift operation pending</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INITS</name>
- <description>Initialization status flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>RSF</name>
- <description>Registers synchronization flag</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INITF</name>
- <description>Initialization flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INIT</name>
- <description>Initialization mode</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALRAF</name>
- <description>Alarm A flag</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ALRBF</name>
- <description>Alarm B flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUTF</name>
- <description>Wakeup timer flag</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TSF</name>
- <description>Time-stamp flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TSOVF</name>
- <description>Time-stamp overflow flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TAMP1F</name>
- <description>Tamper detection flag</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TAMP2F</name>
- <description>RTC_TAMP2 detection flag</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TAMP3F</name>
- <description>RTC_TAMP3 detection flag</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RECALPF</name>
- <description>Recalibration pending Flag</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>PRER</name>
- <displayName>PRER</displayName>
- <description>prescaler register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x007F00FF</resetValue>
- <fields>
- <field>
- <name>PREDIV_A</name>
- <description>Asynchronous prescaler factor</description>
- <bitOffset>16</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>PREDIV_S</name>
- <description>Synchronous prescaler factor</description>
- <bitOffset>0</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>WUTR</name>
- <displayName>WUTR</displayName>
- <description>wakeup timer register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000FFFF</resetValue>
- <fields>
- <field>
- <name>WUT</name>
- <description>Wakeup auto-reload value bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ALRMAR</name>
- <displayName>ALRMAR</displayName>
- <description>alarm A register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MSK4</name>
- <description>Alarm A date mask</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WDSEL</name>
- <description>Week day selection</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DT</name>
- <description>Date tens in BCD format</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DU</name>
- <description>Date units or day in BCD format</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK3</name>
- <description>Alarm A hours mask</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PM</name>
- <description>AM/PM notation</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HT</name>
- <description>Hour tens in BCD format</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>HU</name>
- <description>Hour units in BCD format</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK2</name>
- <description>Alarm A minutes mask</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MNT</name>
- <description>Minute tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MNU</name>
- <description>Minute units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK1</name>
- <description>Alarm A seconds mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ST</name>
- <description>Second tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SU</name>
- <description>Second units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ALRMBR</name>
- <displayName>ALRMBR</displayName>
- <description>alarm B register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MSK4</name>
- <description>Alarm B date mask</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WDSEL</name>
- <description>Week day selection</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DT</name>
- <description>Date tens in BCD format</description>
- <bitOffset>28</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DU</name>
- <description>Date units or day in BCD format</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK3</name>
- <description>Alarm B hours mask</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PM</name>
- <description>AM/PM notation</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HT</name>
- <description>Hour tens in BCD format</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>HU</name>
- <description>Hour units in BCD format</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK2</name>
- <description>Alarm B minutes mask</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MNT</name>
- <description>Minute tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MNU</name>
- <description>Minute units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MSK1</name>
- <description>Alarm B seconds mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ST</name>
- <description>Second tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>SU</name>
- <description>Second units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>WPR</name>
- <displayName>WPR</displayName>
- <description>write protection register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>KEY</name>
- <description>Write protection key</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SSR</name>
- <displayName>SSR</displayName>
- <description>sub second register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SS</name>
- <description>Sub second value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SHIFTR</name>
- <displayName>SHIFTR</displayName>
- <description>shift control register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ADD1S</name>
- <description>Add one second</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SUBFS</name>
- <description>Subtract a fraction of a second</description>
- <bitOffset>0</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TSTR</name>
- <displayName>TSTR</displayName>
- <description>time stamp time register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SU</name>
- <description>Second units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ST</name>
- <description>Second tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MNU</name>
- <description>Minute units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>MNT</name>
- <description>Minute tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>HU</name>
- <description>Hour units in BCD format</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>HT</name>
- <description>Hour tens in BCD format</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PM</name>
- <description>AM/PM notation</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TSDR</name>
- <displayName>TSDR</displayName>
- <description>time stamp date register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>WDU</name>
- <description>Week day units</description>
- <bitOffset>13</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>MT</name>
- <description>Month tens in BCD format</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MU</name>
- <description>Month units in BCD format</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DT</name>
- <description>Date tens in BCD format</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DU</name>
- <description>Date units in BCD format</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TSSSR</name>
- <displayName>TSSSR</displayName>
- <description>timestamp sub second register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SS</name>
- <description>Sub second value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CALR</name>
- <displayName>CALR</displayName>
- <description>calibration register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CALP</name>
- <description>Increase frequency of RTC by 488.5 ppm</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CALW8</name>
- <description>Use an 8-second calibration cycle period</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CALW16</name>
- <description>Use a 16-second calibration cycle period</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CALM</name>
- <description>Calibration minus</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TAMPCR</name>
- <displayName>TAMPCR</displayName>
- <description>tamper configuration register</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TAMP1E</name>
- <description>Tamper 1 detection enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP1TRG</name>
- <description>Active level for tamper 1</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMPIE</name>
- <description>Tamper interrupt enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP2E</name>
- <description>Tamper 2 detection enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP2TRG</name>
- <description>Active level for tamper 2</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP3E</name>
- <description>Tamper 3 detection enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP3TRG</name>
- <description>Active level for tamper 3</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMPTS</name>
- <description>Activate timestamp on tamper detection event</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMPFREQ</name>
- <description>Tamper sampling frequency</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>TAMPFLT</name>
- <description>Tamper filter count</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TAMPPRCH</name>
- <description>Tamper precharge duration</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TAMPPUDIS</name>
- <description>TAMPER pull-up disable</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP1IE</name>
- <description>Tamper 1 interrupt enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP1NOERASE</name>
- <description>Tamper 1 no erase</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP1MF</name>
- <description>Tamper 1 mask flag</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP2IE</name>
- <description>Tamper 2 interrupt enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP2NOERASE</name>
- <description>Tamper 2 no erase</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP2MF</name>
- <description>Tamper 2 mask flag</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP3IE</name>
- <description>Tamper 3 interrupt enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP3NOERASE</name>
- <description>Tamper 3 no erase</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAMP3MF</name>
- <description>Tamper 3 mask flag</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ALRMASSR</name>
- <displayName>ALRMASSR</displayName>
- <description>alarm A sub second register</description>
- <addressOffset>0x44</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MASKSS</name>
- <description>Mask the most-significant bits starting at this bit</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SS</name>
- <description>Sub seconds value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ALRMBSSR</name>
- <displayName>ALRMBSSR</displayName>
- <description>alarm B sub second register</description>
- <addressOffset>0x48</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MASKSS</name>
- <description>Mask the most-significant bits starting at this bit</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>SS</name>
- <description>Sub seconds value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OR</name>
- <displayName>OR</displayName>
- <description>option register</description>
- <addressOffset>0x4C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RTC_ALARM_TYPE</name>
- <description>RTC_ALARM on PC13 output type</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTC_OUT_RMP</name>
- <description>RTC_OUT remap</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP0R</name>
- <displayName>BKP0R</displayName>
- <description>backup register</description>
- <addressOffset>0x50</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP1R</name>
- <displayName>BKP1R</displayName>
- <description>backup register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP2R</name>
- <displayName>BKP2R</displayName>
- <description>backup register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP3R</name>
- <displayName>BKP3R</displayName>
- <description>backup register</description>
- <addressOffset>0x5C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP4R</name>
- <displayName>BKP4R</displayName>
- <description>backup register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP5R</name>
- <displayName>BKP5R</displayName>
- <description>backup register</description>
- <addressOffset>0x64</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP6R</name>
- <displayName>BKP6R</displayName>
- <description>backup register</description>
- <addressOffset>0x68</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP7R</name>
- <displayName>BKP7R</displayName>
- <description>backup register</description>
- <addressOffset>0x6C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP8R</name>
- <displayName>BKP8R</displayName>
- <description>backup register</description>
- <addressOffset>0x70</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP9R</name>
- <displayName>BKP9R</displayName>
- <description>backup register</description>
- <addressOffset>0x74</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP10R</name>
- <displayName>BKP10R</displayName>
- <description>backup register</description>
- <addressOffset>0x78</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP11R</name>
- <displayName>BKP11R</displayName>
- <description>backup register</description>
- <addressOffset>0x7C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP12R</name>
- <displayName>BKP12R</displayName>
- <description>backup register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP13R</name>
- <displayName>BKP13R</displayName>
- <description>backup register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP14R</name>
- <displayName>BKP14R</displayName>
- <description>backup register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP15R</name>
- <displayName>BKP15R</displayName>
- <description>backup register</description>
- <addressOffset>0x8C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP16R</name>
- <displayName>BKP16R</displayName>
- <description>backup register</description>
- <addressOffset>0x90</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP17R</name>
- <displayName>BKP17R</displayName>
- <description>backup register</description>
- <addressOffset>0x94</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP18R</name>
- <displayName>BKP18R</displayName>
- <description>backup register</description>
- <addressOffset>0x98</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP19R</name>
- <displayName>BKP19R</displayName>
- <description>backup register</description>
- <addressOffset>0x9C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP20R</name>
- <displayName>BKP20R</displayName>
- <description>backup register</description>
- <addressOffset>0xA0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP21R</name>
- <displayName>BKP21R</displayName>
- <description>backup register</description>
- <addressOffset>0xA4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP22R</name>
- <displayName>BKP22R</displayName>
- <description>backup register</description>
- <addressOffset>0xA8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP23R</name>
- <displayName>BKP23R</displayName>
- <description>backup register</description>
- <addressOffset>0xAC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP24R</name>
- <displayName>BKP24R</displayName>
- <description>backup register</description>
- <addressOffset>0xB0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP25R</name>
- <displayName>BKP25R</displayName>
- <description>backup register</description>
- <addressOffset>0xB4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP26R</name>
- <displayName>BKP26R</displayName>
- <description>backup register</description>
- <addressOffset>0xB8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP27R</name>
- <displayName>BKP27R</displayName>
- <description>backup register</description>
- <addressOffset>0xBC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP28R</name>
- <displayName>BKP28R</displayName>
- <description>backup register</description>
- <addressOffset>0xC0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP29R</name>
- <displayName>BKP29R</displayName>
- <description>backup register</description>
- <addressOffset>0xC4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP30R</name>
- <displayName>BKP30R</displayName>
- <description>backup register</description>
- <addressOffset>0xC8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BKP31R</name>
- <displayName>BKP31R</displayName>
- <description>backup register</description>
- <addressOffset>0xCC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>BKP</name>
- <description>BKP</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>USART6</name>
- <description>Universal synchronous asynchronous receiver transmitter</description>
- <groupName>USART</groupName>
- <baseAddress>0x40011400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>USART6</name>
- <description>USART6 global interrupt</description>
- <value>71</value>
- </interrupt>
- <registers>
- <register>
- <name>CR1</name>
- <displayName>CR1</displayName>
- <description>Control register 1</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>M1</name>
- <description>Word length</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOBIE</name>
- <description>End of Block interrupt enable</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTOIE</name>
- <description>Receiver timeout interrupt enable</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEAT4</name>
- <description>Driver Enable assertion time</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEAT3</name>
- <description>DEAT3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEAT2</name>
- <description>DEAT2</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEAT1</name>
- <description>DEAT1</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEAT0</name>
- <description>DEAT0</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEDT4</name>
- <description>Driver Enable de-assertion time</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEDT3</name>
- <description>DEDT3</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEDT2</name>
- <description>DEDT2</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEDT1</name>
- <description>DEDT1</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEDT0</name>
- <description>DEDT0</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVER8</name>
- <description>Oversampling mode</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMIE</name>
- <description>Character match interrupt enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MME</name>
- <description>Mute mode enable</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>M0</name>
- <description>Word length</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WAKE</name>
- <description>Receiver wakeup method</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PCE</name>
- <description>Parity control enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PS</name>
- <description>Parity selection</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PEIE</name>
- <description>PE interrupt enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXEIE</name>
- <description>interrupt enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCIE</name>
- <description>Transmission complete interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXNEIE</name>
- <description>RXNE interrupt enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDLEIE</name>
- <description>IDLE interrupt enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TE</name>
- <description>Transmitter enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RE</name>
- <description>Receiver enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UESM</name>
- <description>USART enable in Stop mode</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UE</name>
- <description>USART enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR2</name>
- <displayName>CR2</displayName>
- <description>Control register 2</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>ADD4_7</name>
- <description>Address of the USART node</description>
- <bitOffset>28</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ADD0_3</name>
- <description>Address of the USART node</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>RTOEN</name>
- <description>Receiver timeout enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABRMOD1</name>
- <description>Auto baud rate mode</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABRMOD0</name>
- <description>ABRMOD0</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABREN</name>
- <description>Auto baud rate enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSBFIRST</name>
- <description>Most significant bit first</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TAINV</name>
- <description>Binary data inversion</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXINV</name>
- <description>TX pin active level inversion</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXINV</name>
- <description>RX pin active level inversion</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SWAP</name>
- <description>Swap TX/RX pins</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LINEN</name>
- <description>LIN mode enable</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STOP</name>
- <description>STOP bits</description>
- <bitOffset>12</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>CLKEN</name>
- <description>Clock enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPOL</name>
- <description>Clock polarity</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CPHA</name>
- <description>Clock phase</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBCL</name>
- <description>Last bit clock pulse</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBDIE</name>
- <description>LIN break detection interrupt enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBDL</name>
- <description>LIN break detection length</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADDM7</name>
- <description>7-bit Address Detection/4-bit Address Detection</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CR3</name>
- <displayName>CR3</displayName>
- <description>Control register 3</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>WUFIE</name>
- <description>Wakeup from Stop mode interrupt enable</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WUS</name>
- <description>Wakeup from Stop mode interrupt flag selection</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>SCARCNT</name>
- <description>Smartcard auto-retry count</description>
- <bitOffset>17</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>DEP</name>
- <description>Driver enable polarity selection</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEM</name>
- <description>Driver enable mode</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DDRE</name>
- <description>DMA Disable on Reception Error</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OVRDIS</name>
- <description>Overrun Disable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ONEBIT</name>
- <description>One sample bit method enable</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTSIE</name>
- <description>CTS interrupt enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTSE</name>
- <description>CTS enable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTSE</name>
- <description>RTS enable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAT</name>
- <description>DMA enable transmitter</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DMAR</name>
- <description>DMA enable receiver</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SCEN</name>
- <description>Smartcard mode enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NACK</name>
- <description>Smartcard NACK enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HDSEL</name>
- <description>Half-duplex selection</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IRLP</name>
- <description>Ir low-power</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IREN</name>
- <description>Ir mode enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EIE</name>
- <description>Error interrupt enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BRR</name>
- <displayName>BRR</displayName>
- <description>Baud rate register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>DIV_Mantissa</name>
- <description>DIV_Mantissa</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>DIV_Fraction</name>
- <description>DIV_Fraction</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>GTPR</name>
- <displayName>GTPR</displayName>
- <description>Guard time and prescaler register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>GT</name>
- <description>Guard time value</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>PSC</name>
- <description>Prescaler value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RTOR</name>
- <displayName>RTOR</displayName>
- <description>Receiver timeout register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>BLEN</name>
- <description>Block Length</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>RTO</name>
- <description>Receiver timeout value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RQR</name>
- <displayName>RQR</displayName>
- <description>Request register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TXFRQ</name>
- <description>Transmit data flush request</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXFRQ</name>
- <description>Receive data flush request</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMRQ</name>
- <description>Mute mode request</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBKRQ</name>
- <description>Send break request</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABRRQ</name>
- <description>Auto baud rate request</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISR</name>
- <displayName>ISR</displayName>
- <description>Interrupt & status register</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00C0</resetValue>
- <fields>
- <field>
- <name>REACK</name>
- <description>REACK</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEACK</name>
- <description>TEACK</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WUF</name>
- <description>WUF</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RWU</name>
- <description>RWU</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SBKF</name>
- <description>SBKF</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMF</name>
- <description>CMF</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BUSY</name>
- <description>BUSY</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABRF</name>
- <description>ABRF</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ABRE</name>
- <description>ABRE</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOBF</name>
- <description>EOBF</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTOF</name>
- <description>RTOF</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTS</name>
- <description>CTS</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTSIF</name>
- <description>CTSIF</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBDF</name>
- <description>LBDF</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXE</name>
- <description>TXE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TC</name>
- <description>TC</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXNE</name>
- <description>RXNE</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDLE</name>
- <description>IDLE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ORE</name>
- <description>ORE</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NF</name>
- <description>NF</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FE</name>
- <description>FE</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PE</name>
- <description>PE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICR</name>
- <displayName>ICR</displayName>
- <description>Interrupt flag clear register</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>write-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>WUCF</name>
- <description>Wakeup from Stop mode clear flag</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CMCF</name>
- <description>Character match clear flag</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EOBCF</name>
- <description>End of block clear flag</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RTOCF</name>
- <description>Receiver timeout clear flag</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CTSCF</name>
- <description>CTS clear flag</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LBDCF</name>
- <description>LIN break detection clear flag</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TCCF</name>
- <description>Transmission complete clear flag</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDLECF</name>
- <description>Idle line detected clear flag</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ORECF</name>
- <description>Overrun error clear flag</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NCF</name>
- <description>Noise detected clear flag</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FECF</name>
- <description>Framing error clear flag</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PECF</name>
- <description>Parity error clear flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RDR</name>
- <displayName>RDR</displayName>
- <description>Receive data register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>RDR</name>
- <description>Receive data value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>TDR</name>
- <displayName>TDR</displayName>
- <description>Transmit data register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000</resetValue>
- <fields>
- <field>
- <name>TDR</name>
- <description>Transmit data value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>USART1</name>
- <baseAddress>0x40011000</baseAddress>
- <interrupt>
- <name>USART1</name>
- <description>USART1 global interrupt</description>
- <value>37</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>USART3</name>
- <baseAddress>0x40004800</baseAddress>
- <interrupt>
- <name>USART3</name>
- <description>USART3 global interrupt</description>
- <value>39</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>USART2</name>
- <baseAddress>0x40004400</baseAddress>
- <interrupt>
- <name>USART2</name>
- <description>USART2 global interrupt</description>
- <value>38</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>UART5</name>
- <baseAddress>0x40005000</baseAddress>
- <interrupt>
- <name>UART5</name>
- <description>UART5 global interrupt</description>
- <value>53</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>UART4</name>
- <baseAddress>0x40004C00</baseAddress>
- <interrupt>
- <name>UART4</name>
- <description>UART4 global interrupt</description>
- <value>52</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>UART8</name>
- <baseAddress>0x40007C00</baseAddress>
- <interrupt>
- <name>UART8</name>
- <description>UART 8 global interrupt</description>
- <value>83</value>
- </interrupt>
- </peripheral>
- <peripheral derivedFrom="USART6">
- <name>UART7</name>
- <baseAddress>0x40007800</baseAddress>
- <interrupt>
- <name>UART7</name>
- <description>UART7 global interrupt</description>
- <value>82</value>
- </interrupt>
- </peripheral>
- <peripheral>
- <name>OTG_FS_GLOBAL</name>
- <description>USB on the go full speed</description>
- <groupName>USB_OTG_FS</groupName>
- <baseAddress>0x50000000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_FS_GOTGCTL</name>
- <displayName>OTG_FS_GOTGCTL</displayName>
- <description>OTG_FS control and status register (OTG_FS_GOTGCTL)</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000800</resetValue>
- <fields>
- <field>
- <name>SRQSCS</name>
- <description>Session request success</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SRQ</name>
- <description>Session request</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HNGSCS</name>
- <description>Host negotiation success</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HNPRQ</name>
- <description>HNP request</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSHNPEN</name>
- <description>Host set HNP enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DHNPEN</name>
- <description>Device HNP enabled</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CIDSTS</name>
- <description>Connector ID status</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DBCT</name>
- <description>Long/short debounce time</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ASVLD</name>
- <description>A-session valid</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BSVLD</name>
- <description>B-session valid</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>VBVALOEN</name>
- <description>VBUS valid override enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>VBVALOVAL</name>
- <description>VBUS valid override value</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AVALOEN</name>
- <description>A-peripheral session valid override enable</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AVALOVAL</name>
- <description>A-peripheral session valid override value</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BVALOEN</name>
- <description>B-peripheral session valid override enable</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BVALOVAL</name>
- <description>B-peripheral session valid override value</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EHEN</name>
- <description>Embedded host enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OTGVER</name>
- <description>OTG version</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GOTGINT</name>
- <displayName>OTG_FS_GOTGINT</displayName>
- <description>OTG_FS interrupt register (OTG_FS_GOTGINT)</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SEDET</name>
- <description>Session end detected</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SRSSCHG</name>
- <description>Session request success status change</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HNSSCHG</name>
- <description>Host negotiation success status change</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HNGDET</name>
- <description>Host negotiation detected</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADTOCHG</name>
- <description>A-device timeout change</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBCDNE</name>
- <description>Debounce done</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDCHNG</name>
- <description>ID input pin changed</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GAHBCFG</name>
- <displayName>OTG_FS_GAHBCFG</displayName>
- <description>OTG_FS AHB configuration register (OTG_FS_GAHBCFG)</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>GINT</name>
- <description>Global interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFELVL</name>
- <description>TxFIFO empty level</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PTXFELVL</name>
- <description>Periodic TxFIFO empty level</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GUSBCFG</name>
- <displayName>OTG_FS_GUSBCFG</displayName>
- <description>OTG_FS USB configuration register (OTG_FS_GUSBCFG)</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000A00</resetValue>
- <fields>
- <field>
- <name>TOCAL</name>
- <description>FS timeout calibration</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PHYSEL</name>
- <description>Full Speed serial transceiver select</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SRPCAP</name>
- <description>SRP-capable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HNPCAP</name>
- <description>HNP-capable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TRDT</name>
- <description>USB turnaround time</description>
- <bitOffset>10</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FHMOD</name>
- <description>Force host mode</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FDMOD</name>
- <description>Force device mode</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRSTCTL</name>
- <displayName>OTG_FS_GRSTCTL</displayName>
- <description>OTG_FS reset register (OTG_FS_GRSTCTL)</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <resetValue>0x20000000</resetValue>
- <fields>
- <field>
- <name>CSRST</name>
- <description>Core soft reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSRST</name>
- <description>HCLK soft reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FCRST</name>
- <description>Host frame counter reset</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFFLSH</name>
- <description>RxFIFO flush</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFFLSH</name>
- <description>TxFIFO flush</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>6</bitOffset>
- <bitWidth>5</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AHBIDL</name>
- <description>AHB master idle</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GINTSTS</name>
- <displayName>OTG_FS_GINTSTS</displayName>
- <description>OTG_FS core interrupt register (OTG_FS_GINTSTS)</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <resetValue>0x04000020</resetValue>
- <fields>
- <field>
- <name>CMOD</name>
- <description>Current mode of operation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMIS</name>
- <description>Mode mismatch interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OTGINT</name>
- <description>OTG interrupt</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SOF</name>
- <description>Start of frame</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFLVL</name>
- <description>RxFIFO non-empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NPTXFE</name>
- <description>Non-periodic TxFIFO empty</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>GINAKEFF</name>
- <description>Global IN non-periodic NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>GOUTNAKEFF</name>
- <description>Global OUT NAK effective</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ESUSP</name>
- <description>Early suspend</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBSUSP</name>
- <description>USB suspend</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBRST</name>
- <description>USB reset</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ENUMDNE</name>
- <description>Enumeration done</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ISOODRP</name>
- <description>Isochronous OUT packet dropped interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EOPF</name>
- <description>End of periodic frame interrupt</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IEPINT</name>
- <description>IN endpoint interrupt</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoint interrupt</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>IISOIXFR</name>
- <description>Incomplete isochronous IN transfer</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IPXFR_INCOMPISOOUT</name>
- <description>Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HPRTINT</name>
- <description>Host port interrupt</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HCINT</name>
- <description>Host channels interrupt</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PTXFE</name>
- <description>Periodic TxFIFO empty</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CIDSCHG</name>
- <description>Connector ID status change</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DISCINT</name>
- <description>Disconnect detected interrupt</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SRQINT</name>
- <description>Session request/new session detected interrupt</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WKUPINT</name>
- <description>Resume/remote wakeup detected interrupt</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RSTDET</name>
- <description>Reset detected interrupt</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GINTMSK</name>
- <displayName>OTG_FS_GINTMSK</displayName>
- <description>OTG_FS interrupt mask register (OTG_FS_GINTMSK)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MMISM</name>
- <description>Mode mismatch interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OTGINT</name>
- <description>OTG interrupt mask</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SOFM</name>
- <description>Start of frame mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFLVLM</name>
- <description>Receive FIFO non-empty mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NPTXFEM</name>
- <description>Non-periodic TxFIFO empty mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GINAKEFFM</name>
- <description>Global non-periodic IN NAK effective mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GONAKEFFM</name>
- <description>Global OUT NAK effective mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ESUSPM</name>
- <description>Early suspend mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBSUSPM</name>
- <description>USB suspend mask</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBRST</name>
- <description>USB reset mask</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ENUMDNEM</name>
- <description>Enumeration done mask</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ISOODRPM</name>
- <description>Isochronous OUT packet dropped interrupt mask</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EOPFM</name>
- <description>End of periodic frame interrupt mask</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IEPINT</name>
- <description>IN endpoints interrupt mask</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoints interrupt mask</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IISOIXFRM</name>
- <description>Incomplete isochronous IN transfer mask</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IPXFRM_IISOOXFRM</name>
- <description>Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRTIM</name>
- <description>Host port interrupt mask</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HCIM</name>
- <description>Host channels interrupt mask</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTXFEM</name>
- <description>Periodic TxFIFO empty mask</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CIDSCHGM</name>
- <description>Connector ID status change mask</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DISCINT</name>
- <description>Disconnect detected interrupt mask</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SRQIM</name>
- <description>Session request/new session detected interrupt mask</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUIM</name>
- <description>Resume/remote wakeup detected interrupt mask</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RSTDETM</name>
- <description>Reset detected interrupt mask</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMIN</name>
- <description>LPM interrupt mask</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRXSTSR_Device</name>
- <displayName>OTG_FS_GRXSTSR_Device</displayName>
- <description>OTG_FS Receive status debug read(Device mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRMNUM</name>
- <description>Frame number</description>
- <bitOffset>21</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRXSTSR_Host</name>
- <displayName>OTG_FS_GRXSTSR_Host</displayName>
- <description>OTG_FS Receive status debug read(Host mode)</description>
- <alternateRegister>OTG_FS_GRXSTSR_Device</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CHNUM</name>
- <description>Endpoint number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRXFSIZ</name>
- <displayName>OTG_FS_GRXFSIZ</displayName>
- <description>OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>RXFD</name>
- <description>RxFIFO depth</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF0_Device</name>
- <displayName>OTG_FS_DIEPTXF0_Device</displayName>
- <description>OTG_FS Endpoint 0 Transmit FIFO size</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>TX0FSA</name>
- <description>Endpoint 0 transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>TX0FD</name>
- <description>Endpoint 0 TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HNPTXFSIZ_Host</name>
- <displayName>OTG_FS_HNPTXFSIZ_Host</displayName>
- <description>OTG_FS Host non-periodic transmit FIFO size register</description>
- <alternateRegister>OTG_FS_DIEPTXF0_Device</alternateRegister>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>NPTXFSA</name>
- <description>Non-periodic transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NPTXFD</name>
- <description>Non-periodic TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HNPTXSTS</name>
- <displayName>OTG_FS_HNPTXSTS</displayName>
- <description>OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00080200</resetValue>
- <fields>
- <field>
- <name>NPTXFSAV</name>
- <description>Non-periodic TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NPTQXSAV</name>
- <description>Non-periodic transmit request queue space available</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>NPTXQTOP</name>
- <description>Top of the non-periodic transmit request queue</description>
- <bitOffset>24</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GCCFG</name>
- <displayName>OTG_FS_GCCFG</displayName>
- <description>OTG_FS general core configuration register (OTG_FS_GCCFG)</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PWRDWN</name>
- <description>Power down</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BCDEN</name>
- <description>Battery charging detector (BCD) enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCDEN</name>
- <description>Data contact detection (DCD) mode enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PDEN</name>
- <description>Primary detection (PD) mode enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDEN</name>
- <description>Secondary detection (SD) mode enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VBDEN</name>
- <description>USB VBUS detection enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCDET</name>
- <description>Data contact detection (DCD) status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PDET</name>
- <description>Primary detection (PD) status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDET</name>
- <description>Secondary detection (SD) status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PS2DET</name>
- <description>DM pull-up detection status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_CID</name>
- <displayName>OTG_FS_CID</displayName>
- <description>core ID register</description>
- <addressOffset>0x3C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00001000</resetValue>
- <fields>
- <field>
- <name>PRODUCT_ID</name>
- <description>Product ID field</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HPTXFSIZ</name>
- <displayName>OTG_FS_HPTXFSIZ</displayName>
- <description>OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)</description>
- <addressOffset>0x100</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000600</resetValue>
- <fields>
- <field>
- <name>PTXSA</name>
- <description>Host periodic TxFIFO start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>PTXFSIZ</name>
- <description>Host periodic TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF1</name>
- <displayName>OTG_FS_DIEPTXF1</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF1)</description>
- <addressOffset>0x104</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFO2 transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF2</name>
- <displayName>OTG_FS_DIEPTXF2</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFO3 transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF3</name>
- <displayName>OTG_FS_DIEPTXF3</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)</description>
- <addressOffset>0x10C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFO4 transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRXSTSP_Device</name>
- <displayName>OTG_FS_GRXSTSP_Device</displayName>
- <description>OTG status read and pop register (Device mode)</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRMNUM</name>
- <description>Frame number</description>
- <bitOffset>21</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GRXSTSP_Host</name>
- <displayName>OTG_FS_GRXSTSP_Host</displayName>
- <description>OTG status read and pop register (Host mode)</description>
- <alternateRegister>OTG_FS_GRXSTSP_Device</alternateRegister>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>CHNUM</name>
- <description>Channel number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GI2CCTL</name>
- <displayName>OTG_FS_GI2CCTL</displayName>
- <description>OTG I2C access register</description>
- <addressOffset>0x30</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>RWDATA</name>
- <description>I2C Read/Write Data</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>REGADDR</name>
- <description>I2C Register Address</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>ADDR</name>
- <description>I2C Address</description>
- <bitOffset>16</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>I2CEN</name>
- <description>I2C Enable</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>I2C ACK</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>I2CDEVADR</name>
- <description>I2C Device Address</description>
- <bitOffset>26</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>I2CDATSE0</name>
- <description>I2C DatSe0 USB mode</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RW</name>
- <description>Read/Write Indicator</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BSYDNE</name>
- <description>I2C Busy/Done</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GPWRDN</name>
- <displayName>OTG_FS_GPWRDN</displayName>
- <description>OTG power down register</description>
- <addressOffset>0x58</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>ADPMEN</name>
- <description>ADP module enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADPIF</name>
- <description>ADP interrupt flag</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GADPCTL</name>
- <displayName>OTG_FS_GADPCTL</displayName>
- <description>OTG ADP timer, control and status register</description>
- <addressOffset>0x60</addressOffset>
- <size>0x20</size>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>PRBDSCHG</name>
- <description>Probe discharge</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRBDELTA</name>
- <description>Probe delta</description>
- <bitOffset>2</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRBPER</name>
- <description>Probe period</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RTIM</name>
- <description>Ramp time</description>
- <bitOffset>6</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ENAPRB</name>
- <description>Enable probe</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ENASNS</name>
- <description>Enable sense</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPRST</name>
- <description>ADP reset</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ADPEN</name>
- <description>ADP enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPPRBIF</name>
- <description>ADP probe interrupt flag</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPSNSIF</name>
- <description>ADP sense interrupt flag</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPTOIF</name>
- <description>ADP timeout interrupt flag</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPPRBIM</name>
- <description>ADP probe interrupt mask</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPSNSIM</name>
- <description>ADP sense interrupt mask</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ADPTOIM</name>
- <description>ADP timeout interrupt mask</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AR</name>
- <description>Access request</description>
- <bitOffset>27</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF4</name>
- <displayName>OTG_FS_DIEPTXF4</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)</description>
- <addressOffset>0x110</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint Tx FIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTXF5</name>
- <displayName>OTG_FS_DIEPTXF5</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF5)</description>
- <addressOffset>0x114</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint Tx FIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_GLPMCFG</name>
- <displayName>OTG_FS_GLPMCFG</displayName>
- <description>OTG core LPM configuration register</description>
- <addressOffset>0x54</addressOffset>
- <size>0x20</size>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>LPMEN</name>
- <description>LPM support enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMACK</name>
- <description>LPM token acknowledge enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BESL</name>
- <description>Best effort service latency</description>
- <bitOffset>2</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>REMWAKE</name>
- <description>bRemoteWake value</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>L1SSEN</name>
- <description>L1 Shallow Sleep enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BESLTHRS</name>
- <description>BESL threshold</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>L1DSEN</name>
- <description>L1 deep sleep enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRST</name>
- <description>LPM response</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SLPSTS</name>
- <description>Port sleep status</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>L1RSMOK</name>
- <description>Sleep State Resume OK</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LPMCHIDX</name>
- <description>LPM Channel Index</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRCNT</name>
- <description>LPM retry count</description>
- <bitOffset>21</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNDLPM</name>
- <description>Send LPM transaction</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRCNTSTS</name>
- <description>LPM retry count status</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ENBESL</name>
- <description>Enable best effort service latency</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_FS_HOST</name>
- <description>USB on the go full speed</description>
- <groupName>USB_OTG_FS</groupName>
- <baseAddress>0x50000400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_FS_HCFG</name>
- <displayName>OTG_FS_HCFG</displayName>
- <description>OTG_FS host configuration register (OTG_FS_HCFG)</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>FSLSPCS</name>
- <description>FS/LS PHY clock select</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FSLSS</name>
- <description>FS- and LS-only support</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HFIR</name>
- <displayName>OTG_FS_HFIR</displayName>
- <description>OTG_FS Host frame interval register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000EA60</resetValue>
- <fields>
- <field>
- <name>FRIVL</name>
- <description>Frame interval</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HFNUM</name>
- <displayName>OTG_FS_HFNUM</displayName>
- <description>OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00003FFF</resetValue>
- <fields>
- <field>
- <name>FRNUM</name>
- <description>Frame number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>FTREM</name>
- <description>Frame time remaining</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HPTXSTS</name>
- <displayName>OTG_FS_HPTXSTS</displayName>
- <description>OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <resetValue>0x00080100</resetValue>
- <fields>
- <field>
- <name>PTXFSAVL</name>
- <description>Periodic transmit data FIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTXQSAV</name>
- <description>Periodic transmit request queue space available</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PTXQTOP</name>
- <description>Top of the periodic transmit request queue</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HAINT</name>
- <displayName>OTG_FS_HAINT</displayName>
- <description>OTG_FS Host all channels interrupt register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HAINT</name>
- <description>Channel interrupts</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HAINTMSK</name>
- <displayName>OTG_FS_HAINTMSK</displayName>
- <description>OTG_FS host all channels interrupt mask register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>HAINTM</name>
- <description>Channel interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HPRT</name>
- <displayName>OTG_FS_HPRT</displayName>
- <description>OTG_FS host port control and status register (OTG_FS_HPRT)</description>
- <addressOffset>0x40</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PCSTS</name>
- <description>Port connect status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PCDET</name>
- <description>Port connect detected</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PENA</name>
- <description>Port enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PENCHNG</name>
- <description>Port enable/disable change</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>POCA</name>
- <description>Port overcurrent active</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>POCCHNG</name>
- <description>Port overcurrent change</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRES</name>
- <description>Port resume</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PSUSP</name>
- <description>Port suspend</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRST</name>
- <description>Port reset</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PLSTS</name>
- <description>Port line status</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PPWR</name>
- <description>Port power</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTCTL</name>
- <description>Port test control</description>
- <bitOffset>13</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PSPD</name>
- <description>Port speed</description>
- <bitOffset>17</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR0</name>
- <displayName>OTG_FS_HCCHAR0</displayName>
- <description>OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)</description>
- <addressOffset>0x100</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR1</name>
- <displayName>OTG_FS_HCCHAR1</displayName>
- <description>OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)</description>
- <addressOffset>0x120</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR2</name>
- <displayName>OTG_FS_HCCHAR2</displayName>
- <description>OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)</description>
- <addressOffset>0x140</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR3</name>
- <displayName>OTG_FS_HCCHAR3</displayName>
- <description>OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)</description>
- <addressOffset>0x160</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR4</name>
- <displayName>OTG_FS_HCCHAR4</displayName>
- <description>OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)</description>
- <addressOffset>0x180</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR5</name>
- <displayName>OTG_FS_HCCHAR5</displayName>
- <description>OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)</description>
- <addressOffset>0x1A0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR6</name>
- <displayName>OTG_FS_HCCHAR6</displayName>
- <description>OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)</description>
- <addressOffset>0x1C0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR7</name>
- <displayName>OTG_FS_HCCHAR7</displayName>
- <description>OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)</description>
- <addressOffset>0x1E0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT0</name>
- <displayName>OTG_FS_HCINT0</displayName>
- <description>OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT1</name>
- <displayName>OTG_FS_HCINT1</displayName>
- <description>OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)</description>
- <addressOffset>0x128</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT2</name>
- <displayName>OTG_FS_HCINT2</displayName>
- <description>OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)</description>
- <addressOffset>0x148</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT3</name>
- <displayName>OTG_FS_HCINT3</displayName>
- <description>OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)</description>
- <addressOffset>0x168</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT4</name>
- <displayName>OTG_FS_HCINT4</displayName>
- <description>OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)</description>
- <addressOffset>0x188</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT5</name>
- <displayName>OTG_FS_HCINT5</displayName>
- <description>OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)</description>
- <addressOffset>0x1A8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT6</name>
- <displayName>OTG_FS_HCINT6</displayName>
- <description>OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)</description>
- <addressOffset>0x1C8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT7</name>
- <displayName>OTG_FS_HCINT7</displayName>
- <description>OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)</description>
- <addressOffset>0x1E8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK0</name>
- <displayName>OTG_FS_HCINTMSK0</displayName>
- <description>OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)</description>
- <addressOffset>0x10C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK1</name>
- <displayName>OTG_FS_HCINTMSK1</displayName>
- <description>OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)</description>
- <addressOffset>0x12C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK2</name>
- <displayName>OTG_FS_HCINTMSK2</displayName>
- <description>OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)</description>
- <addressOffset>0x14C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK3</name>
- <displayName>OTG_FS_HCINTMSK3</displayName>
- <description>OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)</description>
- <addressOffset>0x16C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK4</name>
- <displayName>OTG_FS_HCINTMSK4</displayName>
- <description>OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)</description>
- <addressOffset>0x18C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK5</name>
- <displayName>OTG_FS_HCINTMSK5</displayName>
- <description>OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)</description>
- <addressOffset>0x1AC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK6</name>
- <displayName>OTG_FS_HCINTMSK6</displayName>
- <description>OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)</description>
- <addressOffset>0x1CC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK7</name>
- <displayName>OTG_FS_HCINTMSK7</displayName>
- <description>OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)</description>
- <addressOffset>0x1EC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ0</name>
- <displayName>OTG_FS_HCTSIZ0</displayName>
- <description>OTG_FS host channel-0 transfer size register</description>
- <addressOffset>0x110</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ1</name>
- <displayName>OTG_FS_HCTSIZ1</displayName>
- <description>OTG_FS host channel-1 transfer size register</description>
- <addressOffset>0x130</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ2</name>
- <displayName>OTG_FS_HCTSIZ2</displayName>
- <description>OTG_FS host channel-2 transfer size register</description>
- <addressOffset>0x150</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ3</name>
- <displayName>OTG_FS_HCTSIZ3</displayName>
- <description>OTG_FS host channel-3 transfer size register</description>
- <addressOffset>0x170</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ4</name>
- <displayName>OTG_FS_HCTSIZ4</displayName>
- <description>OTG_FS host channel-x transfer size register</description>
- <addressOffset>0x190</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ5</name>
- <displayName>OTG_FS_HCTSIZ5</displayName>
- <description>OTG_FS host channel-5 transfer size register</description>
- <addressOffset>0x1B0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ6</name>
- <displayName>OTG_FS_HCTSIZ6</displayName>
- <description>OTG_FS host channel-6 transfer size register</description>
- <addressOffset>0x1D0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ7</name>
- <displayName>OTG_FS_HCTSIZ7</displayName>
- <description>OTG_FS host channel-7 transfer size register</description>
- <addressOffset>0x1F0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR8</name>
- <displayName>OTG_FS_HCCHAR8</displayName>
- <description>OTG_FS host channel-8 characteristics register</description>
- <addressOffset>0x1F4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT8</name>
- <displayName>OTG_FS_HCINT8</displayName>
- <description>OTG_FS host channel-8 interrupt register</description>
- <addressOffset>0x1F8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK8</name>
- <displayName>OTG_FS_HCINTMSK8</displayName>
- <description>OTG_FS host channel-8 mask register</description>
- <addressOffset>0x1FC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ8</name>
- <displayName>OTG_FS_HCTSIZ8</displayName>
- <description>OTG_FS host channel-8 transfer size register</description>
- <addressOffset>0x200</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR9</name>
- <displayName>OTG_FS_HCCHAR9</displayName>
- <description>OTG_FS host channel-9 characteristics register</description>
- <addressOffset>0x204</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT9</name>
- <displayName>OTG_FS_HCINT9</displayName>
- <description>OTG_FS host channel-9 interrupt register</description>
- <addressOffset>0x208</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK9</name>
- <displayName>OTG_FS_HCINTMSK9</displayName>
- <description>OTG_FS host channel-9 mask register</description>
- <addressOffset>0x20C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ9</name>
- <displayName>OTG_FS_HCTSIZ9</displayName>
- <description>OTG_FS host channel-9 transfer size register</description>
- <addressOffset>0x210</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR10</name>
- <displayName>OTG_FS_HCCHAR10</displayName>
- <description>OTG_FS host channel-10 characteristics register</description>
- <addressOffset>0x214</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT10</name>
- <displayName>OTG_FS_HCINT10</displayName>
- <description>OTG_FS host channel-10 interrupt register</description>
- <addressOffset>0x218</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK10</name>
- <displayName>OTG_FS_HCINTMSK10</displayName>
- <description>OTG_FS host channel-10 mask register</description>
- <addressOffset>0x21C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ10</name>
- <displayName>OTG_FS_HCTSIZ10</displayName>
- <description>OTG_FS host channel-10 transfer size register</description>
- <addressOffset>0x220</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCCHAR11</name>
- <displayName>OTG_FS_HCCHAR11</displayName>
- <description>OTG_FS host channel-11 characteristics register</description>
- <addressOffset>0x224</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multicount</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINT11</name>
- <displayName>OTG_FS_HCINT11</displayName>
- <description>OTG_FS host channel-11 interrupt register</description>
- <addressOffset>0x228</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCINTMSK11</name>
- <displayName>OTG_FS_HCINTMSK11</displayName>
- <description>OTG_FS host channel-11 mask register</description>
- <addressOffset>0x22C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_HCTSIZ11</name>
- <displayName>OTG_FS_HCTSIZ11</displayName>
- <description>OTG_FS host channel-11 transfer size register</description>
- <addressOffset>0x230</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_FS_DEVICE</name>
- <description>USB on the go full speed</description>
- <groupName>USB_OTG_FS</groupName>
- <baseAddress>0x50000800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_FS_DCFG</name>
- <displayName>OTG_FS_DCFG</displayName>
- <description>OTG_FS device configuration register (OTG_FS_DCFG)</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x02200000</resetValue>
- <fields>
- <field>
- <name>DSPD</name>
- <description>Device speed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NZLSOHSK</name>
- <description>Non-zero-length status OUT handshake</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>4</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>PFIVL</name>
- <description>Periodic frame interval</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DCTL</name>
- <displayName>OTG_FS_DCTL</displayName>
- <description>OTG_FS device control register (OTG_FS_DCTL)</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RWUSIG</name>
- <description>Remote wakeup signaling</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SDIS</name>
- <description>Soft disconnect</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GINSTS</name>
- <description>Global IN NAK status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>GONSTS</name>
- <description>Global OUT NAK status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TCTL</name>
- <description>Test control</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SGINAK</name>
- <description>Set global IN NAK</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CGINAK</name>
- <description>Clear global IN NAK</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SGONAK</name>
- <description>Set global OUT NAK</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CGONAK</name>
- <description>Clear global OUT NAK</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>POPRGDNE</name>
- <description>Power-on programming done</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DSTS</name>
- <displayName>OTG_FS_DSTS</displayName>
- <description>OTG_FS device status register (OTG_FS_DSTS)</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000010</resetValue>
- <fields>
- <field>
- <name>SUSPSTS</name>
- <description>Suspend status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ENUMSPD</name>
- <description>Enumerated speed</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>EERR</name>
- <description>Erratic error</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FNSOF</name>
- <description>Frame number of the received SOF</description>
- <bitOffset>8</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPMSK</name>
- <displayName>OTG_FS_DIEPMSK</displayName>
- <description>OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDM</name>
- <description>Endpoint disabled interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TOM</name>
- <description>Timeout condition mask (Non-isochronous endpoints)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ITTXFEMSK</name>
- <description>IN token received when TxFIFO empty mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INEPNMM</name>
- <description>IN token received with EP mismatch mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INEPNEM</name>
- <description>IN endpoint NAK effective mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPMSK</name>
- <displayName>OTG_FS_DOEPMSK</displayName>
- <description>OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDM</name>
- <description>Endpoint disabled interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUPM</name>
- <description>SETUP phase done mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDM</name>
- <description>OUT token received when endpoint disabled mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DAINT</name>
- <displayName>OTG_FS_DAINT</displayName>
- <description>OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IEPINT</name>
- <description>IN endpoint interrupt bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoint interrupt bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DAINTMSK</name>
- <displayName>OTG_FS_DAINTMSK</displayName>
- <description>OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IEPM</name>
- <description>IN EP interrupt mask bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoint interrupt bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DVBUSDIS</name>
- <displayName>OTG_FS_DVBUSDIS</displayName>
- <description>OTG_FS device VBUS discharge time register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000017D7</resetValue>
- <fields>
- <field>
- <name>VBUSDT</name>
- <description>Device VBUS discharge time</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DVBUSPULSE</name>
- <displayName>OTG_FS_DVBUSPULSE</displayName>
- <description>OTG_FS device VBUS pulsing time register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x000005B8</resetValue>
- <fields>
- <field>
- <name>DVBUSP</name>
- <description>Device VBUS pulsing time</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPEMPMSK</name>
- <displayName>OTG_FS_DIEPEMPMSK</displayName>
- <description>OTG_FS device IN endpoint FIFO empty interrupt mask register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTXFEM</name>
- <description>IN EP Tx FIFO empty interrupt mask bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL0</name>
- <displayName>OTG_FS_DIEPCTL0</displayName>
- <description>OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)</description>
- <addressOffset>0x100</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL1</name>
- <displayName>OTG_FS_DIEPCTL1</displayName>
- <description>OTG device endpoint-1 control register</description>
- <addressOffset>0x120</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM_SD1PID</name>
- <description>SODDFRM/SD1PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TXFNUM</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL2</name>
- <displayName>OTG_FS_DIEPCTL2</displayName>
- <description>OTG device endpoint-2 control register</description>
- <addressOffset>0x140</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TXFNUM</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL3</name>
- <displayName>OTG_FS_DIEPCTL3</displayName>
- <description>OTG device endpoint-3 control register</description>
- <addressOffset>0x160</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TXFNUM</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL0</name>
- <displayName>OTG_FS_DOEPCTL0</displayName>
- <description>device endpoint-0 control register</description>
- <addressOffset>0x300</addressOffset>
- <size>0x20</size>
- <resetValue>0x00008000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL1</name>
- <displayName>OTG_FS_DOEPCTL1</displayName>
- <description>device endpoint-1 control register</description>
- <addressOffset>0x320</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL2</name>
- <displayName>OTG_FS_DOEPCTL2</displayName>
- <description>device endpoint-2 control register</description>
- <addressOffset>0x340</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL3</name>
- <displayName>OTG_FS_DOEPCTL3</displayName>
- <description>device endpoint-3 control register</description>
- <addressOffset>0x360</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT0</name>
- <displayName>OTG_FS_DIEPINT0</displayName>
- <description>device endpoint-x interrupt register</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT1</name>
- <displayName>OTG_FS_DIEPINT1</displayName>
- <description>device endpoint-1 interrupt register</description>
- <addressOffset>0x128</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT2</name>
- <displayName>OTG_FS_DIEPINT2</displayName>
- <description>device endpoint-2 interrupt register</description>
- <addressOffset>0x148</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT3</name>
- <displayName>OTG_FS_DIEPINT3</displayName>
- <description>device endpoint-3 interrupt register</description>
- <addressOffset>0x168</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT0</name>
- <displayName>OTG_FS_DOEPINT0</displayName>
- <description>device endpoint-0 interrupt register</description>
- <addressOffset>0x308</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT1</name>
- <displayName>OTG_FS_DOEPINT1</displayName>
- <description>device endpoint-1 interrupt register</description>
- <addressOffset>0x328</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT2</name>
- <displayName>OTG_FS_DOEPINT2</displayName>
- <description>device endpoint-2 interrupt register</description>
- <addressOffset>0x348</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT3</name>
- <displayName>OTG_FS_DOEPINT3</displayName>
- <description>device endpoint-3 interrupt register</description>
- <addressOffset>0x368</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ0</name>
- <displayName>OTG_FS_DIEPTSIZ0</displayName>
- <description>device endpoint-0 transfer size register</description>
- <addressOffset>0x110</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ0</name>
- <displayName>OTG_FS_DOEPTSIZ0</displayName>
- <description>device OUT endpoint-0 transfer size register</description>
- <addressOffset>0x310</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STUPCNT</name>
- <description>SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ1</name>
- <displayName>OTG_FS_DIEPTSIZ1</displayName>
- <description>device endpoint-1 transfer size register</description>
- <addressOffset>0x130</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ2</name>
- <displayName>OTG_FS_DIEPTSIZ2</displayName>
- <description>device endpoint-2 transfer size register</description>
- <addressOffset>0x150</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ3</name>
- <displayName>OTG_FS_DIEPTSIZ3</displayName>
- <description>device endpoint-3 transfer size register</description>
- <addressOffset>0x170</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS0</name>
- <displayName>OTG_FS_DTXFSTS0</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x118</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS1</name>
- <displayName>OTG_FS_DTXFSTS1</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x138</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS2</name>
- <displayName>OTG_FS_DTXFSTS2</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x158</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS3</name>
- <displayName>OTG_FS_DTXFSTS3</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x178</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ1</name>
- <displayName>OTG_FS_DOEPTSIZ1</displayName>
- <description>device OUT endpoint-1 transfer size register</description>
- <addressOffset>0x330</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ2</name>
- <displayName>OTG_FS_DOEPTSIZ2</displayName>
- <description>device OUT endpoint-2 transfer size register</description>
- <addressOffset>0x350</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ3</name>
- <displayName>OTG_FS_DOEPTSIZ3</displayName>
- <description>device OUT endpoint-3 transfer size register</description>
- <addressOffset>0x370</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL4</name>
- <displayName>OTG_FS_DIEPCTL4</displayName>
- <description>OTG device endpoint-4 control register</description>
- <addressOffset>0x180</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TXFNUM</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT4</name>
- <displayName>OTG_FS_DIEPINT4</displayName>
- <description>device endpoint-4 interrupt register</description>
- <addressOffset>0x188</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ4</name>
- <displayName>OTG_FS_DIEPTSIZ4</displayName>
- <description>device endpoint-4 transfer size register</description>
- <addressOffset>0x194</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS4</name>
- <displayName>OTG_FS_DTXFSTS4</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x19C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPCTL5</name>
- <displayName>OTG_FS_DIEPCTL5</displayName>
- <description>OTG device endpoint-5 control register</description>
- <addressOffset>0x1A0</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TXFNUM</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPINT5</name>
- <displayName>OTG_FS_DIEPINT5</displayName>
- <description>device endpoint-5 interrupt register</description>
- <addressOffset>0x1A8</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TXFE</name>
- <description>TXFE</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>INEPNE</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>ITTXFE</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>TOC</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DIEPTSIZ55</name>
- <displayName>OTG_FS_DIEPTSIZ55</displayName>
- <description>device endpoint-5 transfer size register</description>
- <addressOffset>0x1B0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DTXFSTS55</name>
- <displayName>OTG_FS_DTXFSTS55</displayName>
- <description>OTG_FS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x1B8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL4</name>
- <displayName>OTG_FS_DOEPCTL4</displayName>
- <description>device endpoint-4 control register</description>
- <addressOffset>0x378</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT4</name>
- <displayName>OTG_FS_DOEPINT4</displayName>
- <description>device endpoint-4 interrupt register</description>
- <addressOffset>0x380</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ4</name>
- <displayName>OTG_FS_DOEPTSIZ4</displayName>
- <description>device OUT endpoint-4 transfer size register</description>
- <addressOffset>0x388</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPCTL5</name>
- <displayName>OTG_FS_DOEPCTL5</displayName>
- <description>device endpoint-5 control register</description>
- <addressOffset>0x390</addressOffset>
- <size>0x20</size>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>EPENA</name>
- <description>EPENA</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>EPDIS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>SODDFRM</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>SD0PID/SEVNFRM</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>SNAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>CNAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>Stall</name>
- <description>Stall</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>SNPM</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>EPTYP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAKSTS</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>EONUM/DPID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USBAEP</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>MPSIZ</name>
- <description>MPSIZ</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPINT5</name>
- <displayName>OTG_FS_DOEPINT5</displayName>
- <description>device endpoint-5 interrupt register</description>
- <addressOffset>0x398</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>B2BSTUP</name>
- <description>B2BSTUP</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OTEPDIS</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>STUP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>EPDISD</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>XFRC</name>
- <description>XFRC</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_FS_DOEPTSIZ5</name>
- <displayName>OTG_FS_DOEPTSIZ5</displayName>
- <description>device OUT endpoint-5 transfer size register</description>
- <addressOffset>0x3A0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_FS_PWRCLK</name>
- <description>USB on the go full speed</description>
- <groupName>USB_OTG_FS</groupName>
- <baseAddress>0x50000E00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>OTG_FS_WKUP</name>
- <description>USB On-The-Go FS Wakeup through EXTI line
- interrupt</description>
- <value>42</value>
- </interrupt>
- <interrupt>
- <name>OTG_FS</name>
- <description>USB On The Go FS global
- interrupt</description>
- <value>67</value>
- </interrupt>
- <registers>
- <register>
- <name>OTG_FS_PCGCCTL</name>
- <displayName>OTG_FS_PCGCCTL</displayName>
- <description>OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>STPPCLK</name>
- <description>Stop PHY clock</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GATEHCLK</name>
- <description>Gate HCLK</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PHYSUSP</name>
- <description>PHY Suspended</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_HS_GLOBAL</name>
- <description>USB on the go high speed</description>
- <groupName>USB_OTG_HS</groupName>
- <baseAddress>0x40040000</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_HS_GOTGCTL</name>
- <displayName>OTG_HS_GOTGCTL</displayName>
- <description>OTG_HS control and status register</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <resetValue>0x00000800</resetValue>
- <fields>
- <field>
- <name>SRQSCS</name>
- <description>Session request success</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SRQ</name>
- <description>Session request</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HNGSCS</name>
- <description>Host negotiation success</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HNPRQ</name>
- <description>HNP request</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSHNPEN</name>
- <description>Host set HNP enable</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DHNPEN</name>
- <description>Device HNP enabled</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CIDSTS</name>
- <description>Connector ID status</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DBCT</name>
- <description>Long/short debounce time</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ASVLD</name>
- <description>A-session valid</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BSVLD</name>
- <description>B-session valid</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EHEN</name>
- <description>Embedded host enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GOTGINT</name>
- <displayName>OTG_HS_GOTGINT</displayName>
- <description>OTG_HS interrupt register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>SEDET</name>
- <description>Session end detected</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SRSSCHG</name>
- <description>Session request success status change</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HNSSCHG</name>
- <description>Host negotiation success status change</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HNGDET</name>
- <description>Host negotiation detected</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADTOCHG</name>
- <description>A-device timeout change</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DBCDNE</name>
- <description>Debounce done</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDCHNG</name>
- <description>ID input pin changed</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GAHBCFG</name>
- <displayName>OTG_HS_GAHBCFG</displayName>
- <description>OTG_HS AHB configuration register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>GINT</name>
- <description>Global interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HBSTLEN</name>
- <description>Burst length/type</description>
- <bitOffset>1</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DMAEN</name>
- <description>DMA enable</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFELVL</name>
- <description>TxFIFO empty level</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PTXFELVL</name>
- <description>Periodic TxFIFO empty level</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GUSBCFG</name>
- <displayName>OTG_HS_GUSBCFG</displayName>
- <description>OTG_HS USB configuration register</description>
- <addressOffset>0xC</addressOffset>
- <size>32</size>
- <resetValue>0x00000A00</resetValue>
- <fields>
- <field>
- <name>TOCAL</name>
- <description>FS timeout calibration</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PHYSEL</name>
- <description>USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SRPCAP</name>
- <description>SRP-capable</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HNPCAP</name>
- <description>HNP-capable</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TRDT</name>
- <description>USB turnaround time</description>
- <bitOffset>10</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PHYLPCS</name>
- <description>PHY Low-power clock select</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPIFSLS</name>
- <description>ULPI FS/LS select</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPIAR</name>
- <description>ULPI Auto-resume</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPICSM</name>
- <description>ULPI Clock SuspendM</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPIEVBUSD</name>
- <description>ULPI External VBUS Drive</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPIEVBUSI</name>
- <description>ULPI external VBUS indicator</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TSDPS</name>
- <description>TermSel DLine pulsing selection</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PCCI</name>
- <description>Indicator complement</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTCI</name>
- <description>Indicator pass through</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ULPIIPD</name>
- <description>ULPI interface protect disable</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FHMOD</name>
- <description>Forced host mode</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FDMOD</name>
- <description>Forced peripheral mode</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRSTCTL</name>
- <displayName>OTG_HS_GRSTCTL</displayName>
- <description>OTG_HS reset register</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <resetValue>0x20000000</resetValue>
- <fields>
- <field>
- <name>CSRST</name>
- <description>Core soft reset</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HSRST</name>
- <description>HCLK soft reset</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FCRST</name>
- <description>Host frame counter reset</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFFLSH</name>
- <description>RxFIFO flush</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFFLSH</name>
- <description>TxFIFO flush</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>6</bitOffset>
- <bitWidth>5</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>AHBIDL</name>
- <description>AHB master idle</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>DMAREQ</name>
- <description>DMA request signal enabled for USB OTG HS</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GINTSTS</name>
- <displayName>OTG_HS_GINTSTS</displayName>
- <description>OTG_HS core interrupt register</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <resetValue>0x04000020</resetValue>
- <fields>
- <field>
- <name>CMOD</name>
- <description>Current mode of operation</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>MMIS</name>
- <description>Mode mismatch interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OTGINT</name>
- <description>OTG interrupt</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SOF</name>
- <description>Start of frame</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFLVL</name>
- <description>RxFIFO nonempty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NPTXFE</name>
- <description>Nonperiodic TxFIFO empty</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>GINAKEFF</name>
- <description>Global IN nonperiodic NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>BOUTNAKEFF</name>
- <description>Global OUT NAK effective</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ESUSP</name>
- <description>Early suspend</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBSUSP</name>
- <description>USB suspend</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBRST</name>
- <description>USB reset</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ENUMDNE</name>
- <description>Enumeration done</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ISOODRP</name>
- <description>Isochronous OUT packet dropped interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EOPF</name>
- <description>End of periodic frame interrupt</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IEPINT</name>
- <description>IN endpoint interrupt</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoint interrupt</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>IISOIXFR</name>
- <description>Incomplete isochronous IN transfer</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PXFR_INCOMPISOOUT</name>
- <description>Incomplete periodic transfer</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DATAFSUSP</name>
- <description>Data fetch suspended</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>HPRTINT</name>
- <description>Host port interrupt</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HCINT</name>
- <description>Host channels interrupt</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PTXFE</name>
- <description>Periodic TxFIFO empty</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>CIDSCHG</name>
- <description>Connector ID status change</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DISCINT</name>
- <description>Disconnect detected interrupt</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SRQINT</name>
- <description>Session request/new session detected interrupt</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WKUINT</name>
- <description>Resume/remote wakeup detected interrupt</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GINTMSK</name>
- <displayName>OTG_HS_GINTMSK</displayName>
- <description>OTG_HS interrupt mask register</description>
- <addressOffset>0x18</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MMISM</name>
- <description>Mode mismatch interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OTGINT</name>
- <description>OTG interrupt mask</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SOFM</name>
- <description>Start of frame mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RXFLVLM</name>
- <description>Receive FIFO nonempty mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NPTXFEM</name>
- <description>Nonperiodic TxFIFO empty mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GINAKEFFM</name>
- <description>Global nonperiodic IN NAK effective mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GONAKEFFM</name>
- <description>Global OUT NAK effective mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ESUSPM</name>
- <description>Early suspend mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBSUSPM</name>
- <description>USB suspend mask</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBRST</name>
- <description>USB reset mask</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ENUMDNEM</name>
- <description>Enumeration done mask</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ISOODRPM</name>
- <description>Isochronous OUT packet dropped interrupt mask</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EOPFM</name>
- <description>End of periodic frame interrupt mask</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IEPINT</name>
- <description>IN endpoints interrupt mask</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoints interrupt mask</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>IISOIXFRM</name>
- <description>Incomplete isochronous IN transfer mask</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PXFRM_IISOOXFRM</name>
- <description>Incomplete periodic transfer mask</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FSUSPM</name>
- <description>Data fetch suspended mask</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRTIM</name>
- <description>Host port interrupt mask</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>HCIM</name>
- <description>Host channels interrupt mask</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTXFEM</name>
- <description>Periodic TxFIFO empty mask</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CIDSCHGM</name>
- <description>Connector ID status change mask</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>DISCINT</name>
- <description>Disconnect detected interrupt mask</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SRQIM</name>
- <description>Session request/new session detected interrupt mask</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>WUIM</name>
- <description>Resume/remote wakeup detected interrupt mask</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>RSTDE</name>
- <description>Reset detected interrupt mask</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMINTM</name>
- <description>LPM interrupt mask</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRXSTSR_Host</name>
- <displayName>OTG_HS_GRXSTSR_Host</displayName>
- <description>OTG_HS Receive status debug read register (host mode)</description>
- <addressOffset>0x1C</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>CHNUM</name>
- <description>Channel number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRXSTSP_Host</name>
- <displayName>OTG_HS_GRXSTSP_Host</displayName>
- <description>OTG_HS status read and pop register (host mode)</description>
- <addressOffset>0x20</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>CHNUM</name>
- <description>Channel number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRXFSIZ</name>
- <displayName>OTG_HS_GRXFSIZ</displayName>
- <description>OTG_HS Receive FIFO size register</description>
- <addressOffset>0x24</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>RXFD</name>
- <description>RxFIFO depth</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HNPTXFSIZ_Host</name>
- <displayName>OTG_HS_HNPTXFSIZ_Host</displayName>
- <description>OTG_HS nonperiodic transmit FIFO size register (host mode)</description>
- <addressOffset>0x28</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>NPTXFSA</name>
- <description>Nonperiodic transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NPTXFD</name>
- <description>Nonperiodic TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF0_Device</name>
- <displayName>OTG_HS_DIEPTXF0_Device</displayName>
- <description>Endpoint 0 transmit FIFO size (peripheral mode)</description>
- <alternateRegister>OTG_HS_HNPTXFSIZ_Host</alternateRegister>
- <addressOffset>0x28</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x00000200</resetValue>
- <fields>
- <field>
- <name>TX0FSA</name>
- <description>Endpoint 0 transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>TX0FD</name>
- <description>Endpoint 0 TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GNPTXSTS</name>
- <displayName>OTG_HS_GNPTXSTS</displayName>
- <description>OTG_HS nonperiodic transmit FIFO/queue status register</description>
- <addressOffset>0x2C</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x00080200</resetValue>
- <fields>
- <field>
- <name>NPTXFSAV</name>
- <description>Nonperiodic TxFIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>NPTQXSAV</name>
- <description>Nonperiodic transmit request queue space available</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>NPTXQTOP</name>
- <description>Top of the nonperiodic transmit request queue</description>
- <bitOffset>24</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GCCFG</name>
- <displayName>OTG_HS_GCCFG</displayName>
- <description>OTG_HS general core configuration register</description>
- <addressOffset>0x38</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PWRDWN</name>
- <description>Power down</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BCDEN</name>
- <description>Battery charging detector (BCD) enable</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCDEN</name>
- <description>Data contact detection (DCD) mode enable</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PDEN</name>
- <description>Primary detection (PD) mode enable</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDEN</name>
- <description>Secondary detection (SD) mode enable</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VBDEN</name>
- <description>USB VBUS detection enable</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DCDET</name>
- <description>Data contact detection (DCD) status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PDET</name>
- <description>Primary detection (PD) status</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SDET</name>
- <description>Secondary detection (SD) status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PS2DET</name>
- <description>DM pull-up detection status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_CID</name>
- <displayName>OTG_HS_CID</displayName>
- <description>OTG_HS core ID register</description>
- <addressOffset>0x3C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x00001200</resetValue>
- <fields>
- <field>
- <name>PRODUCT_ID</name>
- <description>Product ID field</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HPTXFSIZ</name>
- <displayName>OTG_HS_HPTXFSIZ</displayName>
- <description>OTG_HS Host periodic transmit FIFO size register</description>
- <addressOffset>0x100</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000600</resetValue>
- <fields>
- <field>
- <name>PTXSA</name>
- <description>Host periodic TxFIFO start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>PTXFD</name>
- <description>Host periodic TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF1</name>
- <displayName>OTG_HS_DIEPTXF1</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x104</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF2</name>
- <displayName>OTG_HS_DIEPTXF2</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x108</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF3</name>
- <displayName>OTG_HS_DIEPTXF3</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x11C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF4</name>
- <displayName>OTG_HS_DIEPTXF4</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x120</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF5</name>
- <displayName>OTG_HS_DIEPTXF5</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x124</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF6</name>
- <displayName>OTG_HS_DIEPTXF6</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x128</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTXF7</name>
- <displayName>OTG_HS_DIEPTXF7</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO size register</description>
- <addressOffset>0x12C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02000400</resetValue>
- <fields>
- <field>
- <name>INEPTXSA</name>
- <description>IN endpoint FIFOx transmit RAM start address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>INEPTXFD</name>
- <description>IN endpoint TxFIFO depth</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRXSTSR_Device</name>
- <displayName>OTG_HS_GRXSTSR_Device</displayName>
- <description>OTG_HS Receive status debug read register (peripheral mode mode)</description>
- <alternateRegister>OTG_HS_GRXSTSR_Host</alternateRegister>
- <addressOffset>0x1C</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRMNUM</name>
- <description>Frame number</description>
- <bitOffset>21</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GRXSTSP_Device</name>
- <displayName>OTG_HS_GRXSTSP_Device</displayName>
- <description>OTG_HS status read and pop register (peripheral mode)</description>
- <alternateRegister>OTG_HS_GRXSTSP_Host</alternateRegister>
- <addressOffset>0x20</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>BCNT</name>
- <description>Byte count</description>
- <bitOffset>4</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>15</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PKTSTS</name>
- <description>Packet status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>FRMNUM</name>
- <description>Frame number</description>
- <bitOffset>21</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_GLPMCFG</name>
- <displayName>OTG_HS_GLPMCFG</displayName>
- <description>OTG core LPM configuration register</description>
- <addressOffset>0x54</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>LPMEN</name>
- <description>LPM support enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMACK</name>
- <description>LPM token acknowledge enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BESL</name>
- <description>Best effort service latency</description>
- <bitOffset>2</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>REMWAKE</name>
- <description>bRemoteWake value</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>L1SSEN</name>
- <description>L1 Shallow Sleep enable</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BESLTHRS</name>
- <description>BESL threshold</description>
- <bitOffset>8</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>L1DSEN</name>
- <description>L1 deep sleep enable</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRST</name>
- <description>LPM response</description>
- <bitOffset>13</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SLPSTS</name>
- <description>Port sleep status</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>L1RSMOK</name>
- <description>Sleep State Resume OK</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>LPMCHIDX</name>
- <description>LPM Channel Index</description>
- <bitOffset>17</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRCNT</name>
- <description>LPM retry count</description>
- <bitOffset>21</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNDLPM</name>
- <description>Send LPM transaction</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>LPMRCNTSTS</name>
- <description>LPM retry count status</description>
- <bitOffset>25</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>ENBESL</name>
- <description>Enable best effort service latency</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_HS_HOST</name>
- <description>USB on the go high speed</description>
- <groupName>USB_OTG_HS</groupName>
- <baseAddress>0x40040400</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_HS_HCFG</name>
- <displayName>OTG_HS_HCFG</displayName>
- <description>OTG_HS host configuration register</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>FSLSPCS</name>
- <description>FS/LS PHY clock select</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>FSLSS</name>
- <description>FS- and LS-only support</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HFIR</name>
- <displayName>OTG_HS_HFIR</displayName>
- <description>OTG_HS Host frame interval register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0000EA60</resetValue>
- <fields>
- <field>
- <name>FRIVL</name>
- <description>Frame interval</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HFNUM</name>
- <displayName>OTG_HS_HFNUM</displayName>
- <description>OTG_HS host frame number/frame time remaining register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x00003FFF</resetValue>
- <fields>
- <field>
- <name>FRNUM</name>
- <description>Frame number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>FTREM</name>
- <description>Frame time remaining</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HPTXSTS</name>
- <displayName>OTG_HS_HPTXSTS</displayName>
- <description>OTG_HS_Host periodic transmit FIFO/queue status register</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <resetValue>0x00080100</resetValue>
- <fields>
- <field>
- <name>PTXFSAVL</name>
- <description>Periodic transmit data FIFO space available</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTXQSAV</name>
- <description>Periodic transmit request queue space available</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PTXQTOP</name>
- <description>Top of the periodic transmit request queue</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HAINT</name>
- <displayName>OTG_HS_HAINT</displayName>
- <description>OTG_HS Host all channels interrupt register</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>HAINT</name>
- <description>Channel interrupts</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HAINTMSK</name>
- <displayName>OTG_HS_HAINTMSK</displayName>
- <description>OTG_HS host all channels interrupt mask register</description>
- <addressOffset>0x18</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>HAINTM</name>
- <description>Channel interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HPRT</name>
- <displayName>OTG_HS_HPRT</displayName>
- <description>OTG_HS host port control and status register</description>
- <addressOffset>0x40</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PCSTS</name>
- <description>Port connect status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PCDET</name>
- <description>Port connect detected</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PENA</name>
- <description>Port enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PENCHNG</name>
- <description>Port enable/disable change</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>POCA</name>
- <description>Port overcurrent active</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>POCCHNG</name>
- <description>Port overcurrent change</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRES</name>
- <description>Port resume</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PSUSP</name>
- <description>Port suspend</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PRST</name>
- <description>Port reset</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PLSTS</name>
- <description>Port line status</description>
- <bitOffset>10</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>PPWR</name>
- <description>Port power</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PTCTL</name>
- <description>Port test control</description>
- <bitOffset>13</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PSPD</name>
- <description>Port speed</description>
- <bitOffset>17</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR0</name>
- <displayName>OTG_HS_HCCHAR0</displayName>
- <description>OTG_HS host channel-0 characteristics register</description>
- <addressOffset>0x100</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR1</name>
- <displayName>OTG_HS_HCCHAR1</displayName>
- <description>OTG_HS host channel-1 characteristics register</description>
- <addressOffset>0x120</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR2</name>
- <displayName>OTG_HS_HCCHAR2</displayName>
- <description>OTG_HS host channel-2 characteristics register</description>
- <addressOffset>0x140</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR3</name>
- <displayName>OTG_HS_HCCHAR3</displayName>
- <description>OTG_HS host channel-3 characteristics register</description>
- <addressOffset>0x160</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR4</name>
- <displayName>OTG_HS_HCCHAR4</displayName>
- <description>OTG_HS host channel-4 characteristics register</description>
- <addressOffset>0x180</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR5</name>
- <displayName>OTG_HS_HCCHAR5</displayName>
- <description>OTG_HS host channel-5 characteristics register</description>
- <addressOffset>0x1A0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR6</name>
- <displayName>OTG_HS_HCCHAR6</displayName>
- <description>OTG_HS host channel-6 characteristics register</description>
- <addressOffset>0x1C0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR7</name>
- <displayName>OTG_HS_HCCHAR7</displayName>
- <description>OTG_HS host channel-7 characteristics register</description>
- <addressOffset>0x1E0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR8</name>
- <displayName>OTG_HS_HCCHAR8</displayName>
- <description>OTG_HS host channel-8 characteristics register</description>
- <addressOffset>0x200</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR9</name>
- <displayName>OTG_HS_HCCHAR9</displayName>
- <description>OTG_HS host channel-9 characteristics register</description>
- <addressOffset>0x220</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR10</name>
- <displayName>OTG_HS_HCCHAR10</displayName>
- <description>OTG_HS host channel-10 characteristics register</description>
- <addressOffset>0x240</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR11</name>
- <displayName>OTG_HS_HCCHAR11</displayName>
- <description>OTG_HS host channel-11 characteristics register</description>
- <addressOffset>0x260</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT0</name>
- <displayName>OTG_HS_HCSPLT0</displayName>
- <description>OTG_HS host channel-0 split control register</description>
- <addressOffset>0x104</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT1</name>
- <displayName>OTG_HS_HCSPLT1</displayName>
- <description>OTG_HS host channel-1 split control register</description>
- <addressOffset>0x124</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT2</name>
- <displayName>OTG_HS_HCSPLT2</displayName>
- <description>OTG_HS host channel-2 split control register</description>
- <addressOffset>0x144</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT3</name>
- <displayName>OTG_HS_HCSPLT3</displayName>
- <description>OTG_HS host channel-3 split control register</description>
- <addressOffset>0x164</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT4</name>
- <displayName>OTG_HS_HCSPLT4</displayName>
- <description>OTG_HS host channel-4 split control register</description>
- <addressOffset>0x184</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT5</name>
- <displayName>OTG_HS_HCSPLT5</displayName>
- <description>OTG_HS host channel-5 split control register</description>
- <addressOffset>0x1A4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT6</name>
- <displayName>OTG_HS_HCSPLT6</displayName>
- <description>OTG_HS host channel-6 split control register</description>
- <addressOffset>0x1C4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT7</name>
- <displayName>OTG_HS_HCSPLT7</displayName>
- <description>OTG_HS host channel-7 split control register</description>
- <addressOffset>0x1E4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT8</name>
- <displayName>OTG_HS_HCSPLT8</displayName>
- <description>OTG_HS host channel-8 split control register</description>
- <addressOffset>0x204</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT9</name>
- <displayName>OTG_HS_HCSPLT9</displayName>
- <description>OTG_HS host channel-9 split control register</description>
- <addressOffset>0x224</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT10</name>
- <displayName>OTG_HS_HCSPLT10</displayName>
- <description>OTG_HS host channel-10 split control register</description>
- <addressOffset>0x244</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT11</name>
- <displayName>OTG_HS_HCSPLT11</displayName>
- <description>OTG_HS host channel-11 split control register</description>
- <addressOffset>0x264</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT0</name>
- <displayName>OTG_HS_HCINT0</displayName>
- <description>OTG_HS host channel-11 interrupt register</description>
- <addressOffset>0x108</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT1</name>
- <displayName>OTG_HS_HCINT1</displayName>
- <description>OTG_HS host channel-1 interrupt register</description>
- <addressOffset>0x128</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT2</name>
- <displayName>OTG_HS_HCINT2</displayName>
- <description>OTG_HS host channel-2 interrupt register</description>
- <addressOffset>0x148</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT3</name>
- <displayName>OTG_HS_HCINT3</displayName>
- <description>OTG_HS host channel-3 interrupt register</description>
- <addressOffset>0x168</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT4</name>
- <displayName>OTG_HS_HCINT4</displayName>
- <description>OTG_HS host channel-4 interrupt register</description>
- <addressOffset>0x188</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT5</name>
- <displayName>OTG_HS_HCINT5</displayName>
- <description>OTG_HS host channel-5 interrupt register</description>
- <addressOffset>0x1A8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT6</name>
- <displayName>OTG_HS_HCINT6</displayName>
- <description>OTG_HS host channel-6 interrupt register</description>
- <addressOffset>0x1C8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT7</name>
- <displayName>OTG_HS_HCINT7</displayName>
- <description>OTG_HS host channel-7 interrupt register</description>
- <addressOffset>0x1E8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT8</name>
- <displayName>OTG_HS_HCINT8</displayName>
- <description>OTG_HS host channel-8 interrupt register</description>
- <addressOffset>0x208</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT9</name>
- <displayName>OTG_HS_HCINT9</displayName>
- <description>OTG_HS host channel-9 interrupt register</description>
- <addressOffset>0x228</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT10</name>
- <displayName>OTG_HS_HCINT10</displayName>
- <description>OTG_HS host channel-10 interrupt register</description>
- <addressOffset>0x248</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT11</name>
- <displayName>OTG_HS_HCINT11</displayName>
- <description>OTG_HS host channel-11 interrupt register</description>
- <addressOffset>0x268</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK0</name>
- <displayName>OTG_HS_HCINTMSK0</displayName>
- <description>OTG_HS host channel-11 interrupt mask register</description>
- <addressOffset>0x10C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK1</name>
- <displayName>OTG_HS_HCINTMSK1</displayName>
- <description>OTG_HS host channel-1 interrupt mask register</description>
- <addressOffset>0x12C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK2</name>
- <displayName>OTG_HS_HCINTMSK2</displayName>
- <description>OTG_HS host channel-2 interrupt mask register</description>
- <addressOffset>0x14C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK3</name>
- <displayName>OTG_HS_HCINTMSK3</displayName>
- <description>OTG_HS host channel-3 interrupt mask register</description>
- <addressOffset>0x16C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK4</name>
- <displayName>OTG_HS_HCINTMSK4</displayName>
- <description>OTG_HS host channel-4 interrupt mask register</description>
- <addressOffset>0x18C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK5</name>
- <displayName>OTG_HS_HCINTMSK5</displayName>
- <description>OTG_HS host channel-5 interrupt mask register</description>
- <addressOffset>0x1AC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK6</name>
- <displayName>OTG_HS_HCINTMSK6</displayName>
- <description>OTG_HS host channel-6 interrupt mask register</description>
- <addressOffset>0x1CC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK7</name>
- <displayName>OTG_HS_HCINTMSK7</displayName>
- <description>OTG_HS host channel-7 interrupt mask register</description>
- <addressOffset>0x1EC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK8</name>
- <displayName>OTG_HS_HCINTMSK8</displayName>
- <description>OTG_HS host channel-8 interrupt mask register</description>
- <addressOffset>0x20C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK9</name>
- <displayName>OTG_HS_HCINTMSK9</displayName>
- <description>OTG_HS host channel-9 interrupt mask register</description>
- <addressOffset>0x22C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK10</name>
- <displayName>OTG_HS_HCINTMSK10</displayName>
- <description>OTG_HS host channel-10 interrupt mask register</description>
- <addressOffset>0x24C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK11</name>
- <displayName>OTG_HS_HCINTMSK11</displayName>
- <description>OTG_HS host channel-11 interrupt mask register</description>
- <addressOffset>0x26C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>response received interrupt mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error mask</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ0</name>
- <displayName>OTG_HS_HCTSIZ0</displayName>
- <description>OTG_HS host channel-11 transfer size register</description>
- <addressOffset>0x110</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ1</name>
- <displayName>OTG_HS_HCTSIZ1</displayName>
- <description>OTG_HS host channel-1 transfer size register</description>
- <addressOffset>0x130</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ2</name>
- <displayName>OTG_HS_HCTSIZ2</displayName>
- <description>OTG_HS host channel-2 transfer size register</description>
- <addressOffset>0x150</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ3</name>
- <displayName>OTG_HS_HCTSIZ3</displayName>
- <description>OTG_HS host channel-3 transfer size register</description>
- <addressOffset>0x170</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ4</name>
- <displayName>OTG_HS_HCTSIZ4</displayName>
- <description>OTG_HS host channel-4 transfer size register</description>
- <addressOffset>0x190</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ5</name>
- <displayName>OTG_HS_HCTSIZ5</displayName>
- <description>OTG_HS host channel-5 transfer size register</description>
- <addressOffset>0x1B0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ6</name>
- <displayName>OTG_HS_HCTSIZ6</displayName>
- <description>OTG_HS host channel-6 transfer size register</description>
- <addressOffset>0x1D0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ7</name>
- <displayName>OTG_HS_HCTSIZ7</displayName>
- <description>OTG_HS host channel-7 transfer size register</description>
- <addressOffset>0x1F0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ8</name>
- <displayName>OTG_HS_HCTSIZ8</displayName>
- <description>OTG_HS host channel-8 transfer size register</description>
- <addressOffset>0x210</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ9</name>
- <displayName>OTG_HS_HCTSIZ9</displayName>
- <description>OTG_HS host channel-9 transfer size register</description>
- <addressOffset>0x230</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ10</name>
- <displayName>OTG_HS_HCTSIZ10</displayName>
- <description>OTG_HS host channel-10 transfer size register</description>
- <addressOffset>0x250</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ11</name>
- <displayName>OTG_HS_HCTSIZ11</displayName>
- <description>OTG_HS host channel-11 transfer size register</description>
- <addressOffset>0x270</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA0</name>
- <displayName>OTG_HS_HCDMA0</displayName>
- <description>OTG_HS host channel-0 DMA address register</description>
- <addressOffset>0x114</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA1</name>
- <displayName>OTG_HS_HCDMA1</displayName>
- <description>OTG_HS host channel-1 DMA address register</description>
- <addressOffset>0x134</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA2</name>
- <displayName>OTG_HS_HCDMA2</displayName>
- <description>OTG_HS host channel-2 DMA address register</description>
- <addressOffset>0x154</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA3</name>
- <displayName>OTG_HS_HCDMA3</displayName>
- <description>OTG_HS host channel-3 DMA address register</description>
- <addressOffset>0x174</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA4</name>
- <displayName>OTG_HS_HCDMA4</displayName>
- <description>OTG_HS host channel-4 DMA address register</description>
- <addressOffset>0x194</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA5</name>
- <displayName>OTG_HS_HCDMA5</displayName>
- <description>OTG_HS host channel-5 DMA address register</description>
- <addressOffset>0x1B4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA6</name>
- <displayName>OTG_HS_HCDMA6</displayName>
- <description>OTG_HS host channel-6 DMA address register</description>
- <addressOffset>0x1D4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA7</name>
- <displayName>OTG_HS_HCDMA7</displayName>
- <description>OTG_HS host channel-7 DMA address register</description>
- <addressOffset>0x1F4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA8</name>
- <displayName>OTG_HS_HCDMA8</displayName>
- <description>OTG_HS host channel-8 DMA address register</description>
- <addressOffset>0x214</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA9</name>
- <displayName>OTG_HS_HCDMA9</displayName>
- <description>OTG_HS host channel-9 DMA address register</description>
- <addressOffset>0x234</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA10</name>
- <displayName>OTG_HS_HCDMA10</displayName>
- <description>OTG_HS host channel-10 DMA address register</description>
- <addressOffset>0x254</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA11</name>
- <displayName>OTG_HS_HCDMA11</displayName>
- <description>OTG_HS host channel-11 DMA address register</description>
- <addressOffset>0x274</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR12</name>
- <displayName>OTG_HS_HCCHAR12</displayName>
- <description>OTG_HS host channel-12 characteristics register</description>
- <addressOffset>0x278</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT12</name>
- <displayName>OTG_HS_HCSPLT12</displayName>
- <description>OTG_HS host channel-12 split control register</description>
- <addressOffset>0x27C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT12</name>
- <displayName>OTG_HS_HCINT12</displayName>
- <description>OTG_HS host channel-12 interrupt register</description>
- <addressOffset>0x280</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK12</name>
- <displayName>OTG_HS_HCINTMSK12</displayName>
- <description>OTG_HS host channel-12 interrupt mask register</description>
- <addressOffset>0x284</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ12</name>
- <displayName>OTG_HS_HCTSIZ12</displayName>
- <description>OTG_HS host channel-12 transfer size register</description>
- <addressOffset>0x288</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA12</name>
- <displayName>OTG_HS_HCDMA12</displayName>
- <description>OTG_HS host channel-12 DMA address register</description>
- <addressOffset>0x28C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR13</name>
- <displayName>OTG_HS_HCCHAR13</displayName>
- <description>OTG_HS host channel-13 characteristics register</description>
- <addressOffset>0x290</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT13</name>
- <displayName>OTG_HS_HCSPLT13</displayName>
- <description>OTG_HS host channel-13 split control register</description>
- <addressOffset>0x294</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT13</name>
- <displayName>OTG_HS_HCINT13</displayName>
- <description>OTG_HS host channel-13 interrupt register</description>
- <addressOffset>0x298</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK13</name>
- <displayName>OTG_HS_HCINTMSK13</displayName>
- <description>OTG_HS host channel-13 interrupt mask register</description>
- <addressOffset>0x29C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALLM response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ13</name>
- <displayName>OTG_HS_HCTSIZ13</displayName>
- <description>OTG_HS host channel-13 transfer size register</description>
- <addressOffset>0x2A0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA13</name>
- <displayName>OTG_HS_HCDMA13</displayName>
- <description>OTG_HS host channel-13 DMA address register</description>
- <addressOffset>0x2A4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR14</name>
- <displayName>OTG_HS_HCCHAR14</displayName>
- <description>OTG_HS host channel-14 characteristics register</description>
- <addressOffset>0x2A8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT14</name>
- <displayName>OTG_HS_HCSPLT14</displayName>
- <description>OTG_HS host channel-14 split control register</description>
- <addressOffset>0x2AC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT14</name>
- <displayName>OTG_HS_HCINT14</displayName>
- <description>OTG_HS host channel-14 interrupt register</description>
- <addressOffset>0x2B0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK14</name>
- <displayName>OTG_HS_HCINTMSK14</displayName>
- <description>OTG_HS host channel-14 interrupt mask register</description>
- <addressOffset>0x2B4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALLM</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAKM response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACKM response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ14</name>
- <displayName>OTG_HS_HCTSIZ14</displayName>
- <description>OTG_HS host channel-14 transfer size register</description>
- <addressOffset>0x2B8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA14</name>
- <displayName>OTG_HS_HCDMA14</displayName>
- <description>OTG_HS host channel-14 DMA address register</description>
- <addressOffset>0x2BC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCCHAR15</name>
- <displayName>OTG_HS_HCCHAR15</displayName>
- <description>OTG_HS host channel-15 characteristics register</description>
- <addressOffset>0x2C0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- </field>
- <field>
- <name>EPNUM</name>
- <description>Endpoint number</description>
- <bitOffset>11</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>EPDIR</name>
- <description>Endpoint direction</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSDEV</name>
- <description>Low-speed device</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>MC</name>
- <description>Multi Count (MC) / Error Count (EC)</description>
- <bitOffset>20</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>22</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ODDFRM</name>
- <description>Odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHDIS</name>
- <description>Channel disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHENA</name>
- <description>Channel enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCSPLT15</name>
- <displayName>OTG_HS_HCSPLT15</displayName>
- <description>OTG_HS host channel-15 split control register</description>
- <addressOffset>0x2C4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>PRTADDR</name>
- <description>Port address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>HUBADDR</name>
- <description>Hub address</description>
- <bitOffset>7</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>XACTPOS</name>
- <description>XACTPOS</description>
- <bitOffset>14</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>COMPLSPLT</name>
- <description>Do complete split</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SPLITEN</name>
- <description>Split enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINT15</name>
- <displayName>OTG_HS_HCINT15</displayName>
- <description>OTG_HS host channel-15 interrupt register</description>
- <addressOffset>0x2C8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHH</name>
- <description>Channel halted</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK response received interrupt</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACK</name>
- <description>ACK response received/transmitted interrupt</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERR</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERR</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMOR</name>
- <description>Frame overrun</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERR</name>
- <description>Data toggle error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCINTMSK15</name>
- <displayName>OTG_HS_HCINTMSK15</displayName>
- <description>OTG_HS host channel-15 interrupt mask register</description>
- <addressOffset>0x2CC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CHHM</name>
- <description>Channel halted mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBERR</name>
- <description>AHB error</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STALL</name>
- <description>STALL response received interrupt mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NAKM</name>
- <description>NAK response received interrupt mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ACKM</name>
- <description>ACK response received/transmitted interrupt mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>Response received interrupt</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXERRM</name>
- <description>Transaction error</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BBERRM</name>
- <description>Babble error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FRMORM</name>
- <description>Frame overrun mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTERRM</name>
- <description>Data toggle error mask</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCTSIZ15</name>
- <displayName>OTG_HS_HCTSIZ15</displayName>
- <description>OTG_HS host channel-15 transfer size register</description>
- <addressOffset>0x2D0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>DPID</name>
- <description>Data PID</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_HCDMA15</name>
- <displayName>OTG_HS_HCDMA15</displayName>
- <description>OTG_HS host channel-15 DMA address register</description>
- <addressOffset>0x2D4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_HS_DEVICE</name>
- <description>USB on the go high speed</description>
- <groupName>USB_OTG_HS</groupName>
- <baseAddress>0x40040800</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x400</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>OTG_HS_DCFG</name>
- <displayName>OTG_HS_DCFG</displayName>
- <description>OTG_HS device configuration register</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x02200000</resetValue>
- <fields>
- <field>
- <name>DSPD</name>
- <description>Device speed</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>NZLSOHSK</name>
- <description>Nonzero-length status OUT handshake</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DAD</name>
- <description>Device address</description>
- <bitOffset>4</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>PFIVL</name>
- <description>Periodic (micro)frame interval</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>PERSCHIVL</name>
- <description>Periodic scheduling interval</description>
- <bitOffset>24</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DCTL</name>
- <displayName>OTG_HS_DCTL</displayName>
- <description>OTG_HS device control register</description>
- <addressOffset>0x4</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>RWUSIG</name>
- <description>Remote wakeup signaling</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SDIS</name>
- <description>Soft disconnect</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>GINSTS</name>
- <description>Global IN NAK status</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>GONSTS</name>
- <description>Global OUT NAK status</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TCTL</name>
- <description>Test control</description>
- <bitOffset>4</bitOffset>
- <bitWidth>3</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SGINAK</name>
- <description>Set global IN NAK</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CGINAK</name>
- <description>Clear global IN NAK</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SGONAK</name>
- <description>Set global OUT NAK</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>CGONAK</name>
- <description>Clear global OUT NAK</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>POPRGDNE</name>
- <description>Power-on programming done</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DSTS</name>
- <displayName>OTG_HS_DSTS</displayName>
- <description>OTG_HS device status register</description>
- <addressOffset>0x8</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x00000010</resetValue>
- <fields>
- <field>
- <name>SUSPSTS</name>
- <description>Suspend status</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ENUMSPD</name>
- <description>Enumerated speed</description>
- <bitOffset>1</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>EERR</name>
- <description>Erratic error</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FNSOF</name>
- <description>Frame number of the received SOF</description>
- <bitOffset>8</bitOffset>
- <bitWidth>14</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPMSK</name>
- <displayName>OTG_HS_DIEPMSK</displayName>
- <description>OTG_HS device IN endpoint common interrupt mask register</description>
- <addressOffset>0x10</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDM</name>
- <description>Endpoint disabled interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TOM</name>
- <description>Timeout condition mask (nonisochronous endpoints)</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ITTXFEMSK</name>
- <description>IN token received when TxFIFO empty mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INEPNMM</name>
- <description>IN token received with EP mismatch mask</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INEPNEM</name>
- <description>IN endpoint NAK effective mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXFURM</name>
- <description>FIFO underrun mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BIM</name>
- <description>BNA interrupt mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPMSK</name>
- <displayName>OTG_HS_DOEPMSK</displayName>
- <description>OTG_HS device OUT endpoint common interrupt mask register</description>
- <addressOffset>0x14</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRCM</name>
- <description>Transfer completed interrupt mask</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDM</name>
- <description>Endpoint disabled interrupt mask</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUPM</name>
- <description>SETUP phase done mask</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDM</name>
- <description>OUT token received when endpoint disabled mask</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received mask</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OPEM</name>
- <description>OUT packet error mask</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BOIM</name>
- <description>BNA interrupt mask</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DAINT</name>
- <displayName>OTG_HS_DAINT</displayName>
- <description>OTG_HS device all endpoints interrupt register</description>
- <addressOffset>0x18</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>IEPINT</name>
- <description>IN endpoint interrupt bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>OEPINT</name>
- <description>OUT endpoint interrupt bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DAINTMSK</name>
- <displayName>OTG_HS_DAINTMSK</displayName>
- <description>OTG_HS all endpoints interrupt mask register</description>
- <addressOffset>0x1C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>IEPM</name>
- <description>IN EP interrupt mask bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>OEPM</name>
- <description>OUT EP interrupt mask bits</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DVBUSDIS</name>
- <displayName>OTG_HS_DVBUSDIS</displayName>
- <description>OTG_HS device VBUS discharge time register</description>
- <addressOffset>0x28</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x000017D7</resetValue>
- <fields>
- <field>
- <name>VBUSDT</name>
- <description>Device VBUS discharge time</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DVBUSPULSE</name>
- <displayName>OTG_HS_DVBUSPULSE</displayName>
- <description>OTG_HS device VBUS pulsing time register</description>
- <addressOffset>0x2C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x000005B8</resetValue>
- <fields>
- <field>
- <name>DVBUSP</name>
- <description>Device VBUS pulsing time</description>
- <bitOffset>0</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTHRCTL</name>
- <displayName>OTG_HS_DTHRCTL</displayName>
- <description>OTG_HS Device threshold control register</description>
- <addressOffset>0x30</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>NONISOTHREN</name>
- <description>Nonisochronous IN endpoints threshold enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ISOTHREN</name>
- <description>ISO IN endpoint threshold enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TXTHRLEN</name>
- <description>Transmit threshold length</description>
- <bitOffset>2</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>RXTHREN</name>
- <description>Receive threshold enable</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RXTHRLEN</name>
- <description>Receive threshold length</description>
- <bitOffset>17</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>ARPEN</name>
- <description>Arbiter parking enable</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPEMPMSK</name>
- <displayName>OTG_HS_DIEPEMPMSK</displayName>
- <description>OTG_HS device IN endpoint FIFO empty interrupt mask register</description>
- <addressOffset>0x34</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTXFEM</name>
- <description>IN EP Tx FIFO empty interrupt mask bits</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DEACHINT</name>
- <displayName>OTG_HS_DEACHINT</displayName>
- <description>OTG_HS device each endpoint interrupt register</description>
- <addressOffset>0x38</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>IEP1INT</name>
- <description>IN endpoint 1interrupt bit</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OEP1INT</name>
- <description>OUT endpoint 1 interrupt bit</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DEACHINTMSK</name>
- <displayName>OTG_HS_DEACHINTMSK</displayName>
- <description>OTG_HS device each endpoint interrupt register mask</description>
- <addressOffset>0x3C</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>IEP1INTM</name>
- <description>IN Endpoint 1 interrupt mask bit</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OEP1INTM</name>
- <description>OUT Endpoint 1 interrupt mask bit</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL0</name>
- <displayName>OTG_HS_DIEPCTL0</displayName>
- <description>OTG device endpoint-0 control register</description>
- <addressOffset>0x100</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL1</name>
- <displayName>OTG_HS_DIEPCTL1</displayName>
- <description>OTG device endpoint-1 control register</description>
- <addressOffset>0x120</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL2</name>
- <displayName>OTG_HS_DIEPCTL2</displayName>
- <description>OTG device endpoint-2 control register</description>
- <addressOffset>0x140</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL3</name>
- <displayName>OTG_HS_DIEPCTL3</displayName>
- <description>OTG device endpoint-3 control register</description>
- <addressOffset>0x160</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL4</name>
- <displayName>OTG_HS_DIEPCTL4</displayName>
- <description>OTG device endpoint-4 control register</description>
- <addressOffset>0x180</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL5</name>
- <displayName>OTG_HS_DIEPCTL5</displayName>
- <description>OTG device endpoint-5 control register</description>
- <addressOffset>0x1A0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL6</name>
- <displayName>OTG_HS_DIEPCTL6</displayName>
- <description>OTG device endpoint-6 control register</description>
- <addressOffset>0x1C0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPCTL7</name>
- <displayName>OTG_HS_DIEPCTL7</displayName>
- <description>OTG device endpoint-7 control register</description>
- <addressOffset>0x1E0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even/odd frame</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFNUM</name>
- <description>TxFIFO number</description>
- <bitOffset>22</bitOffset>
- <bitWidth>4</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT0</name>
- <displayName>OTG_HS_DIEPINT0</displayName>
- <description>OTG device endpoint-0 interrupt register</description>
- <addressOffset>0x108</addressOffset>
- <size>32</size>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT1</name>
- <displayName>OTG_HS_DIEPINT1</displayName>
- <description>OTG device endpoint-1 interrupt register</description>
- <addressOffset>0x128</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT2</name>
- <displayName>OTG_HS_DIEPINT2</displayName>
- <description>OTG device endpoint-2 interrupt register</description>
- <addressOffset>0x148</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT3</name>
- <displayName>OTG_HS_DIEPINT3</displayName>
- <description>OTG device endpoint-3 interrupt register</description>
- <addressOffset>0x168</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT4</name>
- <displayName>OTG_HS_DIEPINT4</displayName>
- <description>OTG device endpoint-4 interrupt register</description>
- <addressOffset>0x188</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT5</name>
- <displayName>OTG_HS_DIEPINT5</displayName>
- <description>OTG device endpoint-5 interrupt register</description>
- <addressOffset>0x1A8</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT6</name>
- <displayName>OTG_HS_DIEPINT6</displayName>
- <description>OTG device endpoint-6 interrupt register</description>
- <addressOffset>0x1C8</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPINT7</name>
- <displayName>OTG_HS_DIEPINT7</displayName>
- <description>OTG device endpoint-7 interrupt register</description>
- <addressOffset>0x1E8</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TOC</name>
- <description>Timeout condition</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>ITTXFE</name>
- <description>IN token received when TxFIFO is empty</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>INEPNE</name>
- <description>IN endpoint NAK effective</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>TXFE</name>
- <description>Transmit FIFO empty</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>TXFIFOUDRN</name>
- <description>Transmit Fifo Underrun</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BNA</name>
- <description>Buffer not available interrupt</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>PKTDRPSTS</name>
- <description>Packet dropped status</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>BERR</name>
- <description>Babble error interrupt</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>NAK</name>
- <description>NAK interrupt</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ0</name>
- <displayName>OTG_HS_DIEPTSIZ0</displayName>
- <description>OTG_HS device IN endpoint 0 transfer size register</description>
- <addressOffset>0x110</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPDMA1</name>
- <displayName>OTG_HS_DIEPDMA1</displayName>
- <description>OTG_HS device endpoint-1 DMA address register</description>
- <addressOffset>0x114</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPDMA2</name>
- <displayName>OTG_HS_DIEPDMA2</displayName>
- <description>OTG_HS device endpoint-2 DMA address register</description>
- <addressOffset>0x134</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPDMA3</name>
- <displayName>OTG_HS_DIEPDMA3</displayName>
- <description>OTG_HS device endpoint-3 DMA address register</description>
- <addressOffset>0x154</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPDMA4</name>
- <displayName>OTG_HS_DIEPDMA4</displayName>
- <description>OTG_HS device endpoint-4 DMA address register</description>
- <addressOffset>0x174</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPDMA5</name>
- <displayName>OTG_HS_DIEPDMA5</displayName>
- <description>OTG_HS device endpoint-5 DMA address register</description>
- <addressOffset>0x194</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>DMAADDR</name>
- <description>DMA address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS0</name>
- <displayName>OTG_HS_DTXFSTS0</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x118</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS1</name>
- <displayName>OTG_HS_DTXFSTS1</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x138</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS2</name>
- <displayName>OTG_HS_DTXFSTS2</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x158</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS3</name>
- <displayName>OTG_HS_DTXFSTS3</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x178</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS4</name>
- <displayName>OTG_HS_DTXFSTS4</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x198</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS5</name>
- <displayName>OTG_HS_DTXFSTS5</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x1B8</addressOffset>
- <size>32</size>
- <access>read-only</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ1</name>
- <displayName>OTG_HS_DIEPTSIZ1</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <addressOffset>0x130</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ2</name>
- <displayName>OTG_HS_DIEPTSIZ2</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <addressOffset>0x150</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ3</name>
- <displayName>OTG_HS_DIEPTSIZ3</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <addressOffset>0x170</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ4</name>
- <displayName>OTG_HS_DIEPTSIZ4</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <addressOffset>0x190</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ5</name>
- <displayName>OTG_HS_DIEPTSIZ5</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <addressOffset>0x1B0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL0</name>
- <displayName>OTG_HS_DOEPCTL0</displayName>
- <description>OTG_HS device control OUT endpoint 0 control register</description>
- <addressOffset>0x300</addressOffset>
- <size>32</size>
- <resetValue>0x00008000</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL1</name>
- <displayName>OTG_HS_DOEPCTL1</displayName>
- <description>OTG device endpoint-1 control register</description>
- <addressOffset>0x320</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL2</name>
- <displayName>OTG_HS_DOEPCTL2</displayName>
- <description>OTG device endpoint-2 control register</description>
- <addressOffset>0x340</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL3</name>
- <displayName>OTG_HS_DOEPCTL3</displayName>
- <description>OTG device endpoint-3 control register</description>
- <addressOffset>0x360</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT0</name>
- <displayName>OTG_HS_DOEPINT0</displayName>
- <description>OTG_HS device endpoint-0 interrupt register</description>
- <addressOffset>0x308</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x00000080</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT1</name>
- <displayName>OTG_HS_DOEPINT1</displayName>
- <description>OTG_HS device endpoint-1 interrupt register</description>
- <addressOffset>0x328</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT2</name>
- <displayName>OTG_HS_DOEPINT2</displayName>
- <description>OTG_HS device endpoint-2 interrupt register</description>
- <addressOffset>0x348</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT3</name>
- <displayName>OTG_HS_DOEPINT3</displayName>
- <description>OTG_HS device endpoint-3 interrupt register</description>
- <addressOffset>0x368</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT4</name>
- <displayName>OTG_HS_DOEPINT4</displayName>
- <description>OTG_HS device endpoint-4 interrupt register</description>
- <addressOffset>0x388</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT5</name>
- <displayName>OTG_HS_DOEPINT5</displayName>
- <description>OTG_HS device endpoint-5 interrupt register</description>
- <addressOffset>0x3A8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT6</name>
- <displayName>OTG_HS_DOEPINT6</displayName>
- <description>OTG_HS device endpoint-6 interrupt register</description>
- <addressOffset>0x3C8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPINT7</name>
- <displayName>OTG_HS_DOEPINT7</displayName>
- <description>OTG_HS device endpoint-7 interrupt register</description>
- <addressOffset>0x3E8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRC</name>
- <description>Transfer completed interrupt</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPDISD</name>
- <description>Endpoint disabled interrupt</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUP</name>
- <description>SETUP phase done</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OTEPDIS</name>
- <description>OUT token received when endpoint disabled</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>B2BSTUP</name>
- <description>Back-to-back SETUP packets received</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NYET</name>
- <description>NYET interrupt</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ0</name>
- <displayName>OTG_HS_DOEPTSIZ0</displayName>
- <description>OTG_HS device endpoint-0 transfer size register</description>
- <addressOffset>0x310</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STUPCNT</name>
- <description>SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ1</name>
- <displayName>OTG_HS_DOEPTSIZ1</displayName>
- <description>OTG_HS device endpoint-1 transfer size register</description>
- <addressOffset>0x330</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ2</name>
- <displayName>OTG_HS_DOEPTSIZ2</displayName>
- <description>OTG_HS device endpoint-2 transfer size register</description>
- <addressOffset>0x350</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ3</name>
- <displayName>OTG_HS_DOEPTSIZ3</displayName>
- <description>OTG_HS device endpoint-3 transfer size register</description>
- <addressOffset>0x370</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ4</name>
- <displayName>OTG_HS_DOEPTSIZ4</displayName>
- <description>OTG_HS device endpoint-4 transfer size register</description>
- <addressOffset>0x390</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ6</name>
- <displayName>OTG_HS_DIEPTSIZ6</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <alternateRegister>OTG_HS_DIEPCTL5</alternateRegister>
- <addressOffset>0x1A0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS6</name>
- <displayName>OTG_HS_DTXFSTS6</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x1A4</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DIEPTSIZ7</name>
- <displayName>OTG_HS_DIEPTSIZ7</displayName>
- <description>OTG_HS device endpoint transfer size register</description>
- <alternateRegister>OTG_HS_DIEPINT5</alternateRegister>
- <addressOffset>0x1A8</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>MCNT</name>
- <description>Multi count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DTXFSTS7</name>
- <displayName>OTG_HS_DTXFSTS7</displayName>
- <description>OTG_HS device IN endpoint transmit FIFO status register</description>
- <addressOffset>0x1AC</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>INEPTFSAV</name>
- <description>IN endpoint TxFIFO space avail</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL4</name>
- <displayName>OTG_HS_DOEPCTL4</displayName>
- <description>OTG device endpoint-4 control register</description>
- <addressOffset>0x380</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL5</name>
- <displayName>OTG_HS_DOEPCTL5</displayName>
- <description>OTG device endpoint-5 control register</description>
- <addressOffset>0x3A0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL6</name>
- <displayName>OTG_HS_DOEPCTL6</displayName>
- <description>OTG device endpoint-6 control register</description>
- <addressOffset>0x3C0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPCTL7</name>
- <displayName>OTG_HS_DOEPCTL7</displayName>
- <description>OTG device endpoint-7 control register</description>
- <addressOffset>0x3E0</addressOffset>
- <size>32</size>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>MPSIZ</name>
- <description>Maximum packet size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>11</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>USBAEP</name>
- <description>USB active endpoint</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EONUM_DPID</name>
- <description>Even odd frame/Endpoint data PID</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>NAKSTS</name>
- <description>NAK status</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-only</access>
- </field>
- <field>
- <name>EPTYP</name>
- <description>Endpoint type</description>
- <bitOffset>18</bitOffset>
- <bitWidth>2</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>SNPM</name>
- <description>Snoop mode</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>Stall</name>
- <description>STALL handshake</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>CNAK</name>
- <description>Clear NAK</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SNAK</name>
- <description>Set NAK</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SD0PID_SEVNFRM</name>
- <description>Set DATA0 PID/Set even frame</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>SODDFRM</name>
- <description>Set odd frame</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- <access>write-only</access>
- </field>
- <field>
- <name>EPDIS</name>
- <description>Endpoint disable</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- <field>
- <name>EPENA</name>
- <description>Endpoint enable</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ5</name>
- <displayName>OTG_HS_DOEPTSIZ5</displayName>
- <description>OTG_HS device endpoint-5 transfer size register</description>
- <addressOffset>0x3B0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ6</name>
- <displayName>OTG_HS_DOEPTSIZ6</displayName>
- <description>OTG_HS device endpoint-6 transfer size register</description>
- <addressOffset>0x3D0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>OTG_HS_DOEPTSIZ7</name>
- <displayName>OTG_HS_DOEPTSIZ7</displayName>
- <description>OTG_HS device endpoint-7 transfer size register</description>
- <addressOffset>0x3F0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>XFRSIZ</name>
- <description>Transfer size</description>
- <bitOffset>0</bitOffset>
- <bitWidth>19</bitWidth>
- </field>
- <field>
- <name>PKTCNT</name>
- <description>Packet count</description>
- <bitOffset>19</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>RXDPID_STUPCNT</name>
- <description>Received data PID/SETUP packet count</description>
- <bitOffset>29</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>OTG_HS_PWRCLK</name>
- <description>USB on the go high speed</description>
- <groupName>USB_OTG_HS</groupName>
- <baseAddress>0x40040E00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x3F200</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>OTG_HS_EP1_OUT</name>
- <description>USB On The Go HS End Point 1 Out global
- interrupt</description>
- <value>74</value>
- </interrupt>
- <interrupt>
- <name>OTG_HS_EP1_IN</name>
- <description>USB On The Go HS End Point 1 In global
- interrupt</description>
- <value>75</value>
- </interrupt>
- <interrupt>
- <name>OTG_HS_WKUP</name>
- <description>USB On The Go HS Wakeup through EXTI
- interrupt</description>
- <value>76</value>
- </interrupt>
- <interrupt>
- <name>OTG_HS</name>
- <description>USB On The Go HS global
- interrupt</description>
- <value>77</value>
- </interrupt>
- <registers>
- <register>
- <name>OTG_HS_PCGCR</name>
- <displayName>OTG_HS_PCGCR</displayName>
- <description>Power and clock gating control register</description>
- <addressOffset>0x0</addressOffset>
- <size>32</size>
- <access>read-write</access>
- <resetValue>0x0</resetValue>
- <fields>
- <field>
- <name>STPPCLK</name>
- <description>Stop PHY clock</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GATEHCLK</name>
- <description>Gate HCLK</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PHYSUSP</name>
- <description>PHY suspended</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>NVIC</name>
- <description>Nested Vectored Interrupt Controller</description>
- <groupName>NVIC</groupName>
- <baseAddress>0xE000E100</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x369</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>ISER0</name>
- <displayName>ISER0</displayName>
- <description>Interrupt Set-Enable Register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETENA</name>
- <description>SETENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISER1</name>
- <displayName>ISER1</displayName>
- <description>Interrupt Set-Enable Register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETENA</name>
- <description>SETENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISER2</name>
- <displayName>ISER2</displayName>
- <description>Interrupt Set-Enable Register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETENA</name>
- <description>SETENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICER0</name>
- <displayName>ICER0</displayName>
- <description>Interrupt Clear-Enable Register</description>
- <addressOffset>0x80</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRENA</name>
- <description>CLRENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICER1</name>
- <displayName>ICER1</displayName>
- <description>Interrupt Clear-Enable Register</description>
- <addressOffset>0x84</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRENA</name>
- <description>CLRENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICER2</name>
- <displayName>ICER2</displayName>
- <description>Interrupt Clear-Enable Register</description>
- <addressOffset>0x88</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRENA</name>
- <description>CLRENA</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISPR0</name>
- <displayName>ISPR0</displayName>
- <description>Interrupt Set-Pending Register</description>
- <addressOffset>0x100</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETPEND</name>
- <description>SETPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISPR1</name>
- <displayName>ISPR1</displayName>
- <description>Interrupt Set-Pending Register</description>
- <addressOffset>0x104</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETPEND</name>
- <description>SETPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ISPR2</name>
- <displayName>ISPR2</displayName>
- <description>Interrupt Set-Pending Register</description>
- <addressOffset>0x108</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SETPEND</name>
- <description>SETPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICPR0</name>
- <displayName>ICPR0</displayName>
- <description>Interrupt Clear-Pending Register</description>
- <addressOffset>0x180</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRPEND</name>
- <description>CLRPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICPR1</name>
- <displayName>ICPR1</displayName>
- <description>Interrupt Clear-Pending Register</description>
- <addressOffset>0x184</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRPEND</name>
- <description>CLRPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICPR2</name>
- <displayName>ICPR2</displayName>
- <description>Interrupt Clear-Pending Register</description>
- <addressOffset>0x188</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>CLRPEND</name>
- <description>CLRPEND</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IABR0</name>
- <displayName>IABR0</displayName>
- <description>Interrupt Active Bit Register</description>
- <addressOffset>0x200</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ACTIVE</name>
- <description>ACTIVE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IABR1</name>
- <displayName>IABR1</displayName>
- <description>Interrupt Active Bit Register</description>
- <addressOffset>0x204</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ACTIVE</name>
- <description>ACTIVE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IABR2</name>
- <displayName>IABR2</displayName>
- <description>Interrupt Active Bit Register</description>
- <addressOffset>0x208</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ACTIVE</name>
- <description>ACTIVE</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR0</name>
- <displayName>IPR0</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x300</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR1</name>
- <displayName>IPR1</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x304</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR2</name>
- <displayName>IPR2</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x308</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR3</name>
- <displayName>IPR3</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x30C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR4</name>
- <displayName>IPR4</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x310</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR5</name>
- <displayName>IPR5</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x314</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR6</name>
- <displayName>IPR6</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x318</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR7</name>
- <displayName>IPR7</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x31C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR8</name>
- <displayName>IPR8</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x320</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR9</name>
- <displayName>IPR9</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x324</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR10</name>
- <displayName>IPR10</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x328</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR11</name>
- <displayName>IPR11</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x32C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR12</name>
- <displayName>IPR12</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x330</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR13</name>
- <displayName>IPR13</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x334</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR14</name>
- <displayName>IPR14</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x338</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR15</name>
- <displayName>IPR15</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x33C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR16</name>
- <displayName>IPR16</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x340</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR17</name>
- <displayName>IPR17</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x344</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR18</name>
- <displayName>IPR18</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x348</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR19</name>
- <displayName>IPR19</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x34C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR20</name>
- <displayName>IPR20</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x350</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR21</name>
- <displayName>IPR21</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x354</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR22</name>
- <displayName>IPR22</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x358</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR23</name>
- <displayName>IPR23</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x35C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR24</name>
- <displayName>IPR24</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x360</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>IPR25</name>
- <displayName>IPR25</displayName>
- <description>Interrupt Priority Register</description>
- <addressOffset>0x364</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IPR_N0</name>
- <description>IPR_N0</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N1</name>
- <description>IPR_N1</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N2</name>
- <description>IPR_N2</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IPR_N3</name>
- <description>IPR_N3</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>MPU</name>
- <description>Memory protection unit</description>
- <groupName>MPU</groupName>
- <baseAddress>0xE000ED90</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x15</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>MPU_TYPER</name>
- <displayName>MPU_TYPER</displayName>
- <description>MPU type register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0X00000800</resetValue>
- <fields>
- <field>
- <name>SEPARATE</name>
- <description>Separate flag</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DREGION</name>
- <description>Number of MPU data regions</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>IREGION</name>
- <description>Number of MPU instruction regions</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MPU_CTRL</name>
- <displayName>MPU_CTRL</displayName>
- <description>MPU control register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Enables the MPU</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HFNMIENA</name>
- <description>Enables the operation of MPU during hard fault</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PRIVDEFENA</name>
- <description>Enable priviliged software access to default memory map</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MPU_RNR</name>
- <displayName>MPU_RNR</displayName>
- <description>MPU region number register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>REGION</name>
- <description>MPU region</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MPU_RBAR</name>
- <displayName>MPU_RBAR</displayName>
- <description>MPU region base address register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>REGION</name>
- <description>MPU region field</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>VALID</name>
- <description>MPU region number valid</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ADDR</name>
- <description>Region base address field</description>
- <bitOffset>5</bitOffset>
- <bitWidth>27</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MPU_RASR</name>
- <displayName>MPU_RASR</displayName>
- <description>MPU region attribute and size register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Region enable bit.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SIZE</name>
- <description>Size of the MPU protection region</description>
- <bitOffset>1</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- <field>
- <name>SRD</name>
- <description>Subregion disable bits</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>B</name>
- <description>memory attribute</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>C</name>
- <description>memory attribute</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>S</name>
- <description>Shareable memory attribute</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TEX</name>
- <description>memory attribute</description>
- <bitOffset>19</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>AP</name>
- <description>Access permission</description>
- <bitOffset>24</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>XN</name>
- <description>Instruction access disable bit</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>STK</name>
- <description>SysTick timer</description>
- <groupName>STK</groupName>
- <baseAddress>0xE000E010</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x11</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CSR</name>
- <displayName>CSR</displayName>
- <description>SysTick control and status register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>ENABLE</name>
- <description>Counter enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>TICKINT</name>
- <description>SysTick exception request enable</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>CLKSOURCE</name>
- <description>Clock source selection</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>COUNTFLAG</name>
- <description>COUNTFLAG</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>RVR</name>
- <displayName>RVR</displayName>
- <description>SysTick reload value register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>RELOAD</name>
- <description>RELOAD value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CVR</name>
- <displayName>CVR</displayName>
- <description>SysTick current value register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>CURRENT</name>
- <description>Current counter value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CALIB</name>
- <displayName>CALIB</displayName>
- <description>SysTick calibration value register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>TENMS</name>
- <description>Calibration value</description>
- <bitOffset>0</bitOffset>
- <bitWidth>24</bitWidth>
- </field>
- <field>
- <name>SKEW</name>
- <description>SKEW flag: Indicates whether the TENMS value is exact</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NOREF</name>
- <description>NOREF flag. Reads as zero</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>NVIC_STIR</name>
- <description>Nested vectored interrupt controller</description>
- <groupName>NVIC</groupName>
- <baseAddress>0xE000EF00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x5</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>STIR</name>
- <displayName>STIR</displayName>
- <description>Software trigger interrupt register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>INTID</name>
- <description>Software generated interrupt ID</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>FPU_CPACR</name>
- <description>Floating point unit CPACR</description>
- <groupName>FPU</groupName>
- <baseAddress>0xE000ED88</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x5</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CPACR</name>
- <displayName>CPACR</displayName>
- <description>Coprocessor access control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x0000000</resetValue>
- <fields>
- <field>
- <name>CP</name>
- <description>CP</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCB_ACTRL</name>
- <description>System control block ACTLR</description>
- <groupName>SCB</groupName>
- <baseAddress>0xE000E008</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x5</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>ACTRL</name>
- <displayName>ACTRL</displayName>
- <description>Auxiliary control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>DISFOLD</name>
- <description>DISFOLD</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FPEXCODIS</name>
- <description>FPEXCODIS</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DISRAMODE</name>
- <description>DISRAMODE</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DISITMATBFLUSH</name>
- <description>DISITMATBFLUSH</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>FPU</name>
- <description>Floting point unit</description>
- <groupName>FPU</groupName>
- <baseAddress>0xE000EF34</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0xD</size>
- <usage>registers</usage>
- </addressBlock>
- <interrupt>
- <name>FPU</name>
- <description>Floating point unit interrupt</description>
- <value>81</value>
- </interrupt>
- <registers>
- <register>
- <name>FPCCR</name>
- <displayName>FPCCR</displayName>
- <description>Floating-point context control register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>LSPACT</name>
- <description>LSPACT</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USER</name>
- <description>USER</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>THREAD</name>
- <description>THREAD</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>HFRDY</name>
- <description>HFRDY</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMRDY</name>
- <description>MMRDY</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BFRDY</name>
- <description>BFRDY</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MONRDY</name>
- <description>MONRDY</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSPEN</name>
- <description>LSPEN</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ASPEN</name>
- <description>ASPEN</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FPCAR</name>
- <displayName>FPCAR</displayName>
- <description>Floating-point context address register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ADDRESS</name>
- <description>Location of unpopulated floating-point</description>
- <bitOffset>3</bitOffset>
- <bitWidth>29</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>FPSCR</name>
- <displayName>FPSCR</displayName>
- <description>Floating-point status control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IOC</name>
- <description>Invalid operation cumulative exception bit</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DZC</name>
- <description>Division by zero cumulative exception bit.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>OFC</name>
- <description>Overflow cumulative exception bit</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UFC</name>
- <description>Underflow cumulative exception bit</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IXC</name>
- <description>Inexact cumulative exception bit</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IDC</name>
- <description>Input denormal cumulative exception bit.</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RMode</name>
- <description>Rounding Mode control field</description>
- <bitOffset>22</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>FZ</name>
- <description>Flush-to-zero mode control bit:</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DN</name>
- <description>Default NaN mode control bit</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHP</name>
- <description>Alternative half-precision control bit</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>V</name>
- <description>Overflow condition code flag</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>C</name>
- <description>Carry condition code flag</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>Z</name>
- <description>Zero condition code flag</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>N</name>
- <description>Negative condition code flag</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCB</name>
- <description>System control block</description>
- <groupName>SCB</groupName>
- <baseAddress>0xE000ED00</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x41</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CPUID</name>
- <displayName>CPUID</displayName>
- <description>CPUID base register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x410FC241</resetValue>
- <fields>
- <field>
- <name>Revision</name>
- <description>Revision number</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>PartNo</name>
- <description>Part number of the processor</description>
- <bitOffset>4</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- <field>
- <name>Constant</name>
- <description>Reads as 0xF</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>Variant</name>
- <description>Variant number</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>Implementer</name>
- <description>Implementer code</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ICSR</name>
- <displayName>ICSR</displayName>
- <description>Interrupt control and state register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>VECTACTIVE</name>
- <description>Active vector</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>RETTOBASE</name>
- <description>Return to base level</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VECTPENDING</name>
- <description>Pending vector</description>
- <bitOffset>12</bitOffset>
- <bitWidth>7</bitWidth>
- </field>
- <field>
- <name>ISRPENDING</name>
- <description>Interrupt pending flag</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PENDSTCLR</name>
- <description>SysTick exception clear-pending bit</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PENDSTSET</name>
- <description>SysTick exception set-pending bit</description>
- <bitOffset>26</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PENDSVCLR</name>
- <description>PendSV clear-pending bit</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PENDSVSET</name>
- <description>PendSV set-pending bit</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NMIPENDSET</name>
- <description>NMI set-pending bit.</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>VTOR</name>
- <displayName>VTOR</displayName>
- <description>Vector table offset register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>TBLOFF</name>
- <description>Vector table base offset field</description>
- <bitOffset>9</bitOffset>
- <bitWidth>21</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AIRCR</name>
- <displayName>AIRCR</displayName>
- <description>Application interrupt and reset control register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>VECTRESET</name>
- <description>VECTRESET</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VECTCLRACTIVE</name>
- <description>VECTCLRACTIVE</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYSRESETREQ</name>
- <description>SYSRESETREQ</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PRIGROUP</name>
- <description>PRIGROUP</description>
- <bitOffset>8</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>ENDIANESS</name>
- <description>ENDIANESS</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>VECTKEYSTAT</name>
- <description>Register key</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SCR</name>
- <displayName>SCR</displayName>
- <description>System control register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>SLEEPONEXIT</name>
- <description>SLEEPONEXIT</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SLEEPDEEP</name>
- <description>SLEEPDEEP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SEVEONPEND</name>
- <description>Send Event on Pending bit</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCR</name>
- <displayName>CCR</displayName>
- <description>Configuration and control register</description>
- <addressOffset>0x14</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>NONBASETHRDENA</name>
- <description>Configures how the processor enters Thread mode</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USERSETMPEND</name>
- <description>USERSETMPEND</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UNALIGN__TRP</name>
- <description>UNALIGN_ TRP</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIV_0_TRP</name>
- <description>DIV_0_TRP</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BFHFNMIGN</name>
- <description>BFHFNMIGN</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STKALIGN</name>
- <description>STKALIGN</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DC</name>
- <description>DC</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IC</name>
- <description>IC</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BP</name>
- <description>BP</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SHPR1</name>
- <displayName>SHPR1</displayName>
- <description>System handler priority registers</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PRI_4</name>
- <description>Priority of system handler 4</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>PRI_5</name>
- <description>Priority of system handler 5</description>
- <bitOffset>8</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>PRI_6</name>
- <description>Priority of system handler 6</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SHPR2</name>
- <displayName>SHPR2</displayName>
- <description>System handler priority registers</description>
- <addressOffset>0x1C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PRI_11</name>
- <description>Priority of system handler 11</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SHPR3</name>
- <displayName>SHPR3</displayName>
- <description>System handler priority registers</description>
- <addressOffset>0x20</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>PRI_14</name>
- <description>Priority of system handler 14</description>
- <bitOffset>16</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- <field>
- <name>PRI_15</name>
- <description>Priority of system handler 15</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>SHCRS</name>
- <displayName>SHCRS</displayName>
- <description>System handler control and state register</description>
- <addressOffset>0x24</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>MEMFAULTACT</name>
- <description>Memory management fault exception active bit</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BUSFAULTACT</name>
- <description>Bus fault exception active bit</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USGFAULTACT</name>
- <description>Usage fault exception active bit</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SVCALLACT</name>
- <description>SVC call active bit</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MONITORACT</name>
- <description>Debug monitor active bit</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PENDSVACT</name>
- <description>PendSV exception active bit</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SYSTICKACT</name>
- <description>SysTick exception active bit</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USGFAULTPENDED</name>
- <description>Usage fault exception pending bit</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MEMFAULTPENDED</name>
- <description>Memory management fault exception pending bit</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BUSFAULTPENDED</name>
- <description>Bus fault exception pending bit</description>
- <bitOffset>14</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SVCALLPENDED</name>
- <description>SVC call pending bit</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MEMFAULTENA</name>
- <description>Memory management fault enable bit</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BUSFAULTENA</name>
- <description>Bus fault enable bit</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>USGFAULTENA</name>
- <description>Usage fault enable bit</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CFSR_UFSR_BFSR_MMFSR</name>
- <displayName>CFSR_UFSR_BFSR_MMFSR</displayName>
- <description>Configurable fault status register</description>
- <addressOffset>0x28</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>IACCVIOL</name>
- <description>IACCVIOL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DACCVIOL</name>
- <description>DACCVIOL</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MUNSTKERR</name>
- <description>MUNSTKERR</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MSTKERR</name>
- <description>MSTKERR</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MLSPERR</name>
- <description>MLSPERR</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>MMARVALID</name>
- <description>MMARVALID</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IBUSERR</name>
- <description>Instruction bus error</description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>PRECISERR</name>
- <description>Precise data bus error</description>
- <bitOffset>9</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IMPRECISERR</name>
- <description>Imprecise data bus error</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UNSTKERR</name>
- <description>Bus fault on unstacking for a return from exception</description>
- <bitOffset>11</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>STKERR</name>
- <description>Bus fault on stacking for exception entry</description>
- <bitOffset>12</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>LSPERR</name>
- <description>Bus fault on floating-point lazy state preservation</description>
- <bitOffset>13</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>BFARVALID</name>
- <description>Bus Fault Address Register (BFAR) valid flag</description>
- <bitOffset>15</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UNDEFINSTR</name>
- <description>Undefined instruction usage fault</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INVSTATE</name>
- <description>Invalid state usage fault</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>INVPC</name>
- <description>Invalid PC load usage fault</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>NOCP</name>
- <description>No coprocessor usage fault.</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>UNALIGNED</name>
- <description>Unaligned access usage fault</description>
- <bitOffset>24</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DIVBYZERO</name>
- <description>Divide by zero usage fault</description>
- <bitOffset>25</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>HFSR</name>
- <displayName>HFSR</displayName>
- <description>Hard fault status register</description>
- <addressOffset>0x2C</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>VECTTBL</name>
- <description>Vector table hard fault</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FORCED</name>
- <description>Forced hard fault</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DEBUG_VT</name>
- <description>Reserved for Debug use</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MMFAR</name>
- <displayName>MMFAR</displayName>
- <description>Memory management fault address register</description>
- <addressOffset>0x34</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ADDRESS</name>
- <description>Memory management fault address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>BFAR</name>
- <displayName>BFAR</displayName>
- <description>Bus fault address register</description>
- <addressOffset>0x38</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0x00000000</resetValue>
- <fields>
- <field>
- <name>ADDRESS</name>
- <description>Bus fault address</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>PF</name>
- <description>Processor features</description>
- <groupName>PF</groupName>
- <baseAddress>0xE000ED78</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0xD</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CLIDR</name>
- <displayName>CLIDR</displayName>
- <description>Cache Level ID register</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0x09000003</resetValue>
- <fields>
- <field>
- <name>CL1</name>
- <description>CL1</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL2</name>
- <description>CL2</description>
- <bitOffset>3</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL3</name>
- <description>CL3</description>
- <bitOffset>6</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL4</name>
- <description>CL4</description>
- <bitOffset>9</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL5</name>
- <description>CL5</description>
- <bitOffset>12</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL6</name>
- <description>CL6</description>
- <bitOffset>15</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>CL7</name>
- <description>CL7</description>
- <bitOffset>18</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>LoUIS</name>
- <description>LoUIS</description>
- <bitOffset>21</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>LoC</name>
- <description>LoC</description>
- <bitOffset>24</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>LoU</name>
- <description>LoU</description>
- <bitOffset>27</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CTR</name>
- <displayName>CTR</displayName>
- <description>Cache Type register</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0X8303C003</resetValue>
- <fields>
- <field>
- <name>_IminLine</name>
- <description>IminLine</description>
- <bitOffset>0</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>DMinLine</name>
- <description>DMinLine</description>
- <bitOffset>16</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>ERG</name>
- <description>ERG</description>
- <bitOffset>20</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CWG</name>
- <description>CWG</description>
- <bitOffset>24</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>Format</name>
- <description>Format</description>
- <bitOffset>29</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CCSIDR</name>
- <displayName>CCSIDR</displayName>
- <description>Cache Size ID register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-only</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>LineSize</name>
- <description>LineSize</description>
- <bitOffset>0</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- <field>
- <name>Associativity</name>
- <description>Associativity</description>
- <bitOffset>3</bitOffset>
- <bitWidth>10</bitWidth>
- </field>
- <field>
- <name>NumSets</name>
- <description>NumSets</description>
- <bitOffset>13</bitOffset>
- <bitWidth>15</bitWidth>
- </field>
- <field>
- <name>WA</name>
- <description>WA</description>
- <bitOffset>28</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RA</name>
- <description>RA</description>
- <bitOffset>29</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WB</name>
- <description>WB</description>
- <bitOffset>30</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>WT</name>
- <description>WT</description>
- <bitOffset>31</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>AC</name>
- <description>Access control</description>
- <groupName>AC</groupName>
- <baseAddress>0xE000EF90</baseAddress>
- <addressBlock>
- <offset>0x0</offset>
- <size>0x1D</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>ITCMCR</name>
- <displayName>ITCMCR</displayName>
- <description>Instruction and Data Tightly-Coupled Memory Control Registers</description>
- <addressOffset>0x0</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>EN</name>
- <description>EN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RMW</name>
- <description>RMW</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RETEN</name>
- <description>RETEN</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SZ</name>
- <description>SZ</description>
- <bitOffset>3</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>DTCMCR</name>
- <displayName>DTCMCR</displayName>
- <description>Instruction and Data Tightly-Coupled Memory Control Registers</description>
- <addressOffset>0x4</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>EN</name>
- <description>EN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RMW</name>
- <description>RMW</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RETEN</name>
- <description>RETEN</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SZ</name>
- <description>SZ</description>
- <bitOffset>3</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHBPCR</name>
- <displayName>AHBPCR</displayName>
- <description>AHBP Control register</description>
- <addressOffset>0x8</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>EN</name>
- <description>EN</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>SZ</name>
- <description>SZ</description>
- <bitOffset>1</bitOffset>
- <bitWidth>3</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CACR</name>
- <displayName>CACR</displayName>
- <description>Auxiliary Cache Control register</description>
- <addressOffset>0xC</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>SIWT</name>
- <description>SIWT</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>ECCEN</name>
- <description>ECCEN</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>FORCEWT</name>
- <description>FORCEWT</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>AHBSCR</name>
- <displayName>AHBSCR</displayName>
- <description>AHB Slave Control register</description>
- <addressOffset>0x10</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>CTL</name>
- <description>CTL</description>
- <bitOffset>0</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- <field>
- <name>TPRI</name>
- <description>TPRI</description>
- <bitOffset>2</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>INITCOUNT</name>
- <description>INITCOUNT</description>
- <bitOffset>11</bitOffset>
- <bitWidth>5</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>ABFSR</name>
- <displayName>ABFSR</displayName>
- <description>Auxiliary Bus Fault Status register</description>
- <addressOffset>0x18</addressOffset>
- <size>0x20</size>
- <access>read-write</access>
- <resetValue>0X00000000</resetValue>
- <fields>
- <field>
- <name>ITCM</name>
- <description>ITCM</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>DTCM</name>
- <description>DTCM</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AHBP</name>
- <description>AHBP</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AXIM</name>
- <description>AXIM</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>EPPB</name>
- <description>EPPB</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>AXIMTYPE</name>
- <description>AXIMTYPE</description>
- <bitOffset>8</bitOffset>
- <bitWidth>2</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
- </peripherals>
-</device>
diff --git a/old_examples/entrypoints/anakin/anakin-accel.cpp b/old_examples/entrypoints/anakin/anakin-accel.cpp
deleted file mode 100644
index 9d22fa1e89177b093c2aa30dad997e8e5e53e191..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/anakin-accel.cpp
+++ /dev/null
@@ -1,147 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <sensors/MAX21105.h>
-#include <sensors/MPU9250.h>
-#include <sensors/iNemo.h>
-
-using namespace miosix;
-
-#define SENSOR(NAME, CSPORT, CSPIN) \
- typedef Gpio<GPIO##CSPORT##_BASE, CSPIN> CS_##NAME; \
- typedef ProtocolSPI<busSPI1, CS_##NAME> spi##NAME
-
-#define READ(NAME, ID) spi##NAME::read(ID)
-#define TEST(NAME, REG, REF) test_and_print(#NAME, REG, READ(NAME, REG), REF)
-
-#define ACCEL_ENDLESS_TEST
-
-// SPI1
-typedef Gpio<GPIOA_BASE, 5> GpioSck;
-typedef Gpio<GPIOA_BASE, 6> GpioMiso;
-typedef Gpio<GPIOA_BASE, 7> GpioMosi;
-typedef BusSPI<1, GpioMosi, GpioMiso, GpioSck> busSPI1;
-
-// clang-format off
-// Here's the list of SPI sensors that should be tested
-// | NAME | CSPORT | CSPIN |
-SENSOR(MPU9250, D, 13);
-SENSOR(FXAS21002, G, 10);
-SENSOR(MAX21105, E, 2);
-SENSOR(MAX31856, B, 11);
-SENSOR(LSM9DS0_G, G, 9);
-SENSOR(LSM9DS0_A, G, 11);
-SENSOR(LPS331AP, E, 4);
-SENSOR(MS580301BA07, B, 10);
-// clang-format on
-
-static const char mOK[] = "OK";
-static const char mKO[] = "FAIL";
-
-int num_ok = 0, num_fail = 0;
-
-typedef MAX21105<spiMAX21105> max_t;
-typedef iNEMOLSM9DS0<spiLSM9DS0_G, spiLSM9DS0_A> lsm_t;
-typedef MPU9250<spiMPU9250> mpu_t;
-typedef struct
-{
- Vec3 v[3];
-} vec_t;
-
-Vec3 calcMid(vec_t data[5], int j)
-{
- Vec3 ret;
-
- for (int i = 0; i < 5; i++)
- ret += Vec3(data[i].v[j]);
-
- ret *= 1.0 / 5.0;
-
- return ret;
-}
-
-void calibrate(const vec_t &data[10])
-{
- for (const auto &i : data)
- {
- for (int j = 0; j < 3; j++)
- {
- i->v[j].normalize();
- i->v[j] *= EARTH_GRAVITY;
- }
- }
-}
-
-int main()
-{
- vec_t data[5];
- vector<AccelSensor *> accels;
- accels.push_back(
- new lsm_t(lsm_t::ACC_FS_2G, lsm_t::GYRO_FS_245, lsm_t::COMPASS_FS_2));
- accels.push_back(new mpu_t(mpu_t::ACC_FS_2G, mpu_t::GYRO_FS_250));
- accels.push_back(new max_t(max_t::ACC_FS_2G, max_t::GYRO_FS_250));
-
- uint16_t cnt = 0;
-
- for (auto jj : accels)
- jj->init();
-
- printf("Wait..\n");
- Thread::sleep(2000);
- printf("Calibrating..\n");
-
- vec_t caa[10];
-
- for (int i = 0; i < 10; i++)
- {
- for (int j = 0; j < 3; j++)
- {
- AccelSensor *a = accels[j];
- a->updateParams();
- caa[i].v[j] = a->getAccel();
- }
- printf("%02d/10...\r", i + 1);
- Thread::sleep(20);
- }
-
- calibrate(caa);
-
- while (true)
- {
- printf("%05d ", cnt);
- for (int j = 0; j < 3; j++)
- {
- AccelSensor *i = accels[j];
- i->updateParams();
- data[cnt % 5].v[j] = i->getAccel();
-
- Vec3 mid = adjust(data, j);
- printf("[%+5.2f,%+5.2f,%+5.2f] ", mid.getX(), mid.getY(),
- mid.getZ());
- }
- printf(" \r");
- cnt++;
- Thread::sleep(10);
- }
-}
diff --git a/old_examples/entrypoints/anakin/anakin-demo-board.cpp b/old_examples/entrypoints/anakin/anakin-demo-board.cpp
deleted file mode 100644
index a51bc42a4f8e26ba524224d0399ae31054a08e44..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/anakin-demo-board.cpp
+++ /dev/null
@@ -1,494 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/Leds.h>
-#include <drivers/ethernet/UdpManager.h>
-#include <drivers/stm32f2_f4_i2c.h>
-#include <math/Matrix.h>
-#include <math/Vec3.h>
-#include <sensors/FXAS21002.h>
-#include <sensors/LPS331AP.h>
-#include <sensors/MAX21105.h>
-#include <sensors/MAX31856.h>
-#include <sensors/MPL3115.h>
-#include <sensors/MPU9250.h>
-#include <sensors/MS580301BA07.h>
-#include <sensors/Si7021.h>
-#include <sensors/iNemo.h>
-
-using namespace miosix;
-using std::vector;
-
-//#define ENABLE_ETHERNET
-constexpr uint32_t lp_alpha = 250;
-constexpr uint32_t hp_beta = 700;
-
-#define SENSOR(NAME, CSPORT, CSPIN) \
- typedef Gpio<GPIO##CSPORT##_BASE, CSPIN> CS_##NAME; \
- typedef ProtocolSPI<busSPI1, CS_##NAME> spi##NAME
-
-// SPI1
-typedef Gpio<GPIOA_BASE, 5> GpioSck;
-typedef Gpio<GPIOA_BASE, 6> GpioMiso;
-typedef Gpio<GPIOA_BASE, 7> GpioMosi;
-typedef BusSPI<1, GpioMosi, GpioMiso, GpioSck> busSPI1;
-
-// clang-format off
-// Here's the list of SPI sensors that should be tested
-// | NAME | CSPORT | CSPIN |
-SENSOR(MPU9250, D, 13);
-SENSOR(FXAS21002, G, 10);
-SENSOR(MAX21105, E, 2);
-SENSOR(MAX31856, B, 11);
-SENSOR(LSM9DS0_G, G, 9);
-SENSOR(LSM9DS0_A, G, 11);
-SENSOR(LPS331AP, E, 4);
-SENSOR(MS580301BA07, B, 10);
-// clang-format on
-
-#pragma pack(1)
-struct pkt_t
-{
- float accel[3];
- float gyro[3];
- float compass[3];
- float temperature;
- float humidity;
- float pressure;
- float orientation[3];
-};
-#pragma pack()
-
-// Please don't judge me for these lines
-#define PUSH(a, b, x) \
- do \
- { \
- sensor_t zz = a, b; \
- sensors.push_back(zz); \
- x.push_back(zz); \
- } while (0)
-#define PUSH2(a, b, x, y) \
- do \
- { \
- sensor_t zz = a, b; \
- PUSH(a, b, x); \
- y.push_back(zz); \
- } while (0)
-#define PUSH3(a, b, x, y, z) \
- do \
- { \
- sensor_t zz = a, b; \
- PUSH2(a, b, x, y); \
- z.push_back(zz); \
- } while (0)
-#define PP(name, func) \
- do \
- { \
- printf("[Sensor] " name " started\n"); \
- func; \
- } while (0)
-
-class DemoBoard : public Singleton<DemoBoard>
-{
- friend class Singleton<DemoBoard>;
-
-public:
- void init() {}
-
- void update()
- {
- for (const sensor_t& s : sensors)
- (s.sensor)->onSimpleUpdate();
- }
-
-// Read a float value
-#define RFLO(x, y, k, z, w) \
- vector<x> y() const \
- { \
- vector<x> j; \
- for (const sensor_t& i : w) \
- { \
- j.push_back(*((dynamic_cast<z*>(i.sensor))->k())); \
- } \
- return j; \
- }
-
-// Read a Vec3 value and multiply it by the sensor transform matrix
-#define RVEC(x, y, k, z, w) \
- vector<x> y() const \
- { \
- vector<x> j; \
- for (const sensor_t& i : w) \
- { \
- x vec = *(i.transform) * *((dynamic_cast<z*>(i.sensor))->k()); \
- j.push_back(vec); \
- } \
- return j; \
- }
- // clang-format off
- RVEC(Vec3, getAccel, accelDataPtr, AccelSensor, accel)
- RVEC(Vec3, getRotation, gyroDataPtr, GyroSensor, gyro)
- RVEC(Vec3, getCompass, compassDataPtr, CompassSensor, compass)
- RFLO(float, getTemperature, tempDataPtr, TemperatureSensor, temps)
- RFLO(float, getHumidity, humidityDataPtr,HumiditySensor, humidity)
- RFLO(float, getPressure, pressureDataPtr,PressureSensor, pressure)
- // clang-format on
-
-#undef RFLO
-#undef RVEC
-private:
- DemoBoard()
- {
- static const float v_inemo[16] = {0, 1, 0, 0, -1, 0, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 1};
- static const float v_mpu[16] = {-1, 0, 0, 0, 0, -1, 0, 0,
- 0, 0, 1, 0, 0, 0, 0, 1};
- static const Mat4 idMat = Mat4();
- static const Mat4 iNemoMat = Mat4(v_inemo);
- static const Mat4 mpuMat = Mat4(v_mpu);
-
- // ----- FXAS21102 -----
- typedef FXAS21002<spiFXAS21002> fx_t;
- fx_t* fx = new fx_t(fx_t::DPS500);
- if (fx->init())
- PP("FXAS21102", PUSH({fx, &idMat}, gyro));
- else
- printf("Cannot start FXAS21102\n");
-
- // ----- iNEMO -----
- typedef iNEMOLSM9DS0<spiLSM9DS0_G, spiLSM9DS0_A> pd_inemo_t;
- pd_inemo_t* nemo =
- new pd_inemo_t(pd_inemo_t::ACC_FS_2G, pd_inemo_t::GYRO_FS_245,
- pd_inemo_t::COMPASS_FS_2);
- if (nemo->init())
- PP("iNemo", PUSH3({nemo, &iNemoMat}, accel, gyro, compass));
- else
- printf("Cannot start iNemo\n");
-
- // ----- LPS331AP -----
- typedef LPS331AP<spiLPS331AP> lps_t;
- lps_t* lps = new lps_t(lps_t::SS_25HZ);
- if (lps->init())
- PP("LPS331AP", PUSH2({lps, &idMat}, pressure, temps));
- else
- printf("Cannot start LPS\n");
-
- // ----- MAX21105 -----
- typedef MAX21105<spiMAX21105> max21_t;
- max21_t* max21 = new max21_t(max21_t::ACC_FS_2G, max21_t::GYRO_FS_500);
- if (max21->init())
- PP("MAX21105", PUSH3({max21, &idMat}, accel, gyro, temps));
- else
- printf("Cannot start MAX21105\n");
-
- // ----- MPL3115 -----
- sensors::sda::mode(Mode::ALTERNATE_OD);
- sensors::sda::alternateFunction(4);
- sensors::scl::mode(Mode::ALTERNATE_OD);
- sensors::scl::alternateFunction(4);
-
- typedef MPL3115<ProtocolI2C<miosix::I2C1Driver> > mpl_t;
- mpl_t* mpl = new mpl_t();
- if (mpl->init())
- PP("MPL3115", PUSH2({mpl, &idMat}, pressure, temps));
- else
- printf("Cannot start MPL3115\n");
-
- // ----- MPU9250 -----
- typedef MPU9250<spiMPU9250> mpu_t;
- mpu_t* mpu = new mpu_t(mpu_t::ACC_FS_2G, mpu_t::GYRO_FS_250);
- if (mpu->init())
- PP("MPU9250", PUSH3({mpu, &mpuMat}, accel, compass, temps));
- else
- printf("Cannot start MPU9250\n");
-
- // ----- MS580301BA07 -----
- typedef MS580301BA07<spiMS580301BA07> ms5_t;
- ms5_t* ms5 = new ms5_t();
- if (ms5->init())
- PP("MS580301BA07", PUSH2({ms5, &idMat}, pressure, temps));
- else
- printf("Cannot start MS580\n");
-
- // ----- Si7021 -----
- typedef Si7021<ProtocolI2C<miosix::I2C1Driver> > si_t;
- si_t* si = new si_t();
- if (si->init())
- PP("Si7021", PUSH2({si, &idMat}, humidity, temps));
- else
- printf("Cannot start Si7021\n");
-
- printf("Loaded %d sensors\n", sensors.size());
- printf(" + %d gyro sensors\n", gyro.size());
- printf(" + %d accel sensors\n", accel.size());
- printf(" + %d compass sensors\n", compass.size());
- printf(" + %d temperature sensors\n", temps.size());
- printf(" + %d humidity sensors\n", humidity.size());
- printf(" + %d pressure sensors\n", pressure.size());
- }
-
- typedef struct
- {
- Sensor* sensor;
- const Mat4* transform;
- } sensor_t;
-
- vector<sensor_t> sensors;
- vector<sensor_t> accel;
- vector<sensor_t> gyro;
- vector<sensor_t> compass;
- vector<sensor_t> temps;
- vector<sensor_t> humidity;
- vector<sensor_t> pressure;
-#define sDemoBoard DemoBoard::getInstance()
-};
-
-Vec3 averageVec(const vector<Vec3>& in)
-{
- Vec3 out;
- for (const Vec3& i : in)
- out += i;
-
- if (in.size() > 0)
- out *= 1.0f / (float)in.size();
- return out;
-}
-
-float averageFloat(const vector<float>& in)
-{
- float out = 0;
- for (const float& i : in)
- out += i;
- if (in.size() > 0)
- out *= 1.0f / (float)in.size();
- return out;
-}
-
-template <uint32_t alpha>
-class LowPassPolicy
-{
-protected:
- static float process(uint16_t id, float in)
- {
- if (id >= storage.size())
- storage.resize(id + 1, 0.0);
-
- storage[id] += (alpha / 1000.0f) * (in - storage[id]);
- return storage[id];
- }
- static vector<float> storage;
-};
-
-template <uint32_t beta>
-class HighPassPolicy
-{
-protected:
- static float process(uint16_t id, float in)
- {
- if (id >= storage.size())
- {
- storage.resize(id + 1, 0.0);
- unfiltered.resize(id + 1, 0.0);
- }
-
- storage[id] = (beta / 1000.0f) * (storage[id] + in - unfiltered[id]);
- unfiltered[id] = in;
- return storage[id];
- }
- static vector<float> unfiltered;
- static vector<float> storage;
-};
-
-template <typename FilterPolicy>
-class BandFilter : private FilterPolicy
-{
-public:
- /* For each call, increment id of 3 * data.size() to avoid overlapping */
- static void process(uint16_t id, vector<Vec3>& data)
- {
- for (size_t i = 0; i < data.size(); i++)
- process(id + i * 3, data[i]);
- }
-
- /* For each call, increment id of data.size() to avoid overlapping */
- static void process(uint16_t id, vector<float>& data)
- {
- for (size_t i = 0; i < data.size(); i++)
- FilterPolicy::process(id + i, data[i]);
- }
-
- static void printStorage()
- {
- printf("Lowpass: [");
- for (const float& f : FilterPolicy::storage)
- printf("%5.2f ", f);
- printf("]\n");
- }
-
- static void process(uint16_t id, Vec3& data)
- {
- data.setX(FilterPolicy::process(id + 0, data.getX()));
- data.setY(FilterPolicy::process(id + 1, data.getY()));
- data.setZ(FilterPolicy::process(id + 2, data.getZ()));
- }
-};
-
-template <uint32_t alpha>
-vector<float> LowPassPolicy<alpha>::storage;
-template <uint32_t beta>
-vector<float> HighPassPolicy<beta>::storage;
-template <uint32_t beta>
-vector<float> HighPassPolicy<beta>::unfiltered;
-
-#define VECARRAY_FILTER(id, array) \
- do \
- { \
- BandFilter<LowPassPolicy<lp_alpha> >::process(id, array); \
- id += array.size() * 3; \
- } while (0)
-
-#define FLOATARRAY_FILTER(id, array) \
- do \
- { \
- BandFilter<LowPassPolicy<lp_alpha> >::process(id, array); \
- id += array.size(); \
- } while (0)
-
-#define COPYVEC(arr, v) \
- do \
- { \
- arr[0] = v.getX(); \
- arr[1] = v.getY(); \
- arr[2] = v.getZ(); \
- } while (0)
-
-int main()
-{
- Thread::sleep(100);
- sDemoBoard->init();
-
- // Ethernet setup
-#ifdef ENABLE_ETHERNET
- const uint8_t ipAddr[] = {192, 168, 1, 30}; // Device's IP address
- const uint8_t mask[] = {255, 255, 255, 0}; // Subnet mask
-
- const uint8_t destIp[] = {192, 168, 1, 4}; // Destination IP address
- const uint16_t destPort = 1234; // Destination port
-
- printf("[Ethernet] Starting...\n");
- W5200& eth = W5200::instance();
- eth.setIpAddress(ipAddr);
- eth.setSubnetMask(mask);
- printf("[Ethernet] Got addr\n");
-
- // This socket listens on UDP port 2020
- // UdpManager::getInstance().setTxPort(2020);
- printf("[Ethernet] Socket ready\n");
-#endif
-
- Vec3 orientation;
- Vec3 angularvel;
- int ignore_ctr = 100;
- int led_status = 0x200;
-
- while (1)
- {
- sDemoBoard->update();
- Thread::sleep(20);
-
- vector<Vec3> accels = sDemoBoard->getAccel();
- vector<Vec3> rots = sDemoBoard->getRotation();
- vector<Vec3> compsv = sDemoBoard->getCompass();
- vector<float> temps = sDemoBoard->getTemperature();
- vector<float> humid = sDemoBoard->getHumidity();
- vector<float> press = sDemoBoard->getPressure();
-
- uint16_t id = 0;
-
- VECARRAY_FILTER(id, accels);
- VECARRAY_FILTER(id, rots);
- BandFilter<HighPassPolicy<hp_beta> >::process(0, rots);
- VECARRAY_FILTER(id, compsv);
- FLOATARRAY_FILTER(id, temps);
- FLOATARRAY_FILTER(id, humid);
- FLOATARRAY_FILTER(id, press);
-
- Vec3 acc = averageVec(accels);
- Vec3 rot = averageVec(rots);
- Vec3 comps = averageVec(compsv);
- float tempm = averageFloat(temps);
- float humim = averageFloat(humid);
- float presm = averageFloat(press);
-
- pkt_t packet;
- COPYVEC(packet.accel, acc);
- COPYVEC(packet.gyro, rot);
- COPYVEC(packet.compass, comps);
- COPYVEC(packet.orientation, orientation);
- packet.temperature = tempm;
- packet.humidity = humim;
- packet.pressure = presm;
-
- Leds::set(led_status);
- if (ignore_ctr == 0)
- {
- led_status <<= 1;
- if (led_status == 0x400)
- led_status = 0x04;
- angularvel += rot * 0.2f;
- orientation += angularvel * 0.2f;
- BandFilter<HighPassPolicy<999> >::process(4, orientation);
- }
- else
- {
- led_status ^= 0x200;
- --ignore_ctr;
- if (ignore_ctr == 0)
- led_status = 0x04;
- }
-
-#ifdef ENABLE_ETHERNET
- sock.sendPacketTo(destIp, destPort, &packet, sizeof(packet));
-#endif
-
- printf(
- "[%5.2f %5.2f %5.2f] "
- "[%5.2f %5.2f %5.2f] "
- "[%d %5.2f %5.2f %5.2f] "
- "[%5.2f %5.2f %5.2f] "
- "[%5.2f %5.2f %5.2f] \r",
- acc.getX(), acc.getY(), acc.getZ(), rot.getX(), rot.getY(),
- rot.getZ(), ignore_ctr, orientation.getX(), orientation.getY(),
- orientation.getZ(), comps.getX(), comps.getY(), comps.getZ(), tempm,
- humim, presm);
-
- fflush(stdout);
- }
-
- // Bye.
- while (1)
- {
- Thread::sleep(1000);
- }
-}
diff --git a/old_examples/entrypoints/anakin/anakin-test-canbus.cpp b/old_examples/entrypoints/anakin/anakin-test-canbus.cpp
deleted file mode 100644
index e744cbe23e8776572eaa7b6d852601422c61ff52..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/anakin-test-canbus.cpp
+++ /dev/null
@@ -1,104 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/canbus/CanManager.h>
-#include <drivers/canbus/CanSocket.h>
-#include <drivers/canbus/CanUtils.h>
-
-using namespace miosix;
-
-#define DO_ENDLESS_CANBUS_TEST
-#ifndef BOARDNAME
-#define BOARDNAME "UNKNOWN"
-#endif
-
-static const uint8_t CAN_MYID = 0x49;
-
-void banner()
-{
- printf("****** CAN BUS TEST ROM ******\n");
- printf("My ID: '%s'\n", BOARDNAME);
- printf("\n");
-}
-
-void *test_canbus_recv(void *arg)
-{
- printf("[CAN RECV] Thread started\n");
-
- CanBus *bus = static_cast<CanBus *>(arg);
- CanSocket socket(CAN_MYID);
- char buf[16] = {0};
-
- printf("[CAN RECV] Opening socket\n");
- socket.open(bus);
-
- printf("[CAN RECV] Waiting for packets\n");
- while (true)
- {
- memset(buf, 0, sizeof(buf));
- socket.receive(buf, 16);
- printf("[CAN RECV]: %s\n", buf);
- }
- socket.close();
- return NULL;
-}
-
-void test_canbus_send(CanBus *bus)
-{
- printf("[CAN SEND] Starting test...\n");
- while (true)
- {
- getchar();
- leds::led0::high();
- const char *pkt = BOARDNAME;
- bus->send(CAN_MYID, (const uint8_t *)pkt, strlen(pkt));
- Thread::sleep(250);
- leds::led0::low();
- }
-}
-
-int main()
-{
- /* CAN1 = define di ST */
- CanManager c(CAN1);
-
- banner();
-
- /* */
- canbus_init_t st0 = {
- CAN1, Mode::ALTERNATE, 9, {CAN1_RX0_IRQn, CAN1_RX1_IRQn}};
- c.addBus<GPIOA_BASE, 11, 12>(st0);
-
- canbus_init_t st1 = {
- CAN2, Mode::ALTERNATE, 9, {CAN2_RX0_IRQn, CAN2_RX1_IRQn}};
- c.addBus<GPIOB_BASE, 12, 13>(st1);
-
- // Receive on CAN1
- Thread::create(test_canbus_recv, 1024, 1, static_cast<void *>(c.getBus(0)),
- Thread::JOINABLE);
- // Send on CAN2
- test_canbus_send(c.getBus(1));
-
- return 0;
-}
diff --git a/old_examples/entrypoints/anakin/anakin-test-dma.cpp b/old_examples/entrypoints/anakin/anakin-test-dma.cpp
deleted file mode 100644
index 03815abc7f272b3fea0c471fe82b00508d6650a4..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/anakin-test-dma.cpp
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <boards/AnakinBoard.h>
-#include <diagnostic/CpuMeter.h>
-#include <diagnostic/Log.h>
-#include <drivers/Leds.h>
-
-using namespace miosix;
-
-void fifoQueueSz(void* arg)
-{
- const SPIDriver& spi = SPIDriver::instance();
- int tx_accum = 0, rx_accum = 0, sz_ctr = 0;
- int qsize_accum = 0;
-
- sLog->logString("Thread started");
-
- while (1)
- {
- DMAFIFOStatus tx = spi.getTxFIFOStatus();
- DMAFIFOStatus rx = spi.getRxFIFOStatus();
-
- if (tx > -1 && rx > -1)
- {
- tx_accum += tx;
- rx_accum += rx;
- qsize_accum += sLog->getLogQueueSize();
- if (++sz_ctr == 100)
- {
- float tx1 = tx_accum / (float)(DFS_100 - DFS_EE + 1) * 255.0f;
- float rx1 = rx_accum / (float)(DFS_100 - DFS_EE + 1) * 255.0f;
- float qsz = qsize_accum / 100.0f * 255.0f;
- tx_accum = rx_accum = sz_ctr = qsize_accum = 0;
- sLog->logLimitedInt(17, 0, 255, tx1);
- sLog->logLimitedInt(18, 0, 255, rx1);
- sLog->logUInt32(19, spi.getFIFOFaultCtr());
- sLog->logUInt32(20, averageCpuUtilization());
- sLog->logLimitedInt(21, 0, 255, qsz);
- }
- }
- Thread::sleep(1);
- }
-}
-
-int main()
-{
- sLog->start();
- printf("\n");
- Leds::set(0);
- Log::getInstance();
- sBoard->init();
-
- const std::vector<SingleSensor>& data = sBoard->debugGetSensors();
- int ctr = 0;
-
- Thread::create(fifoQueueSz, 1024);
- while (1)
- {
- for (const auto& s : data)
- {
- switch (s.data)
- {
- case DATA_VEC3:
- sLog->logSensorVec3(s.sensor, *(Vec3*)s.value);
- break;
- case DATA_FLOAT:
- sLog->logSensorFloat(s.sensor, *(float*)s.value);
- break;
- default:
- break;
- }
- }
-
- Thread::sleep(100);
- }
-
- return 0;
-}
diff --git a/old_examples/entrypoints/anakin/anakin-test-suite.cpp b/old_examples/entrypoints/anakin/anakin-test-suite.cpp
deleted file mode 100644
index 3499646a6d6eb3706432ce5ddd517343fa0dcd60..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/anakin-test-suite.cpp
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <sensors/FXAS21002.h>
-#include <sensors/MAX21105.h>
-#include <sensors/MPU9250.h>
-#include <sensors/MS580301BA07.h>
-//#include <sensors/Si7021.h>
-
-using namespace miosix;
-
-#define SENSOR(NAME, CSPORT, CSPIN) \
- typedef Gpio<GPIO##CSPORT##_BASE, CSPIN> CS_##NAME; \
- typedef ProtocolSPI<busSPI1, CS_##NAME> spi##NAME
-
-#define READ(NAME, ID) spi##NAME::read(ID)
-#define TEST(NAME, REG, REF) test_and_print(#NAME, REG, READ(NAME, REG), REF)
-
-#define ACCEL_ENDLESS_TEST
-
-// SPI1
-typedef Gpio<GPIOA_BASE, 5> GpioSck;
-typedef Gpio<GPIOA_BASE, 6> GpioMiso;
-typedef Gpio<GPIOA_BASE, 7> GpioMosi;
-typedef BusSPI<1, GpioMosi, GpioMiso, GpioSck> busSPI1;
-
-// clang-format off
-// Here's the list of SPI sensors that should be tested
-// | NAME | CSPORT | CSPIN |
-SENSOR(MPU9250, D, 13);
-SENSOR(FXAS21002, G, 10);
-SENSOR(MAX21105, E, 2);
-SENSOR(MAX31856, B, 11);
-SENSOR(LSM9DS0_G, G, 9);
-SENSOR(LSM9DS0_A, G, 11);
-SENSOR(LPS331AP, E, 4);
-SENSOR(MS580301BA07, B, 10);
-// clang-format on
-
-static const char mOK[] = "OK";
-static const char mKO[] = "FAIL";
-
-int num_ok = 0, num_fail = 0;
-
-void banner()
-{
- printf(
- "----------------------------------------------------------------------"
- "------\n"
- "d888888b d88888b .d8888. d888888b .d8888. db db d888888b d888888b "
- "d88888b\n"
- "`~~88~~' 88' 88' YP `~~88~~' 88' YP 88 88 `88' `~~88~~' "
- "88' \n"
- " 88 88ooooo `8bo. 88 `8bo. 88 88 88 88 "
- "88ooooo\n"
- " 88 88~~~~~ `Y8b. 88 `Y8b. 88 88 88 88 "
- "88~~~~~\n"
- " 88 88. db 8D 88 db 8D 88b d88 .88. 88 "
- "88. \n"
- " YP Y88888P `8888Y' YP `8888Y' ~Y8888P' Y888888P YP "
- "Y88888P\n"
- "----------------------------------------------------------------------"
- "------\n"
- "\n");
-}
-
-void test_and_print(const char* name, uint8_t reg, uint8_t test,
- uint8_t reference)
-{
- if (test == reference)
- ++num_ok;
- else
- ++num_fail;
- printf("[%13s] [REG 0x%02x]: 0x%02x -> [%s]\n", name, reg, test,
- (test == reference) ? mOK : mKO);
-}
-
-void assert_true(const char* name, const char* func, bool value)
-{
- if (value)
- ++num_ok;
- else
- ++num_fail;
-
- printf("[%13s] [FUNC %9s] -> [%s]\n", name, func, (value) ? mOK : mKO);
-}
-
-void test_max31856()
-{
- // Check if a bunch of register have the reference value
- TEST(MAX31856, 0x00, 0x00); // config 0
- TEST(MAX31856, 0x01, 0x03); // config 1
- TEST(MAX31856, 0x02, 0xFF); // mask
- TEST(MAX31856, 0x03, 0x7F); // hi fault
- TEST(MAX31856, 0x04, 0xc0); // lo fault
- TEST(MAX31856, 0x05, 0x7f); // lol
- TEST(MAX31856, 0x0F, 0x00); // fault status reg
-}
-
-void test_altimeter()
-{
- MS580301BA07<spiMS580301BA07> altiMS580;
-
- // Read and check different const registers
- TEST(MS580301BA07, 0xA4, READ(MS580301BA07, 0xA4));
- TEST(MS580301BA07, 0xAA, READ(MS580301BA07, 0xAA));
- TEST(MS580301BA07, 0xAC, READ(MS580301BA07, 0xAC));
- assert_true("MS580301BA07", "init()", altiMS580.init());
-}
-
-int main()
-{
- MAX21105<spiMAX21105> max21(MAX21105<spiMAX21105>::ACC_FS_2G,
- MAX21105<spiMAX21105>::GYRO_FS_500);
-
- banner();
- // Pausa per lasciare il tempo ai sensori di accendersi
- Thread::sleep(100);
-
- printf("Polling sensors...\n");
-
- // clang-format off
- // First check: compare sensors WHO_AM_I against the reference value
- TEST(MPU9250, 0x75, 0x71);
- TEST(FXAS21002, 0x0c, 0xd7);
- TEST(MAX21105, 0x20, 0xb4);
- TEST(LSM9DS0_G, 0x0f, 0xd4);
- TEST(LSM9DS0_A, 0x0f, 0x49);
- TEST(LPS331AP, 0x0f, 0xBB);
- // clang-format on
-
- test_max31856();
- test_altimeter();
-
- assert_true("MAX21105", "init()", max21.init());
-
- printf("---------------------\n");
- printf(
- "NUM TEST OK: %5d\n"
- "NUM TEST FAIL:%5d\n\n",
- num_ok, num_fail);
-
-#ifdef ACCEL_ENDLESS_TEST
- uint16_t cnt = 0;
- const Vec3* a = max21.accelDataPtr();
- const Vec3* g = max21.gyroDataPtr();
- const float* temp = max21.tempDataPtr();
- while (true)
- {
- max21.onSimpleUpdate();
-
- printf(
- "%05u[ACC %+5.2f,%+5.2f,%+5.2f] "
- "[GYR %+5.2f,%+5.2f,%+5.2f] "
- "[TMP %+5.2fC] \r",
- (uint16_t)(++cnt), a->getX(), a->getY(), a->getZ(), g->getX(),
- g->getY(), g->getZ(), *temp);
- Thread::sleep(10);
- }
-#endif
-
- // Bye.
- while (1)
- {
- Thread::sleep(1000);
- }
-}
diff --git a/old_examples/entrypoints/anakin/canbus-test.cpp b/old_examples/entrypoints/anakin/canbus-test.cpp
deleted file mode 100644
index 32c28396328d7505c5bf75e342e94d0daf0d6aad..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/canbus-test.cpp
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/canbus/CanManager.h>
-#include <drivers/canbus/CanSocket.h>
-#include <drivers/canbus/CanUtils.h>
-#include <sensors/MPU9250.h>
-
-using namespace std;
-using namespace miosix;
-
-#define CAN_PACKETID 0x49
-
-int main()
-{
- CanManager c(CAN1);
-
- canbus_init_t st = {
- CAN1, Mode::ALTERNATE, 9, {CAN1_RX0_IRQn, CAN1_RX1_IRQn}};
-
- c.addBus<GPIOA_BASE, 11, 12>(st);
- // canbus_init_t st2= {
- // CAN2, Mode::ALTERNATE, 9, {CAN2_RX0_IRQn,CAN2_RX1_IRQn}
- //};
- // c.addBus<GPIOB_BASE, 5, 6>(st2);
-
- CanBus *bus = c.getBus(0);
- CanSocket socket(CAN_PACKETID);
- char buf[64] = {0};
- socket.open(bus);
-
- printf("*** Ready ***\n");
-
- while (1)
- {
- const char *pkt = "TestMSG";
- bus->send(CAN_PACKETID, (const uint8_t *)pkt, strlen(pkt));
- socket.receive(buf, 64);
- printf("Recv pkt: '%s'\n", buf);
- Thread::sleep(250);
- }
-
- socket.close();
-}
diff --git a/old_examples/entrypoints/anakin/dma-lowlevel-test.cpp b/old_examples/entrypoints/anakin/dma-lowlevel-test.cpp
deleted file mode 100644
index 9baf3ebdb95572bcc3afe9ed4910ede05c3a60db..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/dma-lowlevel-test.cpp
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/spi/SensorSpi.h>
-#include <sensors/FXAS21002.h>
-#include <sensors/LPS331AP.h>
-#include <sensors/MAX21105.h>
-#include <sensors/MPU9250.h>
-#include <sensors/MS580301BA07.h>
-#include <sensors/SensorSampling.h>
-#include <sensors/iNemo.h>
-
-using namespace miosix;
-
-typedef Gpio<GPIOA_BASE, 5> GpioSck;
-typedef Gpio<GPIOA_BASE, 6> GpioMiso;
-typedef Gpio<GPIOA_BASE, 7> GpioMosi;
-typedef BusSPI<1, GpioMosi, GpioMiso, GpioSck> busSPI1;
-
-typedef ProtocolSPI<busSPI1, Gpio<GPIOD_BASE, 13>> spiMPU9250;
-typedef ProtocolSPI<busSPI1, Gpio<GPIOG_BASE, 11>> spiINEMOA;
-typedef ProtocolSPI<busSPI1, Gpio<GPIOG_BASE, 9>> spiINEMOG;
-
-typedef MPU9250<spiMPU9250> mpu_t;
-typedef iNEMOLSM9DS0<spiINEMOG, spiINEMOA> inemo_t;
-
-int main()
-{
- puts("\n\n---");
- spiMPU9250::init();
- spiINEMOA::init();
- spiINEMOG::init();
- auto& spi = SPIDriver::instance();
-
- inemo_t inemo(inemo_t::ACC_FS_16G, inemo_t::GYRO_FS_245,
- inemo_t::COMPASS_FS_2);
-
- if (inemo.init() == false)
- {
- puts("init failed");
- }
-
- auto req = inemo.buildDMARequest();
- auto sample = [&]()
- {
- if (spi.transaction(req) == false)
- puts("DMA error");
- for (auto& r : req)
- {
- inemo.onDMAUpdate(r);
- printf("ID: %d --> ", r.id());
- auto& resp = r.readResponseFromPeripheral();
- memDump(resp.data(), resp.size());
- }
- };
-
- for (int i = 0; i < 2; i++)
- {
- Thread::sleep(20);
- sample();
- }
-
- for (;;)
- {
- getchar();
- sample();
- }
-}
diff --git a/old_examples/entrypoints/anakin/test-busfault.cpp b/old_examples/entrypoints/anakin/test-busfault.cpp
deleted file mode 100644
index db743d9c73afd3b1234f576965bb78167a3b7af3..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/test-busfault.cpp
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-
-using namespace miosix;
-
-void busfault(void *useless)
-{
- printf("If you can read this, Mr. BusFault is not here.\n");
-}
-
-int main()
-{
- Thread::create(busfault, 1024, miosix::MAIN_PRIORITY, NULL);
- while (1)
- Thread::sleep(10);
- return 0;
-}
diff --git a/old_examples/entrypoints/anakin/test-scheduler.cpp b/old_examples/entrypoints/anakin/test-scheduler.cpp
deleted file mode 100644
index 713696a53ac6a3952aa7cefda3c18c5c6972842c..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/test-scheduler.cpp
+++ /dev/null
@@ -1,60 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Matteo Piazzolla, Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/stm32f2_f4_i2c.h>
-#include <events/Scheduler.h>
-
-using namespace miosix;
-
-template <typename P, unsigned N>
-void blinker()
-{
- if (P::value())
- P::low();
- else
- P::high();
- delayMs(2);
-}
-
-int main()
-{
- sEventScheduler->start();
- // Thread *ledTh=Thread::create(supercar,STACK_MIN);
-
- sEventScheduler->add(blinker<leds::led9, 100>, 100, "task100");
- sEventScheduler->add(blinker<leds::led8, 200>, 200, "task200");
- sEventScheduler->add(blinker<leds::led7, 500>, 500, "task500");
- sEventScheduler->add(blinker<leds::led6, 1000>, 1000, "task1000");
- sEventScheduler->add(blinker<leds::led5, 50>, 50, "task50");
- for (;;)
- {
- Thread::sleep(1000);
- auto result = sEventScheduler->getTaskStats();
- printf("--- begin ---\n");
- printf("%u tasks\n", result.size());
- for (auto& it : result)
- printf("Name: %s\n", it.name.c_str());
- printf("--- end ---\n");
- }
-}
diff --git a/old_examples/entrypoints/anakin/test_ethernet.cpp b/old_examples/entrypoints/anakin/test_ethernet.cpp
deleted file mode 100644
index 45b34fad938910ecc4757fd8bc229df703035751..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/test_ethernet.cpp
+++ /dev/null
@@ -1,74 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/ethernet/UdpManager.h>
-
-#include <string>
-
-using namespace miosix;
-using namespace std;
-
-int main()
-{
- uint8_t ipAddr[] = {192, 168, 1, 30}; // Device's IP address
- uint8_t mask[] = {255, 255, 255, 0}; // Subnet mask
- uint8_t destIp[] = {192, 168, 1, 180}; // Destination IP address
-
- char message[] = "message from the hell...\n";
-
- W5200& eth = W5200::instance();
- eth.setIpAddress(ipAddr);
- eth.setSubnetMask(mask);
-
- auto udp = Singleton<UdpManager>::getInstance();
-
- udp->setTxPort(1234);
- udp->setRxPort(1235);
-
- int counter = 0;
-
- while (1)
- {
- int ncar = sprintf(message, "Hello gumby n° %d!\n", counter);
- udp->sendPacketTo(destIp, 2020, (void*)message, ncar);
- counter++;
-
- if (udp->newReceivedPackets())
- {
-
- size_t pktSiz = udp->recvPacketSize() + 1;
- uint8_t buffer[pktSiz];
- memset(buffer, 0x00, pktSiz);
- uint8_t sip[4] = {0};
- uint16_t sport = 0;
-
- udp->readPacket(sip, sport, buffer);
- printf("received %s from %d.%d.%d.%d:%d\n\n", buffer, sip[0],
- sip[1], sip[2], sip[3], sport);
- }
-
- Thread::sleep(200);
- }
-
- return 0;
-}
diff --git a/old_examples/entrypoints/anakin/test_i2c.cpp b/old_examples/entrypoints/anakin/test_i2c.cpp
deleted file mode 100644
index dc9dcdccdee9073a61746f2a8c3879c488856efc..0000000000000000000000000000000000000000
--- a/old_examples/entrypoints/anakin/test_i2c.cpp
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/Leds.h>
-#include <drivers/stm32f2_f4_i2c.h>
-#include <sensors/MPL3115.h>
-// #include <util/software_i2c.h>
-
-using namespace miosix;
-
-int main()
-{
- sensors::sda::mode(Mode::ALTERNATE_OD);
- sensors::sda::alternateFunction(4);
- sensors::scl::mode(Mode::ALTERNATE_OD);
- sensors::scl::alternateFunction(4);
-
- MPL3115<ProtocolI2C<I2C1Driver>> baro;
-
- printf("%d\n", baro.selfTest() ? 1 : 0);
- baro.setMode(baro.MODE_ALTIMETER);
- baro.setOversampleRatio(128);
-
- while (1)
- {
- baro.onSimpleUpdate();
- printf("press %f, temp %f, alt %f\n", *(baro.pressureDataPtr()),
- *(baro.tempDataPtr()), *(baro.altitudeDataPtr()));
-
- Thread::sleep(1000);
- }
-
- return 0;
-}
diff --git a/old_examples/shared/Common.h b/old_examples/shared/Common.h
deleted file mode 100644
index af1815a12ee74f68f6301d8285ed9157279a4bc7..0000000000000000000000000000000000000000
--- a/old_examples/shared/Common.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/timer/TimestampTimer.h>
-#include <interfaces/endianness.h>
-#include <kernel/scheduler/scheduler.h>
-#include <miosix.h>
-#include <pthread.h>
-#include <utils/Constants.h>
-#include <utils/Debug.h>
-
-#include <array>
-#include <cassert>
-#include <cstdint>
-#include <cstdio>
-#include <cstring>
-#include <map>
-#include <memory>
-#include <set>
-#include <vector>
-
-#define UNUSED(x) (void)(x)
diff --git a/old_examples/shared/diagnostic/FaultCounter.h b/old_examples/shared/diagnostic/FaultCounter.h
deleted file mode 100644
index 5d552b688052cc1926d43cae9d8ddcfafb85d819..0000000000000000000000000000000000000000
--- a/old_examples/shared/diagnostic/FaultCounter.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-#include <Singleton.h>
-#include <diagnostic/FaultCounterData.h>
-
-namespace Boardcore
-{
-
-class FaultCounterMgr : public Singleton<FaultCounterMgr>
-{
- friend class Singleton<FaultCounterMgr>;
-
-public:
- ~FaultCounterMgr() {}
-
- void Increment(const Fault id)
- {
- using FaultCounterData::FaultToCategory;
-
- miosix::FastInterruptDisableLock dLock;
- const uint32_t numId = static_cast<uint32_t>(id);
- const uint32_t catId = FaultToCategory[numId];
- mCounters[numId]++;
- mCategories[catId]++;
-
- mFaultTriggered[numId] = 1;
- mCategoryTriggered[catId] = 1;
- }
-
- inline std::pair<const uint8_t *, size_t> GetFaultCounters() const
- {
- return std::make_pair(mCounters, Fault_SIZE);
- }
-
- inline std::pair<const uint8_t *, size_t> GetCategoryCounters() const
- {
- using FaultCounterData::FaultCategory_SIZE;
- return std::make_pair(mCategories, FaultCategory_SIZE);
- }
-
-private:
- uint8_t mCounters[Fault_SIZE];
- uint8_t mCategories[FaultCounterData::FaultCategory_SIZE];
-
- std::vector<bool> mFaultTriggered;
- std::vector<bool> mCategoryTriggered;
-
- FaultCounterMgr()
- {
- memset(mCounters, 0, sizeof(mCounters));
- memset(mCategories, 0, sizeof(mCategories));
-
- // TODO: static bitmap?
- mFaultTriggered.resize(Fault_SIZE);
- mCategoryTriggered.resize(FaultCounterData::FaultCategory_SIZE);
- }
-};
-
-#define sFaultCounterMgr FaultCounterMgr::getInstance()
-
-} // namespace Boardcore
diff --git a/old_examples/shared/diagnostic/FaultCounterData.h b/old_examples/shared/diagnostic/FaultCounterData.h
deleted file mode 100644
index b5638d43b56f0fee911ea0bce0389ae713061d16..0000000000000000000000000000000000000000
--- a/old_examples/shared/diagnostic/FaultCounterData.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/*
- ******************************************************************************
- * THIS FILE IS AUTOGENERATED. DO NOT EDIT. *
- ******************************************************************************
- */
-
-// CSV File: data/fault_list.csv
-// SHA1 of CSV File: e9a518af53ac91c2e57142fda140689918338c66
-// Autogen date: 2017-09-16 21:53:44.208079
-
-#pragma once
-
-#include <cstdint>
-
-namespace Boardcore
-{
-
-enum class Fault
-{
- F_ANAKIN_TEST_FAULT = 0,
-};
-const std::size_t Fault_SIZE = 1;
-
-namespace FaultCounterData
-{
-
-enum class FaultCategory
-{
- ANAKIN = 0,
-};
-const std::size_t FaultCategory_SIZE = 1;
-
-// Usage: categoryID = FaultCounter::FaultToCategory[faultID];
-const uint32_t FaultToCategory[] = {
- 0,
-}; /* CategoryMapping */
-
-} // namespace FaultCounterData
-
-} // namespace Boardcore
diff --git a/old_examples/shared/drivers/AD7994/AD7994.h b/old_examples/shared/drivers/AD7994/AD7994.h
deleted file mode 100644
index 0528d948835c925023c213af91cde046254b6b45..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/AD7994/AD7994.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright (c) 2018-2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <miosix.h>
-#include <sensors/Sensor.h>
-#include <stdint.h>
-#include <utils/Debug.h>
-
-#include "AD7994Data.h"
-
-/**
- * Driver for the AD7994 Analog Digital Converter
- * CLASS INVARIANT: The address pointer register points to the conversion result
- * register.
- * This is done for performance reasons: we don't want to write to the
- * address pointer register each time we perform a conversion (eg multiple times
- * per second)
- */
-template <typename BusI2C, typename BusyPin, typename CONVST>
-class AD7994 : public Sensor
-{
-public:
- enum class Channel : uint8_t
- {
- CH1 = 1,
- CH2,
- CH3,
- CH4
- };
-
- /**
- * @brief AD7994 constructor. Invariant is respected as the sensor powers up
- * pointing at the conversion result register.
- *
- * @param i2c_address I2C address of the AD7994
- */
- AD7994(uint8_t i2c_address)
- : i2c_address(i2c_address), enabled_channels{0, 0, 0, 0}
- {
- }
-
- ~AD7994() {}
-
- /**
- * @brief Initialize the sensor writing the configuration register
- * This driver is designed to work in Mode 1
- * The configuration register is set to enable the BUSY pin, I2C filtering
- * and no enabled channels.
- * @return true If the sensor was configured successfully
- */
- bool init() override
- {
- uint8_t config_reg_value = 0x0A; // 0b00001010
-
- // Write the configuration register
- BusI2C::write(i2c_address, REG_CONFIG, &config_reg_value, 1);
-
- uint8_t read_config_reg_value;
-
- // Read back the value
- BusI2C::directRead(i2c_address, &read_config_reg_value, 1);
- // BusI2C::read(i2c_address, REG_CONFIG, &read_config_reg_value, 1);
-
- pointToConversionResult();
-
- return read_config_reg_value == config_reg_value;
- }
-
- void enableChannel(Channel channel)
- {
- uint8_t ch = static_cast<uint8_t>(channel);
- enabled_channels[ch - 1] = true;
-
- uint8_t config_reg_value;
- BusI2C::read(i2c_address, REG_CONFIG, &config_reg_value, 1);
-
- // Update the config register value
- uint8_t channel_reg = 0;
- for (int i = 0; i < 4; i++)
- {
- if (enabled_channels[i])
- channel_reg |= 1 << i;
- }
- config_reg_value = (config_reg_value & 0x0F) | channel_reg << 4;
-
- BusI2C::write(i2c_address, REG_CONFIG, &config_reg_value, 1);
-
- pointToConversionResult();
- }
-
- void disableChannel(Channel channel)
- {
- uint8_t ch = static_cast<uint8_t>(channel);
- enabled_channels[ch - 1] = false;
-
- uint8_t channel_reg = 0;
- for (int i = 0; i < 4; i++)
- {
- if (enabled_channels[i])
- channel_reg |= 1 << i;
- }
-
- uint8_t config_reg_value;
- BusI2C::read(i2c_address, REG_CONFIG, &config_reg_value, 1);
-
- // Update the config register value
- config_reg_value = (config_reg_value & 0x0F) | channel_reg << 4;
-
- BusI2C::write(i2c_address, REG_CONFIG, &config_reg_value, 1);
-
- pointToConversionResult();
- }
-
- /**
- * @brief Triggers a new ADC conversion on the enabled channels and reads
- * the value of the conversion register.
- * TODO: Check how to sample multiple channels.
- * @return true If the conversion was successful on all enabled channels
- */
- bool onSimpleUpdate() override
- {
- uint8_t data[2];
-
- for (int i = 0; i < 4; i++)
- {
- if (enabled_channels[i])
- {
- // Trigger a conversion
- CONVST::high();
- miosix::delayUs(3);
- CONVST::low();
- // Wait for the conversion to complete
- miosix::delayUs(2);
-
- BusI2C::directRead(i2c_address, data, 2);
-
- samples[i] = decodeConversion(data);
- samples[i].timestamp = miosix::getTick();
- }
- }
-
- return true;
- }
-
- bool selfTest() { return true; }
-
- AD7994Sample getLastSample(Channel channel)
- {
- uint8_t ch = static_cast<uint8_t>(channel);
- return samples[ch - 1];
- }
-
-private:
- // Address of the AD7994 on the I2C bus
- const uint8_t i2c_address;
-
- // The 4 LSBs indicate where the corresponding channel is enabled or not.
- bool enabled_channels[4];
-
- /**
- * @brief Writes the conversion register address to the address pointer
- * register in order to restore the class invariant.
- */
- void pointToConversionResult()
- {
- uint8_t reg_addr = REG_CONVERSION_RESULT;
- BusI2C::directWrite(i2c_address, ®_addr, 1);
- }
-
- /**
- * @brief Decodes the 2 bytes of the conversion register into an
- * AD7994Sample structure
- *
- * @param data_ptr Pointer to the first of the 2 bytes of the conversione
- * register
- * @return AD7994Sample
- */
- AD7994Sample decodeConversion(uint8_t* data_ptr)
- {
- uint16_t conv_reg =
- static_cast<uint16_t>((data_ptr[0]) << 8) + data_ptr[1];
-
- AD7994Sample out;
- out.value = conv_reg & 0x0FFF;
- out.channel_id = (static_cast<uint8_t>(conv_reg >> 12) & 0x03) + 1;
- out.alert_flag = static_cast<bool>(conv_reg >> 15);
-
- return out;
- }
-
- enum Registers : uint8_t
- {
- REG_CONVERSION_RESULT = 0x00,
- REG_ALERT_STATUS = 0x01,
- REG_CONFIG = 0x02,
- };
-
- AD7994Sample samples[4];
-};
diff --git a/old_examples/shared/drivers/AD7994/AD7994Data.h b/old_examples/shared/drivers/AD7994/AD7994Data.h
deleted file mode 100644
index 4757f68c99a39b0fdbb93d733214a1ce7046cbd9..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/AD7994/AD7994Data.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <cstdint>
-#include <ostream>
-#include <string>
-
-struct AD7994Sample
-{
- long long timestamp;
-
- uint8_t channel_id; // [1-4]
- bool alert_flag;
- uint16_t value;
-
- // Functions used to deserialize the binary logs into csv files
-
- static std::string header() { return "timestamp,ch_id,value,alert_flag\n"; }
-
- void print(std::ostream& os) const
- {
- os << timestamp << "," << channel_id << "," << value << ","
- << (int)alert_flag << "\n";
- }
-};
diff --git a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.cpp b/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.cpp
deleted file mode 100644
index 1554a2c73985b42e113ea6cdfb67173f6df0a765..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.cpp
+++ /dev/null
@@ -1,247 +0,0 @@
-/* Copyright (c) 2018 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "IsbProtocol_serial2.h"
-
-using namespace std;
-using namespace miosix;
-
-typedef Gpio<GPIOA_BASE, 2> u2tx;
-typedef Gpio<GPIOA_BASE, 3> u2rx;
-typedef Gpio<GPIOA_BASE, 1> u2rts;
-
-void __attribute__((weak)) USART2_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z11Serial2_Irqv");
- restoreContext();
-}
-
-void __attribute__((used)) Serial2_Irq()
-{
- auto inst = IsbProtocol_serial2::instance();
- inst.IRQHandler();
-}
-
-IsbProtocol_serial2::IsbProtocol_serial2()
-{
- {
- FastInterruptDisableLock dLock;
- RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
- RCC_SYNC();
-
- u2tx::mode(Mode::ALTERNATE);
- u2tx::alternateFunction(7);
-
-#ifdef _ARCH_CORTEXM3_STM32F1
- u2rx::mode(Mode::INPUT);
-#else
- u2rx::mode(Mode::ALTERNATE);
- u2rx::alternateFunction(7);
-#endif
-
- u2rts::mode(Mode::OUTPUT);
- u2rts::low();
- }
-
- /*** USART 2 configuration ***/
- // Enable parity, 9 bit frame length, no parity,
- // generate interrupt in case a new byte is received
- USART2->CR1 |= USART_CR1_M | USART_CR1_RXNEIE | USART_CR1_TE // enable tx
- | USART_CR1_RE; // enable rx
-
- // CR2 and CR3 registers are left untouched since their default values are
- // OK
-
- NVIC_SetPriority(USART2_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(USART2_IRQn);
- NVIC_EnableIRQ(USART2_IRQn);
-}
-
-IsbProtocol_serial2::~IsbProtocol_serial2()
-{
- FastInterruptDisableLock dLock;
- RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
- RCC_SYNC();
-}
-
-void IsbProtocol_serial2::IRQHandler()
-{
- if (USART2->SR & USART_SR_RXNE)
- {
- /* This protocol uses 9 bit long usart frames.
- * The STM32's data register is 9 bit long, so the
- * lower 8 bits are used to transport the data byte and
- * the MSB - the 9th bit - is used to select between
- * data or address byte
- */
- uint16_t byte = USART->DR;
-
- uint16_t checkMask = 0x100 | nodeAddress;
- if (byte == checkMask)
- {
- rxStatus.rxIndex = 0;
- rxStatus.rxInProgress = true;
- rxStatus.dataLenPending = true;
-
- rxBuf[rxStatus.rxIndex] = byte & 0xFF; // strip away the 9th byte
- rxStatus.rxIndex++;
- }
- else if (rxStatus.rxInProgress)
- {
- if (rxStatus.dataLenPending)
- {
- // Second byte in the packet is the data len field. To this
- // value we have to add 4 bytes: address, data len and two bytes
- // of CRC
- rxStatus.packetSize = (byte & 0xFF) + 4;
- rxStatus.dataLenPending = false;
- }
-
- rxBuf[rxStatus.rxIndex] = byte & 0xFF;
- rxStatus.rxIndex++;
-
- if (rxStatus.rxIndex >= rxStatus.packetSize)
- {
- rxStatus.rxInProgress = false;
- }
- }
- }
-}
-
-size_t IsbProtocol_serial2::newDataAvailable()
-{
- if ((rxStatus.rxInProgress == true) || (rxStatus.packetSize = 0))
- {
- return 0;
- }
-
- // we pass packetSize - 2 in order to avoid including in the CRC calculation
- // the CRC value inserted from the sender
- uint16_t crc = CRC16(rxBuf, rxStatus.packetSize - 2);
- uint16_t pktCrc =
- (rxBuf[rxStatus.packetSize - 2] << 8) | rxBuf[rxStatus.packetSize - 1];
-
- // Packet length check: the value contained in the second byte must be
- // equal to the number of bytes received minus 4
- bool checkLen = (rxBuf[1] == (rxStatus.packetSize - 4)) ? true : false;
-
- if ((crc != pktCrc) || (!checkLen))
- {
- rxStatus.packetSize = 0; // packet is corrupt, discard it
- return 0;
- }
-
- // Return length of the data field
- return rxBuf[1];
-}
-
-void IsbProtocol_serial2::getData(uint8_t* buffer)
-{
- std::memcpy(buffer, rxBuf[2], rxBuf[1]);
-}
-
-void IsbProtocol_serial2::sendData(uint8_t dstAddr, uint8_t* data, size_t len)
-{
- // packet too long
- if (len > 0xFF)
- {
- return;
- }
-
- txBuf[0] = dstAddr;
- txBuf[1] = len;
- std::memcpy(txBuf[2], data, len);
-
- // Include in CRC also address and data len field
- uint16_t crc = CRC16(txBuf, len + 2);
-
- size_t crcBegin = len + 2;
- txBuf[crcBegin] = crc >> 8;
- txBuf[crcBegin + 1] = crc & 0xFF;
-
- u2rts::high();
-
- for (size_t i = 0; i < len + 4; i++)
- {
- // the first byte is the address, so it has to be sent with the 9th bit
- // set to 1
- if (i == 0)
- {
- USART2->DR = txBuf[i] | 0x100;
- }
- else
- {
- USART2->DR = txBuf[i];
- }
-
- // Wait until tx buffer is empty again
- while ((USART2->SR & USART_SR_TXE) == 0)
- ;
- }
-
- u2rts::low();
-}
-
-void IsbProtocol_serial2::setBaud(uint32_t baud)
-{
- uint32_t busFreq = SystemCoreClock;
-
-#ifdef _ARCH_CORTEXM3_STM32F1
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 8) & 0x3) + 1);
- }
-#else
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 10) & 0x3) + 1);
- }
-#endif
-
- uint32_t quot = 2 * busFreq / baud; // 2*freq for round to nearest
- USART2->BRR = quot / 2 + (quot & 1);
-}
-
-void IsbProtocol_serial2::setNodeAddress(uint8_t address)
-{
- nodeAddress = address;
-}
-
-uint16_t IsbProtocol_serial2::CRC16(uint8_t* data, size_t len)
-{
- uint16_t crc = 0xFFFF;
- for (size_t i = 0; i < len; i++)
- {
- uint16_t x = ((crc >> 8) ^ data[i]) & 0xff;
- x ^= x >> 4;
- crc = (crc << 8) ^ (x << 12) ^ (x << 5) ^ x;
- }
-
- return crc;
-}
-
-IsbProtocol_serial2& IsbProtocol_serial2::instance()
-{
- static IsbProtocol_serial2 inst;
- return inst;
-}
diff --git a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.h b/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.h
deleted file mode 100644
index 11e8aff4a7429cf18b02fb3e87b8e4972696f964..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial2.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <stddef.h>
-
-#include <cstdint>
-#include <cstdio>
-#include <cstring>
-
-#include "miosix.h"
-
-/* This class is a kind of driver to be used to excange data between the
- * stormtrooper master and the other stormtrooper slave boards through the
- * RS485 lines. The communication model is this: all the boards are connected
- * on the same bus and each board has a unique node address. To avoid conflicts,
- * the master is the only device on the bus that can initiate a communication;
- * thus, to communicate with a specific slave, the master sends a packet
- * containing the targeted slave address and the data and then waits for the
- * response (if expected). Owing to this model, if two stormtrooper slaves need
- * to exchange data they have to rely on the stormtrooper master acting as a
- * router between them.
- *
- * The packet structure is this:
- *
- * +------+-----+------+-----+
- * | addr | len | data | CRC |
- * +------+-----+------+-----+
- *
- * -> addr: target node address, 8 bit
- * -> len: lenght of the data field, 8 bit
- * -> data: data bytes, up to 255
- * -> CRC: 16 bit field calculated on addr, len and data using the ccitt CRC16
- * formula
- *
- * On the bus data is sent using 9 bit long frames with one stop bit. If the 9th
- * bit is set to 1 means that the byte received is an address byte and so a
- * packet is incoming
- *
- *
- * Here is a sample code about this class' usage:
- *
- * auto comm = IsbProtocol_serial2::instance();
- *
- * comm.setBaud(9600); //set baud to 9600 bps
- * comm.setNodeAddress(0xAB); //set node ID
- *
- * // this to check if new data arrived and to copy the bytes into a local
- * buffer
- *
- * uint8_t rx_buf[256];
- *
- * if(comm.newDataAvailable() > 0)
- * {
- * comm.getData(rx_buf);
- * }
- *
- * // this to send data
- *
- * uint8_t tx_buf[] = "Some data for you! :)";
- *
- * comm.sendData(0xE0, tx_buf, sizeof(tx_buf));
- *
- */
-
-class IsbProtocol_serial2
-{
-public:
- /**
- * @return singleton intance of the class
- */
- static IsbProtocol_serial2& instance();
-
- ~IsbProtocol_serial2();
-
- /**
- * Set the USART baud rate.
- * @param baud baud rate to be set
- */
- void setBaud(uint32_t baud);
-
- /**
- * Set the node's address in the network
- */
- void setNodeAddress(uint8_t address);
-
- /**
- * @return number of payload data bytes received or 0 if none received
- */
- size_t newDataAvailable();
-
- /**
- * Get the latest payload data received.
- * @param buffer pointer to buffer in which copy the new data, it must have
- * dimension greater than or equal to the value returned by
- * newDataAvailable()
- */
- void getData(uint8_t* buffer);
-
- /**
- * Send a packet, this function blocks until all data is sent
- *
- * @param dstAddr destination node address
- * @param data pointer to a buffer containing the payload data
- * @param len payload size in bytes
- */
- void sendData(uint8_t dstAddr, uint8_t* data, size_t len);
-
- /**
- * Interrupt handler. DON'T CALL IT ANYWHERE!!
- */
- void IRQHandler();
-
-private:
- uint8_t rxBuf[300];
- struct R
- {
- uint16_t packetSize;
- uint16_t rxIndex;
- bool rxInProgress;
- bool dataLenPending;
- } rxStatus;
-
- uint8_t txBuf[300];
- uint8_t nodeAddress;
-
- uint16_t CRC16(uint8_t* data, size_t len);
-
- IsbProtocol_serial2();
- IsbProtocol_serial2(const IsbProtocol_serial2& other);
- IsbProtocol_serial2& operator=(const IsbProtocol_serial2& other);
- bool operator==(const IsbProtocol_serial2& other);
-};
diff --git a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.cpp b/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.cpp
deleted file mode 100644
index 68bb3f7905c9876a424a7cc38a1d13a0d52f66dc..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.cpp
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- * Inter Stormtrooper Boards communication protocol through STM32's
- * USART3 interface
- *
- * Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
- */
-
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "IsbProtocol_serial3.h"
-
-using namespace std;
-using namespace miosix;
-
-typedef Gpio<GPIOB_BASE, 10> u3tx;
-typedef Gpio<GPIOB_BASE, 11> u3rx;
-typedef Gpio<GPIOB_BASE, 14> u3rts;
-
-void __attribute__((weak)) USART3_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z11Serial3_Irqv");
- restoreContext();
-}
-
-void __attribute__((used)) Serial3_Irq()
-{
- auto inst = IsbProtocol_serial3::instance();
- inst.IRQHandler();
-}
-
-IsbProtocol_serial3::IsbProtocol_serial3()
-{
- {
- FastInterruptDisableLock dLock;
- RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
- RCC_SYNC();
-
- u3tx::mode(Mode::ALTERNATE);
- u3tx::alternateFunction(7);
-
-#ifdef _ARCH_CORTEXM3_STM32F1
- u3rx::mode(Mode::INPUT);
-#else
- u3rx::mode(Mode::ALTERNATE);
- u3rx::alternateFunction(7);
-#endif
-
- u3rts::mode(Mode::OUTPUT);
- u3rts::low();
- }
-
- /*** USART 3 configuration ***/
- // Enable parity, 9 bit frame length, no parity,
- // generate interrupt in case a new byte is received
- USART3->CR1 |= USART_CR1_M | USART_CR1_RXNEIE | USART_CR1_TE // enable tx
- | USART_CR1_RE; // enable rx
-
- // CR2 and CR3 registers are left untouched since their default values are
- // OK
-
- NVIC_SetPriority(USART3_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(USART3_IRQn);
- NVIC_EnableIRQ(USART3_IRQn);
-}
-
-IsbProtocol_serial3::~IsbProtocol_serial3()
-{
- FastInterruptDisableLock dLock;
- RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
- RCC_SYNC();
-}
-
-void IsbProtocol_serial3::IRQHandler()
-{
- if (USART3->SR & USART_SR_RXNE)
- {
- /* This protocol uses 9 bit long usart frames.
- * The STM32's data register is 9 bit long, so the
- * lower 8 bits are used to transport the data byte and
- * the MSB - the 9th bit - is used to select between
- * data or address byte
- */
- uint16_t byte = USART->DR;
-
- uint16_t checkMask = 0x100 | nodeAddress;
- if (byte == checkMask)
- {
- rxStatus.rxIndex = 0;
- rxStatus.rxInProgress = true;
- rxStatus.dataLenPending = true;
-
- rxBuf[rxStatus.rxIndex] = byte & 0xFF; // strip away the 9th byte
- rxStatus.rxIndex++;
- }
- else if (rxStatus.rxInProgress)
- {
- if (rxStatus.dataLenPending)
- {
- // Second byte in the packet is the data len field. To this
- // value we have to add 4 bytes: address, data len and two bytes
- // of CRC
- rxStatus.packetSize = (byte & 0xFF) + 4;
- rxStatus.dataLenPending = false;
- }
-
- rxBuf[rxStatus.rxIndex] = byte & 0xFF;
- rxStatus.rxIndex++;
-
- if (rxStatus.rxIndex >= rxStatus.packetSize)
- {
- rxStatus.rxInProgress = false;
- }
- }
- }
-}
-
-size_t IsbProtocol_serial3::newDataAvailable()
-{
- if ((rxStatus.rxInProgress == true) || (rxStatus.packetSize = 0))
- {
- return 0;
- }
-
- // we pass packetSize - 2 in order to avoid including in the CRC calculation
- // the CRC value inserted from the sender
- uint16_t crc = CRC16(rxBuf, rxStatus.packetSize - 2);
- uint16_t pktCrc =
- (rxBuf[rxStatus.packetSize - 2] << 8) | rxBuf[rxStatus.packetSize - 1];
-
- // Packet length check: the value contained in the second byte must be
- // equal to the number of bytes received minus 4
- bool checkLen = (rxBuf[1] == (rxStatus.packetSize - 4)) ? true : false;
-
- if ((crc != pktCrc) || (!checkLen))
- {
- rxStatus.packetSize = 0; // packet is corrupt, discard it
- return 0;
- }
-
- // Return length of the data field
- return rxBuf[1];
-}
-
-void IsbProtocol_serial3::getData(uint8_t* buffer)
-{
- std::memcpy(buffer, rxBuf[2], rxBuf[1]);
-}
-
-void IsbProtocol_serial3::sendData(uint8_t dstAddr, uint8_t* data, size_t len)
-{
- // packet too long
- if (len > 0xFF)
- {
- return;
- }
-
- txBuf[0] = dstAddr;
- txBuf[1] = len;
- std::memcpy(txBuf[2], data, len);
-
- // Include in CRC also address and data len field
- uint16_t crc = CRC16(txBuf, len + 2);
-
- size_t crcBegin = len + 2;
- txBuf[crcBegin] = crc >> 8;
- txBuf[crcBegin + 1] = crc & 0xFF;
-
- u3rts::high();
-
- for (size_t i = 0; i < len + 4; i++)
- {
- // the first byte is the address, so it has to be sent with the 9th bit
- // set to 1
- if (i == 0)
- {
- USART3->DR = txBuf[i] | 0x100;
- }
- else
- {
- USART3->DR = txBuf[i];
- }
-
- // Wait until tx buffer is empty again
- while ((USART3->SR & USART_SR_TXE) == 0)
- ;
- }
-
- u3rts::low();
-}
-
-void IsbProtocol_serial3::setBaud(uint32_t baud)
-{
- uint32_t busFreq = SystemCoreClock;
-
-#ifdef _ARCH_CORTEXM3_STM32F1
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 8) & 0x3) + 1);
- }
-#else
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 10) & 0x3) + 1);
- }
-#endif
-
- uint32_t quot = 2 * busFreq / baud; // 2*freq for round to nearest
- USART3->BRR = quot / 2 + (quot & 1);
-}
-
-void IsbProtocol_serial3::setNodeAddress(uint8_t address)
-{
- nodeAddress = address;
-}
-
-uint16_t IsbProtocol_serial3::CRC16(uint8_t* data, size_t len)
-{
- uint16_t crc = 0xFFFF;
- for (size_t i = 0; i < len; i++)
- {
- uint16_t x = ((crc >> 8) ^ data[i]) & 0xff;
- x ^= x >> 4;
- crc = (crc << 8) ^ (x << 12) ^ (x << 5) ^ x;
- }
-
- return crc;
-}
-
-IsbProtocol_serial3& IsbProtocol_serial3::instance()
-{
- static IsbProtocol_serial3 inst;
- return inst;
-}
diff --git a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.h b/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.h
deleted file mode 100644
index 4e762fa2c1fb70159245b45d5670983125cbbbff..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ISB_protocol/IsbProtocol_serial3.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <stddef.h>
-
-#include <cstdint>
-#include <cstdio>
-#include <cstring>
-
-#include "miosix.h"
-
-/* This class is a kind of driver to be used to excange data between the
- * stormtrooper master and the other stormtrooper slave boards through the
- * RS485 lines. The communication model is this: all the boards are connected
- * on the same bus and each board has a unique node address. To avoid conflicts,
- * the master is the only device on the bus that can initiate a communication;
- * thus, to communicate with a specific slave, the master sends a packet
- * containing the targeted slave address and the data and then waits for the
- * response (if expected). Owing to this model, if two stormtrooper slaves need
- * to exchange data they have to rely on the stormtrooper master acting as a
- * router between them.
- *
- * The packet structure is this:
- *
- * +------+-----+------+-----+
- * | addr | len | data | CRC |
- * +------+-----+------+-----+
- *
- * -> addr: target node address, 8 bit
- * -> len: lenght of the data field, 8 bit
- * -> data: data bytes, up to 255
- * -> CRC: 16 bit field calculated on addr, len and data using the ccitt CRC16
- * formula
- *
- * On the bus data is sent using 9 bit long frames with one stop bit. If the 9th
- * bit is set to 1 means that the byte received is an address byte and so a
- * packet is incoming
- *
- *
- * Here is a sample code about this class' usage:
- *
- * auto comm = IsbProtocol_serial2::instance();
- *
- * comm.setBaud(9600); //set baud to 9600 bps
- * comm.setNodeAddress(0xAB); //set node ID
- *
- * // this to check if new data arrived and to copy the bytes into a local
- * buffer
- *
- * uint8_t rx_buf[256];
- *
- * if(comm.newDataAvailable() > 0)
- * {
- * comm.getData(rx_buf);
- * }
- *
- * // this to send data
- *
- * uint8_t tx_buf[] = "Some data for you! :)";
- *
- * comm.sendData(0xE0, tx_buf, sizeof(tx_buf));
- *
- */
-
-class IsbProtocol_serial3
-{
-public:
- /**
- * @return singleton intance of the class
- */
- static IsbProtocol_serial3& instance();
-
- ~IsbProtocol_serial3();
-
- /**
- * Set the USART baud rate.
- * @param baud baud rate to be set
- */
- void setBaud(uint32_t baud);
-
- /**
- * Set the node's address in the network
- */
- void setNodeAddress(uint8_t address);
-
- /**
- * @return number of payload data bytes received or 0 if none received
- */
- size_t newDataAvailable();
-
- /**
- * Get the latest payload data received.
- * @param buffer pointer to buffer in which copy the new data, it must have
- * dimension greater than or equal to the value returned by
- * newDataAvailable()
- */
- void getData(uint8_t* buffer);
-
- /**
- * Send a packet, this function blocks until all data is sent
- *
- * @param dstAddr destination node address
- * @param data pointer to a buffer containing the payload data
- * @param len payload size in bytes
- */
- void sendData(uint8_t dstAddr, uint8_t* data, size_t len);
-
- /**
- * Interrupt handler. DON'T CALL IT ANYWHERE!!
- */
- void IRQHandler();
-
-private:
- uint8_t rxBuf[300];
- struct R
- {
- uint16_t packetSize;
- uint16_t rxIndex;
- bool rxInProgress;
- bool dataLenPending;
- } rxStatus;
-
- uint8_t txBuf[300];
- uint8_t nodeAddress;
-
- uint16_t CRC16(uint8_t* data, size_t len);
-
- IsbProtocol_serial3();
- IsbProtocol_serial3(const IsbProtocol_serial3& other);
- IsbProtocol_serial3& operator=(const IsbProtocol_serial3& other);
- bool operator==(const IsbProtocol_serial3& other);
-};
diff --git a/old_examples/shared/drivers/Leds.cpp b/old_examples/shared/drivers/Leds.cpp
deleted file mode 100644
index 2ec4677a10026890df5834c84723b3a37fb45455..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/Leds.cpp
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "Leds.h"
-
-// Relying on the BSP to provide leds and configure them as output
-#define LED(x) miosix::leds::led##x::getPin()
-std::array<miosix::GpioPin, Leds::numLeds> Leds::pins{
- {LED(0), LED(1), LED(2), LED(3), LED(4), LED(5), LED(6), LED(7), LED(8),
- LED(9)}};
-#undef LED
diff --git a/old_examples/shared/drivers/Leds.h b/old_examples/shared/drivers/Leds.h
deleted file mode 100644
index 781ffda4aa9c9af79886cd4153138eb9e128bd6b..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/Leds.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla, Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-
-#include <array>
-
-class Leds
-{
-public:
- /**
- * Turn on/off all leds using a bitmask
- * \param leds bitmask specifing which led has to be turned on
- */
- static void set(uint16_t leds)
- {
- for (int i = 0; i < 10; i++)
- set(i, (leds & (1 << i)) != 0);
- }
-
- /**
- * \param id should be in range [0,10).
- */
- static void set(uint8_t id, bool enable)
- {
- if (id >= pins.size())
- return;
-
- if (enable)
- pins[id].high();
- else
- pins[id].low();
- }
-
-private:
- static const int numLeds = 10;
- static std::array<miosix::GpioPin, numLeds> pins;
-
- Leds() = delete;
- Leds(const Leds&) = delete;
- Leds& operator=(const Leds&) = delete;
-};
diff --git a/old_examples/shared/drivers/ethernet/PacketBuffer.cpp b/old_examples/shared/drivers/ethernet/PacketBuffer.cpp
deleted file mode 100644
index a487860efa221957c9e7eaef31512a14d6906a11..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/PacketBuffer.cpp
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "PacketBuffer.h"
-
-#include <utils/Debug.h>
-
-using namespace std;
-using namespace miosix;
-
-PacketBuffer::PacketBuffer(size_t storageSize)
- : storageSize(storageSize), usedSize(0), writeIndex(0), readIndex(0),
- valid(true)
-{
-#ifndef __NO_EXCEPTIONS
- try
- {
- buffer = new uint8_t[storageSize];
- }
- catch (std::bad_alloc& exc)
- {
- TRACE("bad alloc!\n");
- valid = false;
- }
-#else
- buffer = new (std::nothrow) uint8_t[storageSize];
- if (buffer == nullptr)
- {
- valid = false;
- }
-#endif
-}
-
-PacketBuffer::~PacketBuffer()
-{
- if (valid)
- delete[] buffer;
-}
-
-bool PacketBuffer::push(packet_header_t& header, const uint8_t* payload)
-{
- if (!valid)
- return false;
-
- size_t packetSize = sizeof(packet_header_t) + header.payloadSize;
-
- // Simple technique to avoid ring buffer writeIndex slip ahead readIndex:
- // we keep track of the amount of space used and we reject a new incoming
- // packet if usedSize + packetSize is greater that the ring buffer size.
-
- if (usedSize + packetSize >= storageSize)
- return false;
-
- // to store the packet into the ring buffer first copy the header
- // and then copy the payload
- {
- Lock<FastMutex> l(mutex);
- uint8_t* head = reinterpret_cast<uint8_t*>(&header);
-
- for (unsigned int i = 0; i < sizeof(packet_header_t); i++)
- {
- buffer[(writeIndex + i) % storageSize] = head[i];
- }
-
- writeIndex = (writeIndex + sizeof(packet_header_t)) % storageSize;
-
- for (unsigned int i = 0; i < header.payloadSize; i++)
- {
- buffer[(writeIndex + i) % storageSize] = payload[i];
- }
-
- writeIndex = (writeIndex + header.payloadSize) % storageSize;
- usedSize += packetSize;
- }
-
- return true;
-}
-
-packet_header_t PacketBuffer::getHeader()
-{
- packet_header_t header = {};
- uint8_t* dest = reinterpret_cast<uint8_t*>(&header);
- memset(dest, 0x00, sizeof(packet_header_t));
-
- if (valid)
- {
- Lock<FastMutex> l(mutex);
- for (unsigned int i = 0; i < sizeof(packet_header_t); i++)
- dest[i] = buffer[(readIndex + i) % storageSize];
- }
- return header;
-}
-
-void PacketBuffer::getData(uint8_t* data)
-{
- if (!valid)
- return;
-
- /* Packet size is stored in header, so first get the payloadSize.
- * The data is stored sizeof(packet_header_t) bytes next the read pointer,
- * since a packet is stored as header followed by payload, so we have to
- * add sizeof(packet_header_t) to the read pointer to reach the first data
- * byte
- */
-
- packet_header_t frontHead = getHeader();
-
- {
- Lock<FastMutex> l(mutex);
- int start = readIndex + sizeof(packet_header_t);
-
- for (unsigned int i = 0; i < frontHead.payloadSize; i++)
- {
- data[i] = buffer[(start + i) % storageSize];
- }
- }
-}
-
-void PacketBuffer::popFront()
-{
-
- if ((!valid) || empty()) // this means that list is empty
- return;
-
- /* Popping a packet out of list simply means move the readIndex forward
- * of the size of the packet at list's head.
- * The size of a packet is made of two parts: a fixed one which is
- * constituded by the size of IP address, port and packet length fields
- * and a variable one that is the size of the payload. The latter is stored
- * into the len field of the packet.
- * What we do here is gather the fixed and variable sizes and sum them
- * together to obtain the readIndex's needed increment
- */
-
- packet_header_t head = getHeader();
- size_t packetSize = sizeof(packet_header_t) + head.payloadSize;
-
- {
- Lock<FastMutex> l(mutex);
- readIndex = (readIndex + packetSize) % storageSize;
- usedSize -= packetSize;
- }
-}
-
-bool PacketBuffer::empty()
-{
- Lock<FastMutex> l(mutex);
- return usedSize == 0;
-}
diff --git a/old_examples/shared/drivers/ethernet/PacketBuffer.h b/old_examples/shared/drivers/ethernet/PacketBuffer.h
deleted file mode 100644
index ee47d5566171d8a21d5818e71cfc159672307d20..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/PacketBuffer.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-
-#include "packet.h"
-
-/**
- * Quick and dirty implementation of a ring buffer. All the operations are
- * guaranteed to be atomic through the use of a mutex
- */
-class PacketBuffer
-{
-public:
- /**
- * @param storageSize: size of internal buffer in bytes
- * internal buffer is made of uint8_t
- */
- explicit PacketBuffer(size_t storageSize);
-
- ~PacketBuffer();
-
- /**
- * Check if internal buffer's allocation succeeded. Call this function
- * immediately after constructor and, if it returns false, call the
- * destructor.
- * @return true on success, false on failure.
- */
- bool isValid() { return valid; }
-
- /**
- * Enqueues a packet at list's tail. If it cannot be enqueued is dropped
- * @param packet packet to be enqueued descriptor sctructure
- * @return true if packet can be enqueued, false otherwise
- */
- bool push(packet_header_t& header, const uint8_t* payload);
-
- packet_header_t getHeader();
-
- void getData(uint8_t* data);
-
- /**
- * Removes the packet placed at list's head by avancing it of the
- * packet's size
- */
- void popFront();
-
- /**
- * @return true if buffer is empty
- */
- bool empty();
-
-private:
- size_t storageSize;
- size_t usedSize;
- uint32_t writeIndex;
- uint32_t readIndex;
- bool valid;
- uint8_t* buffer;
-
- miosix::FastMutex mutex;
-
- // Copy constructor and copy assignment are not allowed
- PacketBuffer(PacketBuffer& other);
- PacketBuffer& operator=(const PacketBuffer& other);
-};
diff --git a/old_examples/shared/drivers/ethernet/UdpManager.cpp b/old_examples/shared/drivers/ethernet/UdpManager.cpp
deleted file mode 100644
index 946ff3c2eb5ce6852eeeeb08f47a65b7801416c0..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/UdpManager.cpp
+++ /dev/null
@@ -1,310 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include "UdpManager.h"
-
-using namespace std;
-using namespace miosix;
-
-void __attribute__((naked)) EXTI1_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z13EXTIrqHandlerv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTIrqHandler()
-{
- EXTI->PR |= EXTI_PR_PR1;
- Singleton<UdpManager>::getInstance().phyIrqHandler();
-}
-
-void _evt_mgmt_thread(void* args)
-{
- Singleton<UdpManager>::getInstance().evtQueue.run();
-}
-
-UdpManager::UdpManager()
-{
- eth::int1::mode(Mode::INPUT);
-
- // Configure STM32 to generate an interrupt on
- // falling edge of chip's INT line
-
- {
- FastInterruptDisableLock dLock;
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
- RCC_SYNC();
- }
-
- SYSCFG->EXTICR[0] |= SYSCFG_EXTICR1_EXTI1_PC;
- EXTI->IMR |= EXTI_IMR_MR1;
- EXTI->FTSR |= EXTI_FTSR_TR1;
-
- NVIC_SetPriority(EXTI1_IRQn, 10);
- NVIC_ClearPendingIRQ(EXTI1_IRQn);
- NVIC_EnableIRQ(EXTI1_IRQn);
-
- phy.setModeReg(0x00);
- phy.setSocketInterruptMask(0xFF);
-
- txBuffer = new PacketBuffer(TX_BUF_SIZE);
- rxBuffer = new PacketBuffer(RX_BUF_SIZE);
-
- wdt->setDuration(TX_TIMEOUT);
- wdt->setCallback(bind(&UdpManager::wdtIrqHandler, this));
-
- if (!txBuffer->isValid() || !rxBuffer->isValid())
- {
- // TODO log!
- }
- else
- {
- Thread::create(_evt_mgmt_thread, 1024);
- }
-}
-
-UdpManager::~UdpManager()
-{
- delete txBuffer;
- delete rxBuffer;
-}
-
-void UdpManager::setTxPort(uint16_t port)
-{
- // Open transmitting socket
- phy.setSocketModeReg(PHY_TX_SOCK_NUM, SOCKn_MR_UDP);
- phy.setSocketSourcePort(PHY_TX_SOCK_NUM, port);
- // Enable timeout & send ok interrupts
- phy.setSocketInterruptMaskReg(PHY_TX_SOCK_NUM, 0x18);
- phy.setSocketCommandReg(PHY_TX_SOCK_NUM, SOCKn_CR_OPEN);
-}
-
-void UdpManager::setRxPort(uint16_t port)
-{
- // Open receiving socket
- phy.setSocketModeReg(PHY_RX_SOCK_NUM, SOCKn_MR_UDP);
- phy.setSocketSourcePort(PHY_RX_SOCK_NUM, port);
- // Enable recv interrupt only
- phy.setSocketInterruptMaskReg(PHY_RX_SOCK_NUM, 0x04);
- phy.setSocketCommandReg(PHY_RX_SOCK_NUM, SOCKn_CR_OPEN);
- phy.setSocketCommandReg(PHY_RX_SOCK_NUM, SOCKn_CR_RECV);
-}
-
-/** Legacy code, uncomment if we want tx @ port and rx @ port+1 **/
-
-// void UdpManager::setPort(uint16_t port) {
-//
-// //Open transmitting socket
-// phy.setSocketModeReg(PHY_TX_SOCK_NUM,SOCKn_MR_UDP);
-// phy.setSocketSourcePort(PHY_TX_SOCK_NUM,port);
-// // Enable timeout & send ok interrupts
-// phy.setSocketInterruptMaskReg(PHY_TX_SOCK_NUM,0x18);
-// phy.setSocketCommandReg(PHY_TX_SOCK_NUM,SOCKn_CR_OPEN);
-//
-// //Open receiving socket
-// phy.setSocketModeReg(PHY_RX_SOCK_NUM,SOCKn_MR_UDP);
-// phy.setSocketSourcePort(PHY_RX_SOCK_NUM,port+1);
-// // Enable recv interrupt only
-// phy.setSocketInterruptMaskReg(PHY_RX_SOCK_NUM,0x04);
-// phy.setSocketCommandReg(PHY_RX_SOCK_NUM,SOCKn_CR_OPEN);
-// phy.setSocketCommandReg(PHY_RX_SOCK_NUM,SOCKn_CR_RECV);
-// }
-
-bool UdpManager::newReceivedPackets() { return !rxBuffer->empty(); }
-
-void UdpManager::sendPacketTo(const uint8_t* ip, const uint16_t port,
- const void* data, size_t len)
-{
- packet_header_t header;
- header.ipAddress = *(reinterpret_cast<const uint32_t*>(ip));
- header.port = port;
- header.payloadSize = len;
-
- bool wasEmpty = txBuffer->empty();
- bool ok = txBuffer->push(header, reinterpret_cast<const uint8_t*>(data));
-
- if (!ok)
- {
- // TODO: better failure logging
- puts("UDP->sendPacketTo: failed to enqueue the new packet\n");
- }
- else if (wasEmpty)
- {
- bool pok =
- evtQueue.postNonBlocking(bind(&UdpManager::tx_handler, this));
-
- if (!pok)
- {
- // TODO: better failure logging
- puts(
- "UDP->sendPacketTo: job queue full."
- "Failed to post tx_handler.\n");
- }
- }
-}
-
-size_t UdpManager::recvPacketSize()
-{
- if (rxBuffer->empty())
- return 0;
-
- packet_header_t hdr = rxBuffer->getHeader();
- return hdr.payloadSize;
-}
-
-void UdpManager::readPacket(uint8_t* ip, uint16_t& port, void* data)
-{
- packet_header_t header = rxBuffer->getHeader();
- // IP address is 4 bytes long
- memcpy(ip, reinterpret_cast<uint8_t*>(&(header.ipAddress)), 4);
- port = header.port;
-
- // The copy of the exact number of bytes is guaranteed by getData. We only
- // have to be sure that the receiving buffer has the right capacity,
- // which is given by UdpManager::recvPacketSize()
- rxBuffer->getData(reinterpret_cast<uint8_t*>(data));
- rxBuffer->popFront();
-}
-
-/** Interrupt and event handlers **/
-void UdpManager::phyIrqHandler()
-{
- bool hppw = false;
-
- uint8_t sockInt = phy.readSocketInterruptReg();
-
- // TX socket interrupts management
- if (sockInt & (0x01 << PHY_TX_SOCK_NUM))
- {
- // Stopping watchdog inside an IRQ is safe to do
- wdt->stop();
-
- uint8_t txFlags = phy.getSocketInterruptReg(PHY_TX_SOCK_NUM);
- phy.clearSocketInterruptReg(PHY_TX_SOCK_NUM);
-
- // Send OK interrupt flag set
- if (txFlags & 0x10)
- evtQueue.IRQpost(bind(&UdpManager::tx_end_handler, this), hppw);
-
- // Timeout flag set, problems with ARP
- if (txFlags & 0x08)
- evtQueue.IRQpost(bind(&UdpManager::timeout_handler, this), hppw);
- }
-
- // RX socket interrupts management
- if (sockInt & (0x01 << PHY_RX_SOCK_NUM))
- {
- uint8_t rxFlags = phy.getSocketInterruptReg(PHY_RX_SOCK_NUM);
- phy.clearSocketInterruptReg(PHY_RX_SOCK_NUM);
-
- if (rxFlags & 0x04)
- evtQueue.IRQpost(bind(&UdpManager::rx_handler, this), hppw);
- }
-
- if (hppw)
- Scheduler::IRQfindNextThread();
-}
-
-void UdpManager::wdtIrqHandler()
-{
- bool hppw = false;
- evtQueue.IRQpost(bind(&UdpManager::timeout_handler, this), hppw);
-
- if (hppw)
- Scheduler::IRQfindNextThread();
-}
-
-void UdpManager::tx_handler()
-{
- if (txBuffer->empty())
- return;
-
- packet_header_t header = txBuffer->getHeader();
- uint8_t* addr = reinterpret_cast<uint8_t*>(&header.ipAddress);
-
- uint8_t payload[header.payloadSize];
- txBuffer->getData(payload);
- txBuffer->popFront();
-
- phy.setSocketDestIp(PHY_TX_SOCK_NUM, addr);
- phy.setSocketDestPort(PHY_TX_SOCK_NUM, header.port);
- phy.writeData(PHY_TX_SOCK_NUM, payload, header.payloadSize);
- phy.setSocketCommandReg(PHY_TX_SOCK_NUM, SOCKn_CR_SEND);
-
- wdt->clear();
- wdt->start();
-}
-
-void UdpManager::tx_end_handler()
-{
- if (txBuffer->empty())
- return;
-
- bool ok = evtQueue.postNonBlocking(bind(&UdpManager::tx_handler, this));
- if (!ok)
- {
- // TODO: better failure logging
- puts("UDP->tx_end_handler:job queue full, failed to post tx_handler");
- }
-}
-
-void UdpManager::timeout_handler()
-{
- if (wdt->expired())
- puts("Tx timeout due to watchdog expiration");
- else
- puts("Tx timeout due to phy error");
-
- bool ok = evtQueue.postNonBlocking(bind(&UdpManager::tx_end_handler, this));
- if (!ok)
- puts(
- "UDP->timeout_handler: job queue full, "
- "failed to post tx_end_handler");
-}
-
-void UdpManager::rx_handler()
-{
- // get new packet len, in bytes
- uint16_t len = phy.getReceivedSize(PHY_RX_SOCK_NUM);
- uint8_t buffer[len];
-
- // read all the packet, that is made of so30urceIp + sourcePort +
- // payload len + payload. Since the header length is of 8 bytes,
- // the payload length is len - 8 bytes! :-)
- phy.readData(PHY_RX_SOCK_NUM, buffer, len);
-
- // Set back to listening mode
- phy.setSocketCommandReg(PHY_RX_SOCK_NUM, SOCKn_CR_RECV);
-
- packet_header_t header;
-
- memcpy(reinterpret_cast<uint8_t*>(&(header.ipAddress)), buffer, 4);
- header.port = (buffer[4] << 8) | buffer[5];
- header.payloadSize = len - 8;
-
- bool pushOk = rxBuffer->push(header, &buffer[8]);
-
- if (!pushOk)
- puts(
- "rx_handler error: rxBuffer is full,"
- "cannot enqueue a new packet!");
-}
diff --git a/old_examples/shared/drivers/ethernet/UdpManager.h b/old_examples/shared/drivers/ethernet/UdpManager.h
deleted file mode 100644
index c89f3ddb08de24b4b51843a8f2a7733341731a25..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/UdpManager.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-#include <Singleton.h>
-#include <W5200/w5200.h>
-#include <e20/e20.h>
-
-#include "PacketBuffer.h"
-#include "WatchdogTimer.h"
-
-class UdpManager : Singleton<UdpManager>
-{
- friend class Singleton<UdpManager>;
-
-public:
- /**
- * Open a transmitting UDP socket which source port is @param port
- */
- void setTxPort(uint16_t port);
-
- /**
- * Open a receiving UDP socket that will listen on @param port, listening
- * starts as soon as this function is called
- */
- void setRxPort(uint16_t port);
-
- /**
- * Send an UDP packet.
- * @param ip: destination IP address
- * @param port: destination port
- * @param data: pointer to payload data
- * @param len: payload lenght in bytes
- */
- void sendPacketTo(const uint8_t* ip, const uint16_t port, const void* data,
- size_t len);
-
- /**
- * @return true if there are new packets in the rx buffer
- */
- bool newReceivedPackets();
-
- /**
- * @return payload size of the packet stored at the head of the internal
- * buffer, in other words the packet that will be read if readPacket() is
- * called.
- */
- size_t recvPacketSize();
-
- /**
- * Read the packet placed at rx buffer's head popping it out of the queue.
- * @param ip: source ip address
- * @param port: source port
- * @param data: pointer to a buffer in which store the payload data. It must
- * have a size greater than or equal to that returned by recvPacketSize()
- */
- void readPacket(uint8_t* ip, uint16_t& port, void* data);
-
- /**
- * IRQ handler for interrupts coming from the phy interface chip
- * WARNING: DON'T call this!!
- */
- void phyIrqHandler();
-
- /**
- * IRQ handler for interrupts coming from the tx watchdog timer
- * WARNING: DON'T call this!!
- */
- void wdtIrqHandler();
-
-private:
- // TX timeout time, in ms
- static constexpr unsigned int TX_TIMEOUT = 500; // 500ms timeout
-
- // Size of the event queue, used for event handling
- static constexpr unsigned int EVT_QUEUE_SIZE = 20;
-
- // Size of buffer used to store packets still to be sent, IN BYTES
- static constexpr unsigned int TX_BUF_SIZE = 100000;
-
- // Size of buffer used to store packets received, IN BYTES
- static constexpr unsigned int RX_BUF_SIZE = 100000;
-
- // TX and RX socket number, used by the phy interface
- static constexpr uint8_t PHY_TX_SOCK_NUM = 0;
- static constexpr uint8_t PHY_RX_SOCK_NUM = 1;
-
- miosix::FixedEventQueue<EVT_QUEUE_SIZE> evtQueue;
- PacketBuffer* txBuffer;
- PacketBuffer* rxBuffer;
- W5200& phy = W5200::instance();
- WatchdogTimer* wdt = Singleton<WatchdogTimer>::getInstance();
-
- // Function used by the event management thread
- friend void _evt_mgmt_thread(void* args);
-
- void tx_handler(); //< Tx event handler function
- void tx_end_handler(); //< Tx end event handler function
- void rx_handler(); //< New packet Rx handler function
- void timeout_handler(); //< Tx timeout handler function
-
- UdpManager();
- UdpManager(const UdpManager& other);
- UdpManager& operator=(const UdpManager& other);
- ~UdpManager();
-};
diff --git a/old_examples/shared/drivers/ethernet/W5200/spi_impl.cpp b/old_examples/shared/drivers/ethernet/W5200/spi_impl.cpp
deleted file mode 100644
index 5585500554449111b801ff6bcf40b0541961a42d..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/W5200/spi_impl.cpp
+++ /dev/null
@@ -1,62 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "spi_impl.h"
-
-using namespace miosix;
-
-void Spi_init()
-{
- eth::sck::mode(Mode::ALTERNATE);
- eth::sck::alternateFunction(5);
-
- eth::miso::mode(Mode::ALTERNATE);
- eth::miso::alternateFunction(5);
-
- eth::mosi::mode(Mode::ALTERNATE);
- eth::mosi::alternateFunction(5);
-
- eth::cs::mode(Mode::OUTPUT);
-
- RCC->APB2ENR |= RCC_APB2ENR_SPI5EN;
- RCC_SYNC();
-
- // APB bus frequency is 90MHz, so leaving the BR[2:0] bits
- // in CR1 makes the SPI clock frequency to be 45MHz
-
- SPI5->CR1 = SPI_CR1_SSM // CS handled in software
- | SPI_CR1_SSI // Internal CS high
- | SPI_CR1_SPE // SPI enabled
- | SPI_CR1_MSTR; // Master mode
-}
-
-unsigned char Spi_sendRecv(unsigned char data)
-{
- SPI5->DR = data;
- while ((SPI5->SR & SPI_SR_RXNE) == 0)
- ; // Wait
- return SPI5->DR;
-}
-
-void Spi_CS_high() { eth::cs::high(); }
-
-void Spi_CS_low() { eth::cs::low(); }
diff --git a/old_examples/shared/drivers/ethernet/W5200/spi_impl.h b/old_examples/shared/drivers/ethernet/W5200/spi_impl.h
deleted file mode 100644
index 6a771766d1be15a7c3b1619eada82fda9d81f198..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/W5200/spi_impl.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-
-void Spi_init();
-
-unsigned char Spi_sendRecv(unsigned char data);
-
-void Spi_CS_high();
-
-void Spi_CS_low();
diff --git a/old_examples/shared/drivers/ethernet/W5200/w5200.cpp b/old_examples/shared/drivers/ethernet/W5200/w5200.cpp
deleted file mode 100644
index 18d1fa62eb17c2d3ce08d58a7bfd5cdf1e21976e..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/W5200/w5200.cpp
+++ /dev/null
@@ -1,398 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "w5200.h"
-
-#include "spi_impl.h"
-#include "w5200_defs.h"
-
-W5200& w5200 = W5200::instance();
-
-W5200::W5200()
-{
- /* initialize RX and TX buffer size vectors to default value,
- which is 2kB */
-
- std::fill(txBufSize, txBufSize + MAX_SOCK_NUM, 0x02 << 10);
- std::fill(rxBufSize, rxBufSize + MAX_SOCK_NUM, 0x02 << 10);
-
- Spi_init(); // start SPI bus if needed
- setMacAddress(macAddress);
-}
-
-W5200& W5200::instance()
-{
- static W5200 instance;
- return instance;
-}
-
-void W5200::setMacAddress(const uint8_t* address)
-{
- writeRegister(SHAR_BASE, address[0]);
- writeRegister(SHAR_BASE + 1, address[1]);
- writeRegister(SHAR_BASE + 2, address[2]);
- writeRegister(SHAR_BASE + 3, address[3]);
- writeRegister(SHAR_BASE + 4, address[4]);
- writeRegister(SHAR_BASE + 5, address[5]);
-}
-
-void W5200::setIpAddress(const uint8_t* address)
-{
- writeRegister(SIPR_BASE, address[0]);
- writeRegister(SIPR_BASE + 1, address[1]);
- writeRegister(SIPR_BASE + 2, address[2]);
- writeRegister(SIPR_BASE + 3, address[3]);
-}
-
-void W5200::setSubnetMask(const uint8_t* mask)
-{
- writeRegister(SUBR_BASE, mask[0]);
- writeRegister(SUBR_BASE + 1, mask[1]);
- writeRegister(SUBR_BASE + 2, mask[2]);
- writeRegister(SUBR_BASE + 3, mask[3]);
-}
-
-void W5200::setGatewayAddress(const uint8_t* address)
-{
- writeRegister(GAR_BASE, address[0]);
- writeRegister(GAR_BASE + 1, address[1]);
- writeRegister(GAR_BASE + 2, address[2]);
- writeRegister(GAR_BASE + 3, address[3]);
-}
-
-void W5200::setModeReg(uint8_t value) { writeRegister(MR, value); }
-
-void W5200::setInterruptMask(uint8_t mask) { writeRegister(IR_MASK, mask); }
-
-uint8_t W5200::readInterruptReg() const { return readRegister(IR); }
-
-void W5200::setSocketMSS(SOCKET sockNum, uint16_t value)
-{
- writeRegister(SOCKn_MSSR0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((value & 0xff00) >> 8));
- writeRegister(SOCKn_MSSR0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(value & 0x00ff));
-}
-
-void W5200::setRetryCount(uint16_t value) { writeRegister(RCR, value); }
-
-void W5200::setRetryTime(uint16_t value)
-{
- writeRegister(RTR_BASE, static_cast<uint8_t>((value & 0xff00) >> 8));
- writeRegister(RTR_BASE + 1, static_cast<uint8_t>(value & 0x00ff));
-}
-
-void W5200::setSocketModeReg(SOCKET sockNum, uint8_t value)
-{
- writeRegister(SOCKn_MR + sockNum * SR_SIZE, value);
-}
-
-uint8_t W5200::getSocketStatusReg(SOCKET sockNum) const
-{
- return readRegister(SOCKn_SR + sockNum * SR_SIZE);
-}
-
-uint8_t W5200::getSocketInterruptReg(SOCKET sockNum) const
-{
- return readRegister(SOCKn_IR + sockNum * SR_SIZE);
-}
-
-void W5200::clearSocketInterruptReg(SOCKET sockNum)
-{
- writeRegister(SOCKn_IR + sockNum * SR_SIZE, 0xFF);
-}
-
-void W5200::setSocketProtocolValue(SOCKET sockNum, uint8_t value)
-{
- writeRegister(SOCKn_PROTO + sockNum * SR_SIZE, value);
-}
-
-uint8_t W5200::getPhyStatus() const { return readRegister(PHY); }
-
-uint8_t W5200::readSocketInterruptReg() const { return readRegister(SOCK_IR); }
-
-void W5200::setSocketInterruptMask(uint8_t mask)
-{
- writeRegister(SOCK_IR_MASK, mask);
-}
-
-void W5200::setSocketInterruptMaskReg(SOCKET sockNum, uint8_t value)
-{
- writeRegister(SOCKn_IMR + sockNum * SR_SIZE, value);
-}
-
-void W5200::setSocketCommandReg(SOCKET sockNum, uint8_t value)
-{
- writeRegister(SOCKn_CR + sockNum * SR_SIZE, value);
-}
-
-uint8_t W5200::getSocketCommandReg(SOCKET sockNum) const
-{
- return readRegister(SOCKn_CR + sockNum * SR_SIZE);
-}
-
-void W5200::setSocketDestIp(SOCKET sockNum, const uint8_t* destIP)
-{
- writeRegister(SOCKn_DIPR0 + sockNum * SR_SIZE, destIP[0]);
- writeRegister(SOCKn_DIPR0 + sockNum * SR_SIZE + 1, destIP[1]);
- writeRegister(SOCKn_DIPR0 + sockNum * SR_SIZE + 2, destIP[2]);
- writeRegister(SOCKn_DIPR0 + sockNum * SR_SIZE + 3, destIP[3]);
-}
-
-void W5200::setSocketDestMac(SOCKET sockNum, uint8_t* destMAC)
-{
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE, destMAC[0]);
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE + 1, destMAC[1]);
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE + 2, destMAC[2]);
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE + 3, destMAC[3]);
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE + 4, destMAC[4]);
- writeRegister(SOCKn_DHAR0 + sockNum * SR_SIZE + 5, destMAC[5]);
-}
-
-void W5200::setSocketDestPort(SOCKET sockNum, uint16_t destPort)
-{
- writeRegister(SOCKn_DPORT0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((destPort & 0xff00) >> 8));
- writeRegister(SOCKn_DPORT0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(destPort & 0x00ff));
-}
-
-void W5200::setSocketSourcePort(SOCKET sockNum, uint16_t port)
-{
- writeRegister(SOCKn_SPORT0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((port & 0xff00) >> 8));
- writeRegister(SOCKn_SPORT0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(port & 0x00ff));
-}
-
-void W5200::setSocketFragmentValue(SOCKET sockNum, uint16_t value)
-{
- writeRegister(SOCKn_FRAG0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((value & 0xff00) >> 8));
- writeRegister(SOCKn_FRAG0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(value & 0x00ff));
-}
-
-void W5200::setSocketTos(SOCKET sockNum, uint8_t TOSvalue)
-{
- writeRegister(SOCKn_TOS + sockNum * SR_SIZE, TOSvalue);
-}
-
-void W5200::setSocketTtl(SOCKET sockNum, uint8_t TTLvalue)
-{
- writeRegister(SOCKn_TTL + sockNum * SR_SIZE, TTLvalue);
-}
-
-void W5200::setSocketRxMemSize(SOCKET sockNum, uint8_t memSize)
-{
- writeRegister(SOCKn_RXMEM_SIZE + sockNum * SR_SIZE, memSize);
- rxBufSize[sockNum] = memSize << 10;
-}
-
-void W5200::setSocketTxMemSize(SOCKET sockNum, uint8_t memSize)
-{
- writeRegister(SOCKn_TXMEM_SIZE + sockNum * SR_SIZE, memSize);
- txBufSize[sockNum] = memSize << 10;
-}
-
-uint16_t W5200::getReceivedSize(SOCKET sockNum) const
-{
- uint16_t len;
- len = readRegister(SOCKn_RX_RSR0 + sockNum * SR_SIZE) << 8;
- len += readRegister(SOCKn_RX_RSR0 + sockNum * SR_SIZE + 1);
-
- return len;
-}
-
-void W5200::readData(SOCKET sockNum, uint8_t* data, uint16_t len)
-{
- uint16_t readPtr;
-
- // Read read pointer's upper byte
- readPtr = readRegister(SOCKn_RX_RD0 + sockNum * SR_SIZE) << 8;
- // Read read pointer's lower byte
- readPtr += readRegister(SOCKn_RX_RD0 + sockNum * SR_SIZE + 1);
-
- readRxBuf(sockNum, readPtr, data, len);
-
- readPtr += len;
-
- // Update read pointer value
- writeRegister(SOCKn_RX_RD0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((readPtr & 0xFF00) >> 8));
- writeRegister(SOCKn_RX_RD0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(readPtr & 0x00FF));
-}
-
-void W5200::writeData(SOCKET sockNum, const uint8_t* data, uint16_t len)
-{
- uint16_t writePtr;
- // Read write pointer's upper byte
- writePtr = readRegister(SOCKn_TX_WR0 + sockNum * SR_SIZE) << 8;
- // Read write pointer's lower byte
- writePtr += readRegister(SOCKn_TX_WR0 + sockNum * SR_SIZE + 1);
-
- writeTxBuf(sockNum, data, writePtr, len);
-
- writePtr += len;
-
- // Update write pointer value
- writeRegister(SOCKn_TX_WR0 + sockNum * SR_SIZE,
- static_cast<uint8_t>((writePtr & 0xFF00) >> 8));
- writeRegister(SOCKn_TX_WR0 + sockNum * SR_SIZE + 1,
- static_cast<uint8_t>(writePtr & 0x00FF));
-}
-
-void W5200::readRxBuf(SOCKET socket, uint16_t src, uint8_t* dst, uint16_t len)
-{
- /* Compute socket's buffer base address as a sum of RX_BUF_BASE and
- * the sizes of buffers allotted for sockets before this
- */
-
- uint16_t sockBufBase = RX_BUF_BASE;
-
- for (int i = 0; i < socket; i++)
- sockBufBase += rxBufSize[i];
-
- /* The address mask value is equal to socket's size in byte minus one */
-
- uint16_t mask = rxBufSize[socket] - 1;
-
- /* The physical address at which reading process begins is base address
- * plus the logical and between src pointer and address mask
- */
-
- uint16_t startAddress = (src & mask) + sockBufBase;
-
- if ((src & mask) + len > rxBufSize[socket])
- {
- uint16_t size = rxBufSize[socket] - (src & mask);
- readBuffer(startAddress, dst, size);
- dst += size;
- size = len - size;
- readBuffer(sockBufBase, dst, size);
- }
- else
- {
- readBuffer(startAddress, dst, len);
- }
-}
-
-void W5200::writeTxBuf(SOCKET socket, const uint8_t* src, uint16_t dst,
- uint16_t len)
-{
- /* Compute socket's buffer base address as a sum of RX_BUF_BASE and
- * the sizes of buffers allotted for sockets before this
- */
- uint16_t sockBufBase = TX_BUF_BASE;
-
- for (int i = 0; i < socket; i++)
- sockBufBase += txBufSize[i];
-
- /* The address mask value is equal to socket's size in byte minus one */
- uint16_t mask = txBufSize[socket] - 1;
-
- /* The physical address at which reading process begins is base address
- * plus the logical and between src pointer and address mask
- */
-
- uint16_t startAddress = (dst & mask) + sockBufBase;
-
- if ((dst & mask) + len > txBufSize[socket])
- {
- uint16_t size = txBufSize[socket] - (dst & mask);
- writeBuffer(startAddress, src, size);
- src += size;
- size = len - size;
- writeBuffer(sockBufBase, src, size);
- }
- else
- {
- writeBuffer(startAddress, src, len);
- }
-}
-
-uint8_t W5200::readRegister(uint16_t address) const
-{
- uint8_t data;
-
- Spi_CS_low();
-
- Spi_sendRecv((address & 0xFF00) >> 8); // Address byte 1
- Spi_sendRecv(address & 0x00FF); // Address byte 2
- Spi_sendRecv(0x00); // Data read command and len[0]
- Spi_sendRecv(0x01); // Read len[1]
- data = Spi_sendRecv(0x00); // Data read
-
- Spi_CS_high();
-
- return data;
-}
-
-void W5200::readBuffer(uint16_t address, uint8_t* data, uint16_t len)
-{
- if (len == 0)
- return;
-
- Spi_CS_low();
-
- Spi_sendRecv((address & 0xFF00) >> 8); // Address byte 1
- Spi_sendRecv(address & 0x00FF); // Address byte 2
- Spi_sendRecv(0x00 | ((len & 0x7F00) >> 8)); // Write cmd and len[0]
- Spi_sendRecv(len & 0x00FF); // Write data len[1]
-
- for (uint16_t i = 0; i < len; i++)
- data[i] = Spi_sendRecv(0x00);
-
- Spi_CS_high();
-}
-
-void W5200::writeBuffer(uint16_t address, const uint8_t* data, uint16_t len)
-{
- if (len == 0)
- return;
-
- Spi_CS_low();
-
- Spi_sendRecv((address & 0xFF00) >> 8); // Address byte 1
- Spi_sendRecv(address & 0x00FF); // Address byte 2
- Spi_sendRecv(0x80 | ((len & 0x7F00) >> 8)); // Write cmd and len[0]
- Spi_sendRecv(len & 0x00FF); // Write data len[1]
-
- for (uint16_t i = 0; i < len; i++)
- Spi_sendRecv(data[i]);
-
- Spi_CS_high();
-}
-
-void W5200::writeRegister(uint16_t address, uint8_t data)
-{
- Spi_CS_low();
-
- Spi_sendRecv((address & 0xFF00) >> 8); // Address byte 1
- Spi_sendRecv(address & 0x00FF); // Address byte 2
- Spi_sendRecv(0x80); // Write cmd and len[0]
- Spi_sendRecv(0x01); // Write data len[1]
- Spi_sendRecv(data); // Data write
-
- Spi_CS_high();
-}
diff --git a/old_examples/shared/drivers/ethernet/W5200/w5200.h b/old_examples/shared/drivers/ethernet/W5200/w5200.h
deleted file mode 100644
index d59c6bc817d7ad5eb8381f80af3e669903dc015e..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/W5200/w5200.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include "spi_impl.h"
-#include "w5200_defs.h"
-
-typedef uint8_t SOCKET;
-
-// extern W5200& w5200; //a W5200 driver class instance
-
-class W5200
-{
-public:
- /**
- * \return a singleton instance of W5200 class
- */
- static W5200 &instance();
-
- /**
- * Set chip's MAC address
- */
- void setMacAddress(const uint8_t *address);
-
- /**
- * Set chip's IP address
- */
- void setIpAddress(const uint8_t *address);
-
- /**
- * Set network's subnet mask
- */
- void setSubnetMask(const uint8_t *mask);
-
- /**
- * Set network's gateway IP address
- */
- void setGatewayAddress(const uint8_t *address);
-
- /**
- * Set Mode register flags
- */
- void setModeReg(uint8_t value);
-
- /**
- * Set retransmission timeout period in units of 100us each
- * for example to set timeout period to 400ms you have to set
- * this register to 0x4000
- */
- void setRetryTime(uint16_t value);
-
- /**
- * Configures the number of retransmissions
- */
- void setRetryCount(uint16_t value);
-
- /**
- * Configures the interrupt mask for socket interrupts
- */
- void setInterruptMask(uint8_t mask);
-
- /**
- * \return chip's interrupt register value
- */
- uint8_t readInterruptReg() const;
-
- /**
- * \return chip's IR2 register value, please refer to datasheet
- */
- uint8_t readSocketInterruptReg() const;
-
- /**
- * Configures chip's IMR2 register, please refer to datasheet
- */
- void setSocketInterruptMask(uint8_t mask);
-
- /**
- * \return value of register that indicates chip's
- * physical status
- */
- uint8_t getPhyStatus() const;
-
- /**
- * Writes socket's mode register
- * \param sockNum: socket number, between 0 and 7
- * \param value: value to be written
- */
- void setSocketModeReg(SOCKET sockNum, uint8_t value);
-
- /**
- * Used to send a command to a socket through its command register
- * \param sockNum: socket number, between 0 and 7
- * \param value: command opcode
- */
- void setSocketCommandReg(SOCKET sockNum, uint8_t value);
-
- /**
- * Used to get register's value, as a way to check if a given
- * command is completed
- * \param sockNum: socket number, between 0 and 7
- * \return register's value
- */
- uint8_t getSocketCommandReg(SOCKET sockNum) const;
-
- /**
- * Configures the socket interrupts that will be signalled
- * \param sockNum: socket number, between 0 and 7
- * \param value: mask value
- */
- void setSocketInterruptMaskReg(SOCKET sockNum, uint8_t value);
-
- /**
- * Reads socket's interrupt register
- * \param sockNum: socket number, between 0 and 7
- * \return socket's interrupt register value
- */
- uint8_t getSocketInterruptReg(SOCKET sockNum) const;
-
- /**
- * Resets all the socket's interrupt register flags
- * \param sockNum: socket number, between 0 and 7
- */
-
- void clearSocketInterruptReg(SOCKET sockNum);
-
- /**
- * Reads socket's status register
- * \param sockNum: socket number, between 0 and 7
- * \return socket's status register value
- */
- uint8_t getSocketStatusReg(SOCKET sockNum) const;
-
- /**
- * Sets socket's source port value, both for TCP and UDP
- * \param sockNum: socket number, between 0 and 7
- * \param port: socket's source port number
- */
- void setSocketSourcePort(SOCKET sockNum, uint16_t port);
-
- /**
- * Sets socket's destination MAC address
- * \param sockNum: socket number, between 0 and 7
- * \param destMAC: socket's destination MAC address
- */
- void setSocketDestMac(SOCKET sockNum, uint8_t *destMAC);
-
- /**
- * Sets socket's destination IP address
- * \param sockNum: socket number, between 0 and 7
- * \param destIP: socket's destination IP address
- */
- void setSocketDestIp(SOCKET sockNum, const uint8_t *destIP);
-
- /**
- * Sets socket's destination port number
- * \param sockNum: socket number, between 0 and 7
- * \param value: socket's destination port number
- */
- void setSocketDestPort(SOCKET sockNum, uint16_t destPort);
-
- /**
- * Set socket's Maximum Segment Size for TCP mode
- * \param sockNum: socket number, between 0 and 7
- * \param value: MSS value
- */
- void setSocketMSS(SOCKET sockNum, uint16_t value);
-
- /**
- * Set socket's protocol number when used in IPraw mode
- * \param sockNum: socket number, between 0 and 7
- * \param value: protocol number
- */
- void setSocketProtocolValue(SOCKET sockNum, uint8_t value);
-
- /** W5200();
- * Sets Type Of Service field value in socket's IP header
- * \param sockNum: socket number, between 0 and 7
- * \param TOSvalue: field value
- */
- void setSocketTos(SOCKET sockNum, uint8_t TOSvalue);
-
- /**
- * Sets Time To Live field value in socket's IP header
- * \param sockNum: socket number, between 0 and 7
- * \param TTLvalue: field value
- */
- void setSocketTtl(SOCKET sockNum, uint8_t TTLvalue);
-
- /**
- * Sets Fragment field value in socket's IP header
- * \param sockNum: socket number, between 0 and 7
- * \param value: field value
- */
- void setSocketFragmentValue(SOCKET sockNum, uint16_t value);
-
- /**
- * Configures socket's internal RX memory size
- * Accepted values are: 0, 1, 2, 4, 8 and 16kB
- * \param sockNum: socket number, between 0 and 7
- * \param memSize: desired RX memory size
- */
- void setSocketRxMemSize(SOCKET sockNum, uint8_t memSize);
-
- /**
- * Configures socket's internal TX memory size
- * Accepted values are: 0, 1, 2, 4, 8 and 16kB
- * \param sockNum: socket number, between 0 and 7
- * \param memSize: desired TX memory size
- */
- void setSocketTxMemSize(SOCKET sockNum, uint8_t memSize);
-
- /**
- * Writes data into socket TX buffer and updates in-chip pointer
- * \param sockNum: socket number, between 0 and 7
- * \param data: pointer to buffer containing data to be written
- * \param len: number of bytes to be written
- */
- void writeData(SOCKET sockNum, const uint8_t *data, uint16_t len);
-
- /**
- * Reads data from socket RX buffer and updates in-chip pointer
- * \param sockNum: socket number, between 0 and 7
- * \param data: pointer to buffer in which write data
- * \param len: number of bytes to be read
- */
- void readData(SOCKET sockNum, uint8_t *data, uint16_t len);
-
- /**
- * \param sockNum: socket number, between 0 and 7
- * \return the received data size in byte
- */
- uint16_t getReceivedSize(SOCKET sockNum) const;
-
-private:
- W5200();
-
- /**
- * Write one byte into chip's register
- * \param address: register's address
- * \param data: data to be written
- */
- void writeRegister(uint16_t address, uint8_t data);
-
- /**
- * Write multiple bytes into chip's memory
- * \param address: writing process start point address
- * \param data: pointer to the data to be written
- * \param len: number of bytes to be written
- */
- void writeBuffer(uint16_t address, const uint8_t *data, uint16_t len);
-
- /**
- * Read one byte from chip's register
- * \param address: register's address
- * \return data read
- */
- uint8_t readRegister(uint16_t address) const;
-
- /**
- * Read multiple bytes into chip's memory
- * \param address: reading process start point address
- * \param data: pointer to the data to be read
- * \param len: number of bytes to be read
- */
- void readBuffer(uint16_t address, uint8_t *data, uint16_t len);
-
- /**
- * This function is used to copy data from application buffer to socket's
- * in-chip TX buffer
- *
- * TODO: better description
- *
- * \param socket: socket number, between 0 and 7
- * \param src: pointer to source buffer
- * \param dst: destination buffer start address.
- * This start address is referred to chip's buffer!!
- * \param len: number of bytes to be copied
- */
- void writeTxBuf(SOCKET socket, const uint8_t *src, uint16_t dst,
- uint16_t len);
-
- /**
- * This function is used to copy data from socket's in-chip TX buffer
- * to application buffer
- *
- * TODO: better description
- *
- * \param socket: socket number, between 0 and 7
- * \param src: source buffer start address.
- * This start address is referred to chip's buffer!!
- * \param dst: pointer to destination buffer
- * \param len: number of bytes to be copied
- */
- void readRxBuf(SOCKET socket, uint16_t src, uint8_t *dst, uint16_t len);
-
- uint16_t txBufSize[MAX_SOCK_NUM]; // sockets TX buffer size in byte
- uint16_t rxBufSize[MAX_SOCK_NUM]; // sockets RX buffer size in byte
-
- const uint8_t macAddress[6] = {0xde, 0xad, 0x00, 0x00, 0xbe, 0xef};
-};
diff --git a/old_examples/shared/drivers/ethernet/W5200/w5200_defs.h b/old_examples/shared/drivers/ethernet/W5200/w5200_defs.h
deleted file mode 100644
index 32f38f6845e66933a177dcaf07db7ab350e1bfba..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/W5200/w5200_defs.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-
-/* Maximum number of sockets managed by the device */
-constexpr uint8_t MAX_SOCK_NUM = 8;
-
-static constexpr uint32_t COMMON_BASE = 0x0000;
-
-// TX buffer memory base address
-constexpr uint32_t TX_BUF_BASE = COMMON_BASE + 0x8000;
-
-// RX buffer memory base address
-constexpr uint32_t RX_BUF_BASE = COMMON_BASE + 0xC000;
-
-// clang-format off
-/** Common registers **/
-enum eW5200Registers
-{
- MR = COMMON_BASE + 0x0000, //mode register address
- GAR_BASE = COMMON_BASE + 0x0001, //Gateway IP Register base address
- SUBR_BASE = COMMON_BASE + 0x0005, //Subnet mask Register base address
- SHAR_BASE = COMMON_BASE + 0x0009, //Source MAC Register base address
- SIPR_BASE = COMMON_BASE + 0x000F, //Source IP Register base address
- IR = COMMON_BASE + 0x0015, //Interrupt Register address
- IR_MASK = COMMON_BASE + 0x0036, //Interrupt mask register
- RTR_BASE = COMMON_BASE + 0x0017, //retransmission Timeout register
- RCR = COMMON_BASE + 0x0019, //retransmission count register
- SOCK_IR = COMMON_BASE + 0x0034, //Socket Interrupt Register
- SOCK_IR_MASK = COMMON_BASE + 0x0016, //Socket Interrupt mask register
- PHY = COMMON_BASE + 0x0035, //PHY Status Register
- VERSION = COMMON_BASE + 0x001F, //chip version number register
- PPP_AUTH_REG = COMMON_BASE + 0x001C, //autentication type in PPPoE mode
- PPP_TIME_REG = COMMON_BASE + 0x0028, //LCP Request Timer in PPPoE mode
- PPP_MAGIC_REG = COMMON_BASE + 0x0029, //PPP LCP Magic number in PPPoE mode
- INTLEVEL0 = COMMON_BASE + 0x0030, //set Interrupt LL timer register
- INTLEVEL1 = COMMON_BASE + 0x0031,
-};
-
-/* MODE register values */
-enum eW5200MODERegisters
-{
- MR_RST = 0x80, // Reset
- MR_PB = 0x10, // Ping block enable
- MR_PPPOE = 0x08, // PPPoE enable
-};
-
-/* IR register values */
-enum eW5200IRRegisters
-{
- IR_CONFLICT = 0x80, //IP conflict
- IR_PPPoE = 0x20, //PPPoE connection close
-};
-
-/* Socket registers */
-enum eW5200SockRegisters
-{
- SR_BASE = COMMON_BASE + 0x4000, //Socket registers base address
- SR_SIZE = 0x100, //Size of each channel register map
-};
-
-enum eW5200SockNRegisters
-{
- SOCKn_MR = SR_BASE + 0x0000, // Mode register
- SOCKn_CR = SR_BASE + 0x0001, // Command register
- SOCKn_IR = SR_BASE + 0x0002, // Interrupt register
- SOCKn_SR = SR_BASE + 0x0003, // Status register
- SOCKn_SPORT0 = SR_BASE + 0x0004, // Source port register
- SOCKn_DHAR0 = SR_BASE + 0x0006, // Destination MAC address register
- SOCKn_DIPR0 = SR_BASE + 0x000C, // Destination IP address register
- SOCKn_DPORT0 = SR_BASE + 0x0010, // Destination port register
- SOCKn_IMR = SR_BASE + 0x002C, // Interrupt mask register
-
- SOCKn_MSSR0 = SR_BASE + 0x0012, // MSS in TCP mode
-
- SOCKn_PROTO = SR_BASE + 0x0014, // Protocol number in IPRAW mode
-
- SOCKn_TOS = SR_BASE + 0x0015, // IP header ToS field value
- SOCKn_TTL = SR_BASE + 0x0016, // IP header TTL field value
- SOCKn_FRAG0 = SR_BASE + 0x002D, // IP header Fragment field value
-
- SOCKn_RXMEM_SIZE = SR_BASE + 0x001E, // RX buffer size register
- SOCKn_TXMEM_SIZE = SR_BASE + 0x001F, // TX buffer size register
-
- SOCKn_TX_FSR0 = SR_BASE + 0x0020, // TX buffer free size register
- SOCKn_TX_RD0 = SR_BASE + 0x0022, // TX buffer read pointer address
- SOCKn_TX_WR0 = SR_BASE + 0x0024, // TX buffer write pointer address
-
- SOCKn_RX_RSR0 = SR_BASE + 0x0026, // Received data size register
- SOCKn_RX_RD0 = SR_BASE + 0x0028, // RX buffer read pointer address
- SOCKn_RX_WR0 = SR_BASE + 0x002A, // RX buffer write pointer address
-};
-
-/* SOCKn_MR values */
-enum eW5200SockNMRValues
-{
- SOCKn_MR_CLOSE = 0x00, // Socket closed
- SOCKn_MR_TCP = 0x01, // TCP mode
- SOCKn_MR_UDP = 0x02, // UDP mode
- SOCKn_MR_IPRAW = 0x03, // IP layer raw socket
- SOCKn_MR_MACRAW = 0x04, // MAC layer raw socket
- SOCKn_MR_PPPOE = 0x05, // PPPoE mode
- SOCKn_MR_ND = 0x20, // No delayed ACK enable
- SOCKn_MR_MULTI = 0x80, // Enable multicasting (only in UDP mode)
-};
-
-/* SOCKn_CR values */
-enum eW5200SockNCRValues
-{
- SOCKn_CR_OPEN = 0x01, // Initialize and open socket
- SOCKn_CR_LISTEN = 0x02, // Wait conn request in TCP mode (Server mode)
- SOCKn_CR_CONNECT = 0x04, // Send conn request in TCP mode (Client mode)
- SOCKn_CR_DISCON = 0x08, // Disconnect request in TCP mode
- SOCKn_CR_CLOSE = 0x10, // Close socket
- SOCKn_CR_SEND = 0x20, // Send all data stored in TX buffer
- SOCKn_CR_SEND_MAC = 0x21, // Send data + MAC without ARP (only in UDP mode)
- SOCKn_CR_SEND_KEEP = 0x22, // Check if TCP connection is still alive
- SOCKn_CR_RECV = 0x40, // Receive data
-};
-
-/* SOCKn_IR values */
-enum eW5200SockNIRValues
-{
- SOCKn_IR_CON = 0x01, // Connection established
- SOCKn_IR_DISCON = 0x02, // Disconnected (TCP mode)
- SOCKn_IR_RECV = 0x04, // Some data received
- SOCKn_IR_TIMEOUT = 0x08, // Timeout occurred in ARP or TCP
- SOCKn_IR_SEND_OK = 0x10, // SEND command completed
-};
-
-/* SOCKn_SR values */
-enum eW5200SockStatus
-{
- SOCK_CLOSED = 0x00, // Socket closed
- SOCK_INIT = 0x13, // TCP init state
- SOCK_LISTEN = 0x14, // TCP server listen for connection state
- SOCK_SYNSENT = 0x15, // TCP connection request sent to server
- SOCK_SYNRECV = 0x16, // TCP connection request received from client
- SOCK_ESTABLISHED = 0x17, // TCP connection established
- SOCK_FIN_WAIT = 0x18, // TCP closing state
- SOCK_CLOSING = 0x1A, // TCP closing state
- SOCK_TIME_WAIT = 0x1B, // TCP closing state
- SOCK_CLOSE_WAIT = 0x1C, // TCP closing state
- SOCK_LAST_ACK = 0x1D, // TCP closing state
- SOCK_UDP = 0x22, // Socket opened in UDP mode
- SOCK_IPRAW = 0x32, // Socket opened in IP raw mode
- SOCK_MACRAW = 0x42, // Socket opened in MAC raw mode
- SOCK_PPPOE = 0x5F, // Socket opened in PPPoE mode
-};
-
-/* IPProto values */
-enum eW5200IPProtoValues
-{
- IPPROTO_IP = 0, // Dummy for IP
- IPPROTO_ICMP = 1, // ICMP protocol
- IPPROTO_IGMP = 2, // IGMP protocol
- IPPROTO_GGP = 3, // GGP protocol
- IPPROTO_TCP = 6, // TCP
- IPPROTO_PUP = 12, // PUP
- IPPROTO_UDP = 17, // UDP
- IPPROTO_IDP = 22, // XNS idp
- IPPROTO_RAW = 255, // Raw IP packet */
-};
-// clang-format on
diff --git a/old_examples/shared/drivers/ethernet/WatchdogTimer.cpp b/old_examples/shared/drivers/ethernet/WatchdogTimer.cpp
deleted file mode 100644
index 3868ac03bf142c5462207ef720509bec0d8b5476..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/WatchdogTimer.cpp
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include "WatchdogTimer.h"
-
-using namespace miosix;
-using namespace std;
-
-void __attribute__((naked)) TIM7_IRQHandler()
-{
-
- saveContext();
- asm volatile("bl _Z8Irq_implv");
- restoreContext();
-}
-
-void __attribute__((used)) Irq_impl()
-{
-
- TIM7->SR = 0;
- auto inst = Singleton<WatchdogTimer>::getInstance();
- inst->stop();
- inst->triggered = true;
- inst->irqCallback();
-}
-
-WatchdogTimer::WatchdogTimer() : ms_to_tick(1), triggered(false)
-{
-
- {
- FastInterruptDisableLock dLock;
- RCC->APB1ENR |= RCC_APB1ENR_TIM7EN;
- RCC_SYNC();
- }
-
- unsigned int busFreq = SystemCoreClock; // CMSIS defined variable
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= (0x01 << ((RCC->CFGR >> 10) & 0x3));
- }
-
- uint32_t prescaler = busFreq / 1000; // We want a 1ms/tick timer
-
- // If we obtain a prescaler value upper than 65536 there is a problem:
- // since prescaler value can be at most 65536 the counter will run at a
- // frequency greater than 1kHz. To obtain a timer with a resolution of
- // 1ms we have to determine how many ticks are 1ms. To do this we calculate
- // the timer frequency as busFreq/prescaler and then ms_to_tick as
- // timer_freq/1000
-
- if (prescaler >= 65536)
- {
- prescaler = 65536;
- unsigned int fclock = busFreq / prescaler;
- ms_to_tick = static_cast<float>(fclock) / 1000.0f;
- }
-
- TIM7->CNT = 0;
- TIM7->ARR = 0;
- TIM7->PSC = prescaler - 1; // Set prescaler
- TIM7->CR1 |= TIM_CR1_OPM // Enable one pulse mode
- | TIM_CR1_URS; // interrupt only on counter overflow
- TIM7->DIER |= TIM_DIER_UIE; // Enable interrupt
- TIM7->EGR |= TIM_EGR_UG; // Generate update event to preset registers
-
- NVIC_SetPriority(TIM7_IRQn, 10);
- NVIC_ClearPendingIRQ(TIM7_IRQn);
- NVIC_EnableIRQ(TIM7_IRQn);
-}
-
-WatchdogTimer::~WatchdogTimer()
-{
-
- stop();
-
- {
- FastInterruptDisableLock dLock;
- RCC->APB1ENR &= ~RCC_APB1ENR_TIM7EN;
- RCC_SYNC();
- }
-}
-
-void WatchdogTimer::clear()
-{
-
- TIM7->CNT = 0;
- triggered = false;
-}
-
-void WatchdogTimer::start()
-{
-
- triggered = false;
- TIM7->CR1 |= TIM_CR1_CEN;
-}
-
-void WatchdogTimer::stop() { TIM7->CR1 &= ~TIM_CR1_CEN; }
-
-void WatchdogTimer::setDuration(uint16_t duration)
-{
-
- float ticks = static_cast<float>(duration) * ms_to_tick;
- TIM7->ARR = static_cast<uint16_t>(ticks + 0.5f); // round to nearest
-}
diff --git a/old_examples/shared/drivers/ethernet/WatchdogTimer.h b/old_examples/shared/drivers/ethernet/WatchdogTimer.h
deleted file mode 100644
index 35dc5a9e0e9eeb4224ac57a3aa0b63843b5de01f..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/WatchdogTimer.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Common.h>
-#include <Singleton.h>
-
-#include <functional>
-
-class WatchdogTimer : Singleton<WatchdogTimer>
-{
- friend class Singleton<WatchdogTimer>;
-
-public:
- /**
- * Start the timer
- */
- void start();
-
- /**
- * Stop the timer
- */
- void stop();
-
- /**
- * Clear timer's internal counter
- */
- void clear();
-
- /**
- * Set timeout period: callback after @param duration milliseconds after
- * counter is started
- */
- void setDuration(uint16_t duration);
-
- /**
- * Set a function that will be called when timer expires.
- * WARNING: the callback will be executed inside an interrupt routine, so
- * it must be written properly!! It cannot malloc, printf and other things
- * like that
- */
- void setCallback(const std::function<void()>& callback)
- {
- irqCallback = callback;
- }
-
- /**
- * @return true if timer expired. Calling start() and clear() reset the
- * flag to false
- */
- bool expired() { return triggered; }
-
-private:
- WatchdogTimer();
- ~WatchdogTimer();
-
- float ms_to_tick; // conversion factor, number of counter ticks in a ms
- bool triggered;
- std::function<void()> irqCallback;
-
- friend void Irq_impl();
-
- WatchdogTimer(const WatchdogTimer& other);
- WatchdogTimer& operator=(const WatchdogTimer& other);
- bool operator==(const WatchdogTimer& other);
-};
diff --git a/old_examples/shared/drivers/ethernet/packet.h b/old_examples/shared/drivers/ethernet/packet.h
deleted file mode 100644
index 54ceb48e5c60f84320a49586944cfbc20bdb33cb..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/ethernet/packet.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <cstdint>
-#include <cstdio>
-
-// UDP packet header descriptor
-typedef struct __attribute__((packed))
-{
- uint32_t ipAddress;
- uint16_t port;
- size_t payloadSize;
-} packet_header_t;
diff --git a/old_examples/shared/drivers/interrupt/InterruptManager.cpp b/old_examples/shared/drivers/interrupt/InterruptManager.cpp
deleted file mode 100644
index e85020369072c7ac4da979a8cd24d4bad9ff513c..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/interrupt/InterruptManager.cpp
+++ /dev/null
@@ -1,207 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "InterruptManager.h"
-
-#include <e20/e20.h>
-
-#include <iostream>
-
-#include "miosix.h"
-
-miosix::FixedEventQueue<5> eq;
-
-void* thread_eq_interrupt_manager(void*)
-{
- eq.run();
- return NULL;
-}
-
-InterruptManager::InterruptManager() : interrupts{NULL}
-{
- pthread_t t;
- pthread_create(&t, NULL, thread_eq_interrupt_manager, NULL);
-}
-
-void InterruptManager::OnInterruptEvent(unsigned n)
-{
- IGenericInterrupt* const ptr =
- InterruptManager::getInstance().interrupts[n];
- if (ptr)
- ptr->OnReciveInt();
-}
-
-void __attribute__((naked)) EXTI0_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z20EXTI0_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI0_IRQHandlerImpl()
-{
- EXTI->PR = EXTI_PR_PR0;
- if (eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 0)) ==
- false)
- ;
-}
-
-void __attribute__((naked)) EXTI1_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z20EXTI1_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI1_IRQHandlerImpl()
-{
- EXTI->PR = EXTI_PR_PR1;
- if (eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 1)) ==
- false)
- ;
-}
-
-void __attribute__((naked)) EXTI2_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z20EXTI2_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI2_IRQHandlerImpl()
-{
- EXTI->PR = EXTI_PR_PR2;
- if (eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 2)) ==
- false)
- ;
-}
-
-void __attribute__((naked)) EXTI3_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z20EXTI3_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI3_IRQHandlerImpl()
-{
- EXTI->PR = EXTI_PR_PR3;
- if (eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 3)) ==
- false)
- ;
-}
-
-void __attribute__((naked)) EXTI4_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z20EXTI4_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI4_IRQHandlerImpl()
-{
- EXTI->PR = EXTI_PR_PR4;
- if (eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 4)) ==
- false)
- ;
-}
-
-void __attribute__((naked)) EXTI9_5_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z22EXTI9_5_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI9_5_IRQHandlerImpl()
-{
- const uint32_t status = EXTI->PR;
- EXTI->PR = status;
- if (status & GetPendingBitForLine(5) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 5)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(6) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 6)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(7) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 7)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(8) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 8)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(9) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 9)) ==
- false)
- {
- }
-}
-
-void __attribute__((naked)) EXTI15_10_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z24EXTI15_10_IRQHandlerImplv");
- restoreContext();
-}
-
-void __attribute__((used)) EXTI15_10_IRQHandlerImpl()
-{
- const uint32_t status = EXTI->PR;
- EXTI->PR = status;
- if (status & GetPendingBitForLine(10) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 10)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(11) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 11)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(12) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 12)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(13) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 13)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(14) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 14)) ==
- false)
- {
- }
- if (status & GetPendingBitForLine(15) &&
- eq.IRQpost(std::tr1::bind(InterruptManager::OnInterruptEvent, 15)) ==
- false)
- {
- }
-}
diff --git a/old_examples/shared/drivers/memory/FlashController.h b/old_examples/shared/drivers/memory/FlashController.h
deleted file mode 100644
index 79f55fae3c78937bf463fb58a4a0b02070729e5b..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/memory/FlashController.h
+++ /dev/null
@@ -1,678 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Matteo Piazzolla
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Singleton.h>
-#include <diagnostic/FaultCounter.h>
-#include <diagnostic/NewLogger.h>
-#include <drivers/memory/FlashDriverInclude.h>
-#include <miosix.h>
-
-using logging::logger;
-
-// Forward declaration
-namespace testing
-{
-namespace flashmemorytests
-{
-template <typename>
-class FlashTest;
-}
-} // namespace testing
-
-namespace flashmemory
-{
-
-/*
- 16 pagine da 256 byte
- 1000000 pagine in un banco
- 62500 sottosettori
- */
-static const uint16_t CONTROLLER_VERSION = 1;
-static const uint16_t BOARD_ID = 0xAB; // TBD
-
-// BLOCK_SIZE deve essere un divisore di SUBSECTOR_SIZE
-static const uint32_t BLOCK_SIZE = PAGE_SIZE;
-
-/** Number of flash data blocks that fit in each sector.
- * First block of each sector is reserved for the header.
- * In the first sector, the entire first subsector is reserved for the header.
- */
-static const uint32_t BLOCKS_PER_SECTOR = SECTOR_SIZE / BLOCK_SIZE;
-static const uint32_t BLOCKS_NUM = BLOCKS_PER_SECTOR * SECTORS_NUM;
-
-static const uint32_t FIRST_BOOT_KEY = 0xF135B007;
-static const uint32_t READ_ONLY_KEY = 0x3EAD0271;
-
-// How many sectors should we attempt to write in before we give up?
-static const int MAX_SECTOR_ITERATIONS = 50;
-
-struct FlashHeader
-{
- const uint16_t version = CONTROLLER_VERSION;
- const uint16_t board_id = BOARD_ID;
-
- uint32_t first_boot = FIRST_BOOT_KEY;
- uint32_t start_index = 0;
- uint32_t read_only = 0;
-
- bool operator==(const FlashHeader& other) const
- {
- return memcmp(this, &other, sizeof(FlashHeader)) == 0;
- }
-
- bool operator!=(const FlashHeader& other) const
- {
- return memcmp(this, &other, sizeof(FlashHeader)) != 0;
- }
-};
-
-static const uint8_t SECTOR_EMPTY = 0x55;
-static const uint8_t SECTOR_WRITTEN = 0x44;
-static const uint8_t SECTOR_CORRUPT = 0x00;
-
-struct SectorHeader
-{
- uint8_t content = SECTOR_CORRUPT; // Either one of SECTOR_EMPTY,
- // SECTOR_WRITTEN, SECTOR_CORRUPT
- bool operator==(const SectorHeader& other) const
- {
- return memcmp(this, &other, sizeof(SectorHeader)) == 0;
- }
-};
-
-static const uint32_t FLASH_BUFFER_SIZE =
- (BLOCK_SIZE) - (sizeof(uint32_t) * 2 + sizeof(uint16_t));
-
-struct FlashDataBlock
-{
- uint32_t id;
- uint32_t timestamp;
- uint8_t buffer[FLASH_BUFFER_SIZE];
- uint16_t crc;
-
- bool operator==(const FlashDataBlock& other) const
- {
- return memcmp(this, &other, sizeof(FlashDataBlock)) == 0;
- }
-
- bool operator!=(const FlashDataBlock& other) const
- {
- return memcmp(this, &other, sizeof(FlashDataBlock)) != 0;
- }
-};
-
-template <typename MemoryBus>
-class FlashController : Singleton<FlashController<MemoryBus>>
-{
- friend class Singleton<FlashController<MemoryBus>>;
-
- template <typename>
- friend class testing::flashmemorytests::FlashTest;
-
- typedef FlashController<MemoryBus> FlashControllerType;
- typedef FlashDriver<MemoryBus> FlashDriverType;
-
-public:
- enum class Status
- {
- WRITE_READY = 0,
- READ_ONLY = 1,
- INITIALIZATION_ERROR = 2,
- WRITE_ERROR = 3
- };
-
- void init()
- {
- status_ = Status::INITIALIZATION_ERROR;
- block_index_ = SUBSECTOR_SIZE / BLOCK_SIZE;
-
- FlashHeader header;
-
- if (!readFlashHeader(&header))
- {
- logger.critical(logtag(), "Cannot read flash header.");
- sFaultCounterMgr->Increment(Fault::F_MASTER_FLASH_CNTRL_FAULT);
- return;
- }
-
- if (header.read_only == READ_ONLY_KEY)
- {
- flash_->setReadOnly();
- status_ = Status::READ_ONLY;
- }
- else
- {
- if (header.first_boot == FIRST_BOOT_KEY)
- {
- // Update the first boot key
- header.first_boot = 0;
-
- if (!writeFlashHeader(header, false))
- {
- logger.critical(logtag(),
- "Could not update first boot value.");
- sFaultCounterMgr->Increment(
- Fault::F_MASTER_FLASH_CNTRL_FAULT);
- return;
- }
-
- if (header.start_index >= block_index_)
- {
- block_index_ = header.start_index;
- }
- status_ = Status::WRITE_READY;
- }
- else
- {
- if (recoverFromReboot())
- {
- status_ = Status::WRITE_READY;
- }
- else
- {
- logger.critical(logtag(),
- "Couldn't find sector to write in.");
- sFaultCounterMgr->Increment(
- Fault::F_MASTER_FLASH_CNTRL_FAULT);
- }
- }
- }
- }
-
- FlashController::Status getStatus() { return status_; }
-
- uint32_t getBlockIndex() { return block_index_; }
-
- /**
- * @brief Writes a block onto the flash memory.
- *
- * @param block The block to be written on the flash
- */
- bool writeDataBlock(FlashDataBlock* block_buf)
- {
-
- if (status_ != Status::WRITE_READY)
- {
- logger.error(logtag(), "Writing is not enabled.");
- return false;
- }
-
- if (block_index_ >= BLOCKS_NUM)
- {
- logger.critical(logtag(), "Memory is full.");
- sFaultCounterMgr->Increment(Fault::F_MASTER_FLASH_CNTRL_FAULT);
- status_ = Status::WRITE_ERROR;
- return false;
- }
-
- // Enforce size <= BLOCK_SIZE
- size_t size = sizeof(FlashDataBlock) < BLOCK_SIZE
- ? sizeof(FlashDataBlock)
- : BLOCK_SIZE;
-
- // Beginning of a new sector. Check if we can write in it and update its
- // header
- if (block_index_ % BLOCKS_PER_SECTOR == 0)
- {
- if (!gotoNewSector())
- {
- logger.critical(logtag(), "Could not find sector to write in.");
- status_ = Status::WRITE_ERROR;
- sFaultCounterMgr->Increment(Fault::F_MASTER_FLASH_CNTRL_FAULT);
- return false;
- }
- }
-
- uint8_t result;
- flash_->write(&result, block_index_ * BLOCK_SIZE,
- reinterpret_cast<uint8_t*>(block_buf), size);
- block_index_++;
-
- return result == RESULT_OK;
- }
-
- static bool readFlashHeader(FlashHeader* header)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
- flash->read(&result, 0, (uint8_t*)header, sizeof(FlashHeader));
- return result == RESULT_OK;
- }
-
- /**
- * Saves (and overwrites) the header in the first address on the memory.
- * @param header
- */
- static bool writeFlashHeader(const FlashHeader& header, bool erase = true)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
- if (erase)
- {
- flash->enableErase();
- flash->eraseSubsector(&result, 0);
- if (result != OpResultFlags::RESULT_OK)
- {
- return false;
- }
- }
- uint32_t size = sizeof(FlashHeader) > SUBSECTOR_SIZE
- ? SUBSECTOR_SIZE
- : sizeof(FlashHeader);
-
- flash->writeAndCheck(&result, 0, (uint8_t*)(&header), size);
- return result == RESULT_OK;
- }
-
- static bool readBlock(uint32_t block_index, uint8_t* buffer)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
-
- flash->read(&result, block_index * BLOCK_SIZE, buffer, BLOCK_SIZE);
- return result == RESULT_OK;
- }
-
- static bool readDataBlock(uint32_t block_index, FlashDataBlock* block)
- {
- // Flash header & sector headers are not *data* blocks.
- if (block_index % BLOCKS_PER_SECTOR == 0 ||
- block_index < SUBSECTOR_SIZE / BLOCK_SIZE)
- {
- return false;
- }
-
- readBlock(block_index, reinterpret_cast<uint8_t*>(block));
- return true;
- }
-
- /**
- * Saves (and overwrites) the header in the first address on the memory.
- * @param header
- */
- static bool writeSectorHeader(uint32_t sector, const SectorHeader& header)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
-
- uint32_t size = sizeof(SectorHeader) > BLOCK_SIZE
- ? BLOCK_SIZE
- : sizeof(SectorHeader);
-
- flash->writeAndCheck(&result, sector * SECTOR_SIZE, (uint8_t*)(&header),
- size);
-
- return result == RESULT_OK;
- }
-
- static bool readSectorHeader(uint32_t sector, SectorHeader* header)
- {
- return readSectorHeader(sector, (uint8_t*)header);
- }
-
- static bool readSectorHeader(uint32_t sector, uint8_t* header_buff)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
- flash->read(&result, SECTOR_SIZE * sector, header_buff,
- sizeof(SectorHeader));
- return result == RESULT_OK;
- }
-
- static bool format()
- {
- uint8_t result;
- logger.warning(logtag(), "THE MEMORY WILL BE FORMATTED IN 5 SECONDS");
- // Thread::sleep(5000);
- logger.info(logtag(), "Erasing...");
- // TODO: Flash leds for a few seconds as a warning
- eraseMemory(&result);
- if (result != OpResultFlags::RESULT_OK)
- {
- logger.error(logtag(), "Error: result=", logging::hex(result));
- return false;
- }
- logger.info(logtag(), "Writing flash header...");
- FlashHeader header = {};
- header.first_boot = FIRST_BOOT_KEY;
- // header.magic_word = MAGIC_WORD;
-
- if (!writeFlashHeader(header, false))
- {
- logger.error(logtag(), "Error: result=", logging::hex(result));
- return false;
- }
- logger.info(logtag(), "Writing sector headers...");
- SectorHeader sheader;
- sheader.content = SECTOR_EMPTY;
-
- for (uint32_t sector = 1; sector < SECTORS_NUM; sector++)
- {
- if (!writeSectorHeader(sector, sheader))
- {
- logger.error(logtag(), "Error: result=", logging::hex(result),
- " sector: ", sector);
- return false;
- }
- }
- logger.info(logtag(), "Success!");
-
- return true;
- }
-
- /**
- * @brief Formats the memory.
- * Use this only if the filesystem is in a good state: this fuction
- * reads every sector header and erases only sector where
- * header content != SECTOR_EMPTY
- *
- * @warning Use this only for testing!
- */
- static bool fastFormat()
- {
- logger.warning(logtag(), "!!!THE MEMORY IS ABOUT TO BE FORMATTED!!!\n");
-
- logger.info(logtag(), "Formatting...\n");
- // TODO: Flash leds for a few seconds as a warning
- // Always erase the first sector
- if (!erase(0, SUBSECTORS_PER_SECTOR))
- {
- logger.error(logtag(), "Couldn't erase sector 0");
- return false;
- }
-
- // Then erase only the written/broken sectors
- uint32_t s;
- for (s = 1; s < SECTORS_NUM; s++)
- {
- SectorHeader header;
- bool read_result = readSectorHeader(s, &header);
- if (read_result && header.content != SECTOR_EMPTY)
- {
- // Erase data in this sector
- if (!erase(s * SUBSECTORS_PER_SECTOR,
- (s + 1) * SUBSECTORS_PER_SECTOR))
- {
- logger.error(logtag(), "Couldn't erase sector ", s);
- return false;
- }
-
- // Rewrite the header
- SectorHeader sheader;
- sheader.content = SECTOR_EMPTY;
- if (!writeSectorHeader(s, sheader))
- {
- logger.error("Error writing sector header in sector ", s);
- return false;
- }
- }
- else if (!read_result)
- {
- logger.error(logtag(), "Error reading sector header in sector ",
- s);
- return false;
- }
- }
-
- // Format the memory
- FlashHeader header{};
- header.first_boot = FIRST_BOOT_KEY;
-
- if (!writeFlashHeader(header, false))
- {
- logger.error(logtag(), "Couldn't write flash header.");
- return false;
- }
-
- return true;
- }
-
- static bool eraseMemory(uint8_t* result)
- {
- return erase(0, SUBSECTORS_NUM);
- }
-
- /**
- * Erases the memory between the given subsectors
- * Only erases a subsector if data has been written into it,
- * to avoid wasting erase cycles.
- *
- * @brief Erases The memory between the given bounds.
- * @param result Erase successful or not
- * @param from Address belonging to the first subsector to be erased
- * @param to Address belonging to the last subsector to be erased
- * @return
- */
- static bool erase(uint32_t from_subsector, uint32_t to_subsector)
- {
- uint8_t result;
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
- uint8_t* buffer = new uint8_t[PAGE_SIZE];
-
- std::stringstream
- stream; // To save strings to write in a single log line
- stream << "Erasing subsectors: ";
-
- // Erase from the start of the subsector corresponding to "from"
- uint32_t from_addr = from_subsector * SUBSECTOR_SIZE;
-
- // To the end of the subsector corresponding to "to".
- uint32_t to_addr = to_subsector * SUBSECTOR_SIZE;
-
- // Read memory in blocks of PAGE_SIZE, if a byte is != 0xFF, erase the
- // subsector and start reading again from the next one.
- while (from_addr < to_addr)
- {
- flash->read(&result, from_addr, buffer, PAGE_SIZE);
-
- if (result == OpResultFlags::RESULT_OK)
- {
- bool erase = false;
- for (uint32_t i = 0; i < PAGE_SIZE; i++)
- {
- erase = buffer[i] != 0xFF;
-
- if (erase)
- break;
- }
-
- if (erase)
- {
- stream << from_addr / SUBSECTOR_SIZE << ", ";
-
- flash->enableErase();
- flash->eraseSubsector(&result, from_addr);
- if (result == OpResultFlags::RESULT_OK)
- {
- // Move to the beginning of the next subsector
- from_addr =
- (from_addr / SUBSECTOR_SIZE + 1) * SUBSECTOR_SIZE;
- }
- else
- {
- logger.error(logtag(),
- "Error erasing subsector: result=0x",
- logging::hex(result));
- break;
- }
- }
- else
- {
- from_addr = from_addr + PAGE_SIZE;
- }
- }
- else
- {
- logger.error(logtag(), "Error reading memory: result=0x",
- logging::hex(result));
- break;
- }
- }
-
- stream << "--";
-
- logger.info(logtag(), stream.str());
- delete buffer;
-
- return from_addr >= to_addr;
- }
-
- static bool isMemoryClean(uint8_t* result)
- {
- FlashDriverType* flash = Singleton<FlashDriverType>::getInstance();
- uint8_t buffer[BLOCK_SIZE];
-
- // Check from the start of the subsector corresponding to "from"
- uint32_t addr = SUBSECTOR_SIZE;
-
- bool clean = true;
- while (addr < MEMORY_SIZE)
- {
- if (addr % SECTOR_SIZE == 0)
- {
- SectorHeader header;
- bool read_result =
- readSectorHeader(addr / SECTOR_SIZE, &header);
- if (!read_result || header.content != SECTOR_EMPTY)
- {
- logger.warning(logtag(), "Wrong sector header @", addr);
- clean = false;
- }
- }
- else
- {
- flash->read(result, addr, buffer, BLOCK_SIZE);
- if (*result == OpResultFlags::RESULT_OK)
- {
- for (uint32_t i = 0; i < BLOCK_SIZE; i++)
- {
- if (buffer[i] != 0xFF)
- {
- logger.warning(logtag(), "Dirty block @", addr);
- clean = false;
- break;
- }
- }
- }
- else
- {
- logger.warning(logtag(), "Error reading at %d\n", addr);
- break;
- }
- }
-
- addr = addr + BLOCK_SIZE;
- }
-
- if (clean)
- {
- logger.info(logtag(), "Memory is clean.");
- }
- return clean;
- }
-
-private:
- FlashController() { flash_ = Singleton<FlashDriverType>::getInstance(); }
-
- /**
- * @brief Restores the state after a reboot.
- *
- * Restores the state after a reboot.
- * Sequentially search for the first empty sector and update block_index_
- * accordingly
- *
- * @return Empty sector found or not
- */
- bool recoverFromReboot()
- {
- // Start from the second sector
- uint32_t sector = 1;
- SectorHeader header;
-
- do
- {
- bool r = readSectorHeader(sector, &header);
- if (r && header.content == SECTOR_EMPTY)
- {
- block_index_ = sector * BLOCKS_PER_SECTOR;
- return true;
- }
- } while (++sector < SECTORS_NUM);
-
- return false;
- }
-
- /**
- * Updates block_index_ to point to the next available sector.
- *
- * @return True if a new sector is found
- */
- bool gotoNewSector()
- {
- uint32_t sector = block_index_ / BLOCKS_PER_SECTOR;
- SectorHeader readHeader, writeHeader;
-
- // Look for an empty sector
- bool read_result;
- int i = 0;
- do
- {
- read_result = readSectorHeader(sector, &readHeader);
-
- } while (((read_result && readHeader.content != SECTOR_EMPTY) ||
- !read_result) &&
- ++sector < SECTORS_NUM && ++i < MAX_SECTOR_ITERATIONS);
-
- block_index_ = sector * BLOCKS_PER_SECTOR;
-
- if (read_result && readHeader.content == SECTOR_EMPTY)
- {
- writeHeader.content = SECTOR_WRITTEN;
-
- if (!writeSectorHeader(sector, writeHeader))
- {
- logger.error(logtag(), "Error writing sector header.");
- return false;
- }
- block_index_++;
- }
- else
- {
- logger.error(logtag(),
- "Error: could not find empty sector to write in.");
- return false;
- }
-
- return true;
- }
-
- static std::string logtag() { return "FlashCTRL"; }
-
- FlashDriverType* flash_;
- uint32_t block_index_ = 0;
- // Value will be changed if initialization is successful
- Status status_ = Status::INITIALIZATION_ERROR;
-};
-
-} // namespace flashmemory
diff --git a/old_examples/shared/drivers/memory/FlashDriver.h b/old_examples/shared/drivers/memory/FlashDriver.h
deleted file mode 100644
index 2fedca894523e1f8417085f38a7dcd6e2baaa196..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/memory/FlashDriver.h
+++ /dev/null
@@ -1,596 +0,0 @@
-/* Copyright (c) 2020 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Singleton.h>
-#include <diagnostic/NewLogger.h>
-#include <miosix.h>
-
-#include <string>
-
-using miosix::Mode;
-using miosix::Thread;
-
-using logging::logger;
-
-namespace flashmemory
-{
-
-static const uint32_t PAGES_PER_SUBSECTOR = 16U;
-static const uint32_t PAGES_PER_SECTOR = 256U;
-static const uint32_t SUBSECTORS_PER_SECTOR = 16U;
-
-static const uint32_t SUBSECTORS_NUM = 16384U;
-static const uint32_t SECTORS_NUM = 1024U;
-static const uint32_t PAGE_SIZE = 256U;
-
-static const uint32_t SUBSECTOR_SIZE = PAGE_SIZE * PAGES_PER_SUBSECTOR;
-static const uint32_t SECTOR_SIZE = PAGE_SIZE * PAGES_PER_SECTOR;
-
-static const uint32_t BANK_SIZE = SECTOR_SIZE * SECTORS_NUM / 2;
-static const uint32_t MEMORY_SIZE = SECTOR_SIZE * SECTORS_NUM;
-
-/**
- * @brief Definitions for results of various flash operations.
- *
- * Definitions for result flags of various flash operations.
- */
-enum OpResultFlags
-{
- RESULT_OK = 0x00,
-
- RESULT_F_OUT_OF_MEMORY = 0x01,
- RESULT_F_CHECK_FAIL = 0x04,
-
- // Bits reserved for future use
- RESULT_F_UNUSED_1 = 0x08,
- RESULT_F_UNUSED_2 = 0x40,
- RESULT_F_UNUSED_3 = 0x80,
-
- /**
- * These bits are in the same positions of the corresponding bits in the
- * FLAG STATUS REGISTER
- */
- RESULT_F_PROTECTION_ERROR = 0x02,
- RESULT_F_PROGRAM_ERROR = 0x10,
- RESULT_F_ERASE_ERROR = 0x20
-};
-
-/*
- * TODO:
- * -Controlla significato bit Vpp nel Flag status register
- * -Casi in cui eseguire _write_disable()
- * -Velocizzare il clock software per il factory reset
- * -Controlla se bisogna davvero leggere due volte il flag_status_register per
- * vedere se una scrittura ad un registro e' stata completata
- *
- */
-
-template <typename Bus>
-class FlashDriver : Singleton<FlashDriver<Bus>>
-{
- typedef Singleton<FlashDriver<Bus>> SingletonType;
-
- friend class Singleton<FlashDriver<Bus>>;
-
- template <typename>
- friend class FlashDriverTest;
-
-public:
- /**
- * @brief Read n bytes into a buffer, starting from the specified address
- *
- * @param result
- * @param address Starting address
- * @param buf Buffer to read data into
- * @param size Number of bytes to read
- */
- void read(uint8_t* result, uint32_t address, uint8_t* buf, uint32_t size)
- {
- if (address + size > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- uint32_t rsize;
- if (address < BANK_SIZE)
- rsize = std::min(size, BANK_SIZE - address);
- else
- rsize = size;
-
- uint8_t addr_buf[4];
- addrToBuf(addr_buf, address);
-
- Bus::read(READ, addr_buf, buf, 4, rsize);
-
- size -= rsize;
-
- // This means that we reached the end of the first die but we still need
- // to read some data.
- if (size > 0)
- {
- address += rsize;
- buf += rsize;
-
- addrToBuf(addr_buf, address);
-
- // Read the remaining bytes
- Bus::read(READ, addr_buf, buf, 4, size);
- }
-
- *result = RESULT_OK;
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address.
- *
- * @param address
- * @param data
- * @param size
- */
- void write(uint8_t* result, uint32_t address, uint8_t* data, uint32_t size)
- {
- // Do not write outside of the memory
- if (address + size > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- uint8_t addr_buf[4], status;
-
- uint32_t next_page, wsize;
-
- do
- {
- next_page = (address / 256) * 256 + 256;
-
- wsize = std::min(next_page - address, size);
-
- addrToBuf(addr_buf, address);
- writeEnable();
- Bus::write(PROGRAM_PAGE, addr_buf, data, 4, wsize);
-
- do
- {
- status = readFlagStatusReg();
- } while ((status & FSR_PRG_ERS_CTRL) == 0);
-
- data += wsize;
- size -= wsize;
- address = next_page;
-
- *result = status & (FSR_PROGRAM | FSR_PROTECTION);
- } while (size > 0 && *result == RESULT_OK);
-
- // Clear flag status register if an error occurred
- if (*result != RESULT_OK)
- {
- clearFlagStatusReg();
-
- // Manually reset write_enable latch
- if ((*result & RESULT_F_PROTECTION_ERROR) > 0)
- {
- writeDisable();
- }
- }
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address, then
- * checks if everything was written correctly.
- *
- * @param address
- * @param data
- * @param size
- */
- void writeAndCheck(uint8_t* result, uint32_t address, uint8_t* data,
- uint32_t size)
- { // TODO: size_t
- write(result, address, data, size);
- if (*result == RESULT_OK)
- {
- uint8_t* check = new uint8_t[size];
- read(result, address, check, size);
- for (uint32_t i = 0; i < size; i++)
- {
- if (*check++ != *data++)
- {
- // Something was not written/read correctly.
- *result = RESULT_F_CHECK_FAIL;
- break;
- }
- }
- }
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address, only
- * if the provided data fits in a single page.
- *
- * Writes data on the flash starting from the specified address, only
- * if the provided data fits in a single page. If too much data is provided
- * nothing will be written and result will be set to RESULT_F_OUT_OF_MEMORY
- *
- * @param result
- * @param address
- * @param data
- * @param size
- */
- void programPage(uint8_t* result, uint32_t address, uint8_t* data,
- uint32_t size)
- {
- // Do now wrap around a page and do not try to write outside of the
- // memory
- uint32_t next_page = (address / 256) * 256 + 256;
- if (address + size > next_page || address > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- uint8_t addr_buf[4], status;
- addrToBuf(addr_buf, address);
-
- writeEnable();
- Bus::write(PROGRAM_PAGE, addr_buf, data, 4, size);
-
- do
- {
- status = readFlagStatusReg();
- } while ((status & FSR_PRG_ERS_CTRL) == 0);
-
- *result = status & (FSR_PROGRAM | FSR_PROTECTION);
-
- // Clear flag status register if an error has been encountered
- if (*result != RESULT_OK)
- {
- clearFlagStatusReg();
-
- // Manually reset write_enable latch
- if ((*result & RESULT_F_PROTECTION_ERROR) > 0)
- {
- writeDisable();
- }
- }
- }
-
- /**
- * @brief Enables or disables read only mode
- */
- void setReadOnly(bool readonly = true) { read_only_ = readonly; }
-
- bool isReadOnly() const { return read_only_; }
-
- /**
- * @brief Enable the next erase operation. Call this before every erase op.
- */
- void enableErase() { writeEnable(); }
-
- /**
- * @brief Erases the subsector containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- *
- * @warning Estimated execution time is slightly less than 1 second.
- *
- * @param result
- * @param address
- */
- void eraseSubsector(uint8_t* result, uint32_t address)
- {
- erase(result, SUBSECTOR_ERASE, address);
- }
-
- /**
- * @brief Erases the sector containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- * @warning Estimated execution time is about 2 seconds.
- *
- * @param result
- * @param address
- */
- void eraseSector(uint8_t* result, uint32_t address)
- {
- erase(result, SECTOR_ERASE, address);
- }
-
- /**
- * @brief Erases the entire die containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- * @warning Estimated execution time is more than 4 minutes.
- *
- * @param result
- * @param die: 0 to erase the first die, 1 to erase the second.
- */
- void eraseDie(uint8_t* result, uint8_t die)
- {
- if (die == 0)
- {
- erase(result, DIE_ERASE, 0);
- }
- else if (die == 1)
- {
- erase(result, DIE_ERASE, BANK_SIZE);
- }
- }
-
- /**
- * Reads id information for this flash memory.
- * @param buf Buffer with at least 20 bytes
- */
- void readId(uint8_t* buf) { Bus::read(READ_ID, buf, 20); }
-
- /**
- * @brief Software reset for the memory. All volatile bits are set to their
- * default value.
- */
- void softReset()
- {
- Bus::write(RESET_ENABLE);
- usleep(5);
- Bus::write(RESET_MEMORY);
- waitUntilReady();
- }
-
- /**
- * If the flash memory is in a bad state and can't be recovered by any
- * other means, run this, then set CONFIG_REGISTER to 0xFFFF.
- */
- template <class CS, class MOSI, class CLK>
- static void factoryReset()
- {
- {
- miosix::FastInterruptDisableLock dLock;
- CS::mode(Mode::OUTPUT);
- MOSI::mode(Mode::OUTPUT);
- CLK::mode(Mode::OUTPUT);
- }
- MOSI::high();
- Thread::sleep(20);
-
- factoryResetSequence<CS, CLK>(7);
- factoryResetSequence<CS, CLK>(13);
- factoryResetSequence<CS, CLK>(17);
- factoryResetSequence<CS, CLK>(25);
- factoryResetSequence<CS, CLK>(33);
-
- MOSI::low();
- Thread::sleep(50);
- MOSI::high();
- factoryResetSequence<CS, CLK>(8);
-
- MOSI::low();
- CS::low();
- }
-
-private:
- FlashDriver()
- {
- waitUntilReady();
-
- uint8_t buf[20];
- readId(buf);
-
- if (buf[0] != 0x20)
- {
- logger.critical(logtag(), "Wrong id on FlashDriver instantiation");
- }
-
- writeStatusReg(0x00);
-
- clearFlagStatusReg();
-
- uint16_t config = readConfigReg();
-
- // Last bit to 0 to enable 4 byte address mode
- if (config != 0xFFFE)
- writeConfigReg(0xFFFE);
- }
-
- void erase(uint8_t* result, uint8_t erase_cmd, uint32_t address)
- {
- if (address > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- uint8_t addr_buf[4], status;
- addrToBuf(addr_buf, address);
- Bus::write(erase_cmd, addr_buf, 4);
-
- do
- {
- status = readFlagStatusReg();
- } while ((status & FSR_PRG_ERS_CTRL) == 0);
-
- *result = status & (FSR_ERASE | FSR_PROTECTION);
-
- // Clear flag status register if an error has been encountered
- if (*result != RESULT_OK)
- {
- clearFlagStatusReg();
-
- // Manually reset write_enable latch
- if ((*result & RESULT_F_PROTECTION_ERROR) > 0)
- {
- writeDisable();
- }
- }
- }
-
- /**
- * @brief Checks if a program operation is still in progress.
- * @param result
- */
- bool isBusy() { return readFlagStatusReg() & FSR_PRG_ERS_CTRL; }
-
- /**
- * @brief Waits until the memory is ready to perform a new write/erase op.
- * @param result
- */
- void waitUntilReady()
- {
- while ((readFlagStatusReg() & FSR_PRG_ERS_CTRL) == 0)
- {
- }
- }
-
- uint8_t readStatusReg()
- {
- uint8_t ret = Bus::read(READ_STATUS_REG);
- return ret;
- }
-
- void writeStatusReg(uint8_t val)
- {
- writeEnable();
- Bus::write(WRITE_STATUS_REG, val);
- writeDisable();
- waitUntilReady();
- }
-
- uint8_t readFlagStatusReg()
- {
- uint8_t ret = Bus::read(READ_FLAG_STATUS_REG);
- return ret;
- }
-
- void clearFlagStatusReg() { Bus::write(CLEAR_FLAG_STATUS_REG); }
-
- uint16_t readConfigReg()
- {
- uint8_t buf[2];
- Bus::read(READ_NV_CONFIG_REG, buf, 2);
-
- uint16_t res = buf[0] | (buf[1] << 8);
-
- return res;
- }
-
- void writeConfigReg(uint16_t val)
- {
- /*
- * Mask some of the bits of the config register because
- * we don't want to change them by accident.
- */
- val = val | 0x0FEC;
-
- uint8_t buf[2];
- buf[0] = val & 0xFF;
- buf[1] = (val >> 8) & 0xFF;
-
- writeEnable();
- Bus::write(WRITE_NV_CONFIG_REG, buf, 2);
- writeDisable();
- waitUntilReady();
- }
-
- void writeEnable()
- {
- if (!read_only_)
- {
- Bus::write(WRITE_ENABLE);
- }
- }
-
- void writeDisable() { Bus::write(WRITE_DISABLE); }
-
- static void addrToBuf(uint8_t* buf, uint32_t addr)
- {
- for (int i = 0; i < 4; i++)
- {
- buf[3 - i] = (addr >> 8 * i) & 0xFF;
- }
- }
-
- template <class CS, class CLK>
- static void factoryResetSequence(int cycles)
- {
- CS::low();
- Thread::sleep(5);
- for (int i = 0; i < cycles; i++)
- {
- CLK::high();
- Thread::sleep(5);
- CLK::low();
- Thread::sleep(5);
- }
- CS::high();
- Thread::sleep(20);
- }
-
- static std::string logtag() { return "FLASH_DRIVER"; }
-
- enum Commands
- {
- READ_ID = 0x9F,
-
- WRITE_ENABLE = 0x06,
- WRITE_DISABLE = 0x04,
-
- READ_STATUS_REG = 0x05,
- WRITE_STATUS_REG = 0x01,
-
- READ_FLAG_STATUS_REG = 0x70,
- CLEAR_FLAG_STATUS_REG = 0x50,
-
- // non-volatile configuration register
- READ_NV_CONFIG_REG = 0xB5,
- WRITE_NV_CONFIG_REG = 0xB1,
-
- // volatile configuration register
- WRITE_VOL_CONFIG_REG = 0x85,
- READ_VOL_CONFIG_REG = 0x81,
-
- READ_EXT_ADDRESS_REG = 0xC8,
- WRITE_EXT_ADDRESS_REG = 0xC5,
-
- RESET_ENABLE = 0x66,
- RESET_MEMORY = 0x99,
-
- READ = 0x03,
- PROGRAM_PAGE = 0x02,
-
- SUBSECTOR_ERASE = 0x20,
- SECTOR_ERASE = 0xD8,
- DIE_ERASE = 0xC4
- };
-
- bool read_only_ = false;
-
- /**
- * Flag status register bit definitions
- */
- static const uint8_t FSR_ADDRESSING_MODE = 0x01;
- static const uint8_t FSR_PROTECTION = 0x02;
- static const uint8_t FSR_PROGRAM_SUSPEND = 0x04;
- static const uint8_t FSR_VPP = 0x08;
- static const uint8_t FSR_PROGRAM = 0x10;
- static const uint8_t FSR_ERASE = 0x20;
- static const uint8_t FSR_ERASE_SUSPEND = 0x40;
- static const uint8_t FSR_PRG_ERS_CTRL = 0x80;
-};
-
-} // namespace flashmemory
diff --git a/old_examples/shared/drivers/memory/FlashDriverInclude.h b/old_examples/shared/drivers/memory/FlashDriverInclude.h
deleted file mode 100644
index 79db21e808857c14b16957e1c4b843d8c63c14cc..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/memory/FlashDriverInclude.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#ifdef FLASH_TEST
-
-#include <flashmemory/mockup/FlashDriver.h>
-
-#else
-
-#include <drivers/memory/FlashDriver.h>
-
-#endif /* FLASH_TEST */
diff --git a/old_examples/shared/drivers/memory/MultiFlashController.cpp b/old_examples/shared/drivers/memory/MultiFlashController.cpp
deleted file mode 100644
index cd7f967c195527dc0d18afbaa28459732c52e123..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/memory/MultiFlashController.cpp
+++ /dev/null
@@ -1,100 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "MultiFlashController.h"
-
-#include <Singleton.h>
-#include <diagnostic/NewLogger.h>
-
-using logging::logger;
-/* stub crc class */
-
-namespace flashmemory
-{
-class CRCHelper
-{
-public:
- static uint16_t calcCRC16(uint8_t* data, uint32_t size) { return 0xABCD; }
-};
-
-// miosix::Queue<FlashDataBlock,20> MultiFlashController::block_queue_;
-
-MultiFlashController::MultiFlashController() : ActiveObject::ActiveObject()
-{
- flash0_ = Singleton<FlashController<MemoryBus0>>::getInstance();
-
- // block_queue_ = new miosix::Queue<FlashDataBlock, 5>();
-}
-
-MultiFlashController::~MultiFlashController() {}
-
-/**
- * @brief Infinite loop that process the block queue.
- */
-void MultiFlashController::run()
-{
- FlashDataBlock to_flash;
- while (true)
- {
- block_queue_.waitUntilNotEmpty();
-
- block_queue_.get(to_flash);
-
- bool result = true;
-
- result = result && flash0_->writeDataBlock(&to_flash);
-
- // TODO: Also write on 2nd and 3rd flash memory
- // result = result && flash1_->writeBlock(&to_flash);
- // result = result && flash1_->writeBlock(&to_flash);
-
- if (!result)
- {
- logger.error(logtag(), "Error writing blocks!");
- }
- }
-}
-
-/**
- * @brief Insert into the fixed queue a new FlashDataBlock to save in flash.
- *
- * @param buffer data do be saved
- * @param size the size of the data (must be < FLASH_BUFFER_SIZE)
- */
-void MultiFlashController::addData(const uint8_t* buffer, size_t size)
-{
- /* limit data to FLASH_BUFFER_SIZE */
- uint16_t safe_size = (size <= FLASH_BUFFER_SIZE ? size : FLASH_BUFFER_SIZE);
- FlashDataBlock to_save = {};
-
- // create the Flash Data Block.
- to_save.id = block_counter++;
- to_save.timestamp = miosix::getTick();
- memcpy((uint8_t*)to_save.buffer, (uint8_t*)buffer, safe_size);
-
- // TODO crc of the whole block with toSave.crc = 0x0000?
- to_save.crc = CRCHelper::calcCRC16((uint8_t*)to_save.buffer, safe_size);
-
- block_queue_.put(to_save);
-}
-
-} // namespace flashmemory
diff --git a/old_examples/shared/drivers/memory/MultiFlashController.h b/old_examples/shared/drivers/memory/MultiFlashController.h
deleted file mode 100644
index a309f14fc67bbab6dfc5ddfc4651fc891bb07d8b..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/memory/MultiFlashController.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <ActiveObject.h>
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-
-#include "FlashController.h"
-
-using miosix::Gpio;
-
-// Forward declaration
-namespace testing
-{
-namespace flashmemorytests
-{
-template <typename>
-class FlashTest;
-}
-} // namespace testing
-
-namespace flashmemory
-{
-
-class MultiFlashController : public Singleton<MultiFlashController>,
- ActiveObject
-{
- friend class Singleton<MultiFlashController>;
-
- template <typename>
- friend class testing::flashmemorytests::FlashTest;
-
- typedef Gpio<GPIOA_BASE, 5> GpioSck;
- typedef Gpio<GPIOA_BASE, 6> GpioMiso;
- typedef Gpio<GPIOA_BASE, 7> GpioMosi;
- typedef BusSPI<1, GpioMosi, GpioMiso, GpioSck> bus;
-
- typedef Gpio<GPIOC_BASE, 15> CS_FLASH0;
-
-public:
- typedef ProtocolSPI<bus, CS_FLASH0> MemoryBus0;
-
- virtual ~MultiFlashController();
-
- void addData(const uint8_t* buffer, size_t size);
-
-protected:
- void run() override;
-
-private:
- MultiFlashController();
-
- static std::string logtag() { return "MultiFlashCTRL"; }
-
- uint32_t block_counter = 0;
- miosix::Queue<FlashDataBlock, 20> block_queue_;
-
- FlashController<MemoryBus0>* flash0_;
- // FlashController<spi_flash0> flash1; //Change to spi_flash1
- // FlashController<spi_flash0> flash2; //Change to spi_flash2
-};
-
-} // namespace flashmemory
diff --git a/old_examples/shared/drivers/modbus/ExceptionCodes.h b/old_examples/shared/drivers/modbus/ExceptionCodes.h
deleted file mode 100644
index 8818055b8af3201e0842ee7a413060c9850b14b3..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/ExceptionCodes.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include "Common.h"
-
-namespace modbus
-{
-static constexpr uint8_t EXC_ILLEGAL_FUN = 0x01; ///< Illegal function
-static constexpr uint8_t EXC_ILLEGAL_ADDR = 0x02; ///< Illegal data address
-static constexpr uint8_t EXC_ILLEGAL_VAL = 0x03; ///< Illegal data value
-static constexpr uint8_t EXC_SLAVE_FAILURE = 0x04; ///< Slave internal failure
-static constexpr uint8_t ACKNOWLEDGE = 0x05; ///< Acknowledge
-static constexpr uint8_t SLAVE_BUSY = 0x06; ///< Slave busy
-static constexpr uint8_t EXC_MEM_PARITY = 0x08; ///< Memory parity error
-} // namespace modbus
diff --git a/old_examples/shared/drivers/modbus/HooksInterface.h b/old_examples/shared/drivers/modbus/HooksInterface.h
deleted file mode 100644
index d7c691b8b0f56f05bae04e288a30745677810184..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/HooksInterface.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/* Class that provides an interface made by a set of function interface used by
- * Modbus slave engine to handle the server requests.
- * By default the functions will return the error code "function unsupported",
- * user must provide a correct implementation by subclassing this class
- */
-
-#pragma once
-
-#include "Common.h"
-#include "ExceptionCodes.h"
-
-class HooksInterface
-{
-public:
- HooksInterface() {}
-
- ~HooksInterface() {}
-
- virtual uint8_t ReadCoil(bool& value, uint16_t addr)
- {
- return modbus::EXC_ILLEGAL_FUN;
- }
-
- virtual uint8_t WriteCoil(bool value, uint16_t addr)
- {
- return modbus::EXC_ILLEGAL_FUN;
- }
-
- virtual uint8_t ReadRegister(uint16_t& value, uint16_t addr)
- {
- return modbus::EXC_ILLEGAL_FUN;
- }
-
- virtual uint8_t WriteRegister(uint16_t value, uint16_t addr)
- {
- return modbus::EXC_ILLEGAL_FUN;
- }
-
-private:
- HooksInterface(const HooksInterface& other) = delete;
- HooksInterface& operator=(const HooksInterface& other) = delete;
- bool operator==(const HooksInterface& other) = delete;
-};
diff --git a/old_examples/shared/drivers/modbus/Modbus.h b/old_examples/shared/drivers/modbus/Modbus.h
deleted file mode 100644
index 02d7070e89987894b5bcdabdac618fef58774456..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/Modbus.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <slave/SlaveEngine.h>
-#include <slave/SlaveInterface.h>
-
-#include "ExceptionCodes.h"
-#include "PDU.h"
diff --git a/old_examples/shared/drivers/modbus/PDU.cpp b/old_examples/shared/drivers/modbus/PDU.cpp
deleted file mode 100644
index b04742dbb6b74588bd941e88f9d8b0c1e36b26cc..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/PDU.cpp
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "PDU.h"
-
-PDU::PDU() : fuCode(0), pSize(0), pData(nullptr) {}
-
-PDU::PDU(uint8_t fCode, const uint8_t* data, uint8_t dataSize)
- : fuCode(fCode), pSize(dataSize)
-{
-
-#ifndef __NO_EXCEPTIONS
- try
- {
- pData = new uint8_t[pSize];
- }
- catch (std::bad_alloc& exc)
- {
- std::cout << "bad alloc! " << exc.what() << std::endl;
- pData = nullptr;
- }
-#else
- pData = new (std::nothrow) uint8_t[pSize];
-#endif
-
- std::memcpy(pData, data, pSize);
-}
-
-PDU::~PDU()
-{
-
- if (pData != nullptr)
- {
- delete[] pData;
- }
-}
-
-uint8_t PDU::funcCode() const { return fuCode; }
-
-std::pair<uint8_t, uint8_t const*> PDU::data() const
-{
-
- return std::pair<uint8_t, const uint8_t*>(pSize, pData);
-}
diff --git a/old_examples/shared/drivers/modbus/PDU.h b/old_examples/shared/drivers/modbus/PDU.h
deleted file mode 100644
index 5450371ce81cff907ff6f5598f8a081dcab4b8cd..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/PDU.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <stddef.h>
-
-#include "Common.h"
-
-class PDU
-{
-public:
- /**
- * Create a new PDU structure
- * @param fCode: PDU's function code
- * @param data: pointer to data to be put into PDU's data field
- * @param dataSize: size of PDU's data field
- */
- PDU(uint8_t fCode, const uint8_t const* data, uint8_t dataSize);
-
- /**
- * Default constructor does nothing
- */
- PDU();
- ~PDU();
-
- /**
- * @return PDU's function code
- */
- uint8_t funcCode() const;
-
- /**
- * @return std::pair: first field is data size, the second one is
- * a uint8_t const* to internal data.
- */
- std::pair<uint8_t, uint8_t const*> data() const;
-
-private:
- uint8_t fuCode;
- uint8_t pSize;
- uint8_t* pData;
-
- PDU(const PDU& other);
- PDU& operator=(const PDU& other);
- bool operator==(const PDU& other);
-};
diff --git a/old_examples/shared/drivers/modbus/slave/RtuSlave.cpp b/old_examples/shared/drivers/modbus/slave/RtuSlave.cpp
deleted file mode 100644
index 293108d3966bb87fcf18e6714f84437779fe8e8f..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/RtuSlave.cpp
+++ /dev/null
@@ -1,309 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "RtuSlave.h"
-
-using namespace std;
-using namespace miosix;
-
-typedef Gpio<GPIOA_BASE, 2> u2tx;
-typedef Gpio<GPIOA_BASE, 3> u2rx;
-typedef Gpio<GPIOA_BASE, 1> u2rts;
-
-typedef Gpio<GPIOB_BASE, 10> u3tx;
-typedef Gpio<GPIOB_BASE, 11> u3rx;
-typedef Gpio<GPIOB_BASE, 14> u3rts;
-
-void __attribute__((naked)) TIM1_BRK_TIM9_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z13TimIRQHandlerv");
- restoreContext();
-}
-
-void __attribute__((weak)) USART2_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z14Ser2IRQHandlerv");
- restoreContext();
-}
-
-void __attribute__((weak)) USART3_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z14Ser3IRQHandlerv");
- restoreContext();
-}
-
-void __attribute__((used)) TimIRQHandler()
-{
-
- auto inst = Singleton<RtuSlave>::getInstance();
- inst->IRQTimerInterrupt();
-}
-
-void __attribute__((used)) Ser2IRQHandler()
-{
-
- auto inst = Singleton<RtuSlave>::getInstance();
- inst->IRQSerial2Interrupt();
-}
-
-void __attribute__((used)) Ser3IRQHandler()
-{
-
- auto inst = Singleton<RtuSlave>::getInstance();
- inst->IRQSerial3Interrupt();
-}
-
-RtuSlave::RtuSlave() : timer_k(1.0f)
-{
- memset(serial2_data.rxBuffer, 0, 256);
- serial2_data.rxWriteIndx = 0;
- serial2_data.lastEvent = 0;
- serial2_data.rxInProgress = false;
-
- memset(serial2_data.txBuffer, 0, 256);
- serial2_data.txReadIndx = 0;
- serial2_data.txSize = 0;
-
- memset(serial3_data.rxBuffer, 0, 256);
- serial3_data.rxWriteIndx = 0;
- serial3_data.lastEvent = 0;
- serial3_data.rxInProgress = false;
-
- memset(serial3_data.txBuffer, 0, 256);
- serial3_data.txReadIndx = 0;
- serial3_data.txSize = 0;
-
- {
- FastInterruptDisableLock dLock;
- RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
- RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
- RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;
- RCC_SYNC();
-
- u2tx::mode(Mode::ALTERNATE);
- u2rx::mode(Mode::ALTERNATE);
- u2tx::alternateFunction(7);
- u2rx::alternateFunction(7);
- u2rts::mode(Mode::OUTPUT);
- u2rts::low();
-
- u3tx::mode(Mode::ALTERNATE);
- u3rx::mode(Mode::ALTERNATE);
- u3tx::alternateFunction(7);
- u3rx::alternateFunction(7);
- u3rts::mode(Mode::OUTPUT);
- u3rts::low();
- }
-
- /*** USART 2 configuration ***/
- // Enable parity, 9 bit frame length (9th bit is the parity one),
- // use even parity, generate interrupt in case of parity error, tx end,
- // new byte received
- USART2->CR1 |= USART_CR1_M | USART_CR1_PCE | USART_CR1_PEIE |
- USART_CR1_TXEIE | USART_CR1_RXNEIE |
- USART_CR1_TE // enable tx
- | USART_CR1_RE; // enable rx
-
- // CR2 register is left untouched since its default values are OK
-
- USART2->CR3 |= USART_CR3_ONEBIT;
-
- NVIC_SetPriority(USART2_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(USART2_IRQn);
- NVIC_EnableIRQ(USART2_IRQn);
-
- /*** USART 3 configuration, same as USART 2 ***/
- USART3->CR1 |= USART_CR1_M | USART_CR1_PCE | USART_CR1_PEIE |
- USART_CR1_TXEIE | USART_CR1_RXNEIE |
- USART_CR1_TE // enable tx
- | USART_CR1_RE; // enable rx
-
- USART3->CR3 |= USART_CR3_ONEBIT;
-
- NVIC_SetPriority(USART3_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(USART3_IRQn);
- NVIC_EnableIRQ(USART3_IRQn);
-}
-
-RtuSlave::~RtuSlave()
-{
- FastInterruptDisableLock dLock;
-
- TIM9->CR1 &= ~TIM_CR1_CEN;
-
- RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN;
- RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN;
- RCC->APB2ENR &= ~RCC_APB2ENR_TIM9EN;
- RCC_SYNC();
-}
-
-void RtuSlave::setBaud(uint32_t baud)
-{
- uint32_t busFreq = SystemCoreClock;
- if (RCC->CFGR & RCC_CFGR_PPRE1_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 10) & 0x3) + 1);
- }
-
- uint32_t quot = 2 * busFreq / baud; // 2*freq for round to nearest
- USART2->BRR = quot / 2 + (quot & 1);
- USART3->BRR = quot / 2 + (quot & 1);
-
- timerInit(baud);
-}
-
-bool RtuSlave::newDataReceived(uint8_t interface)
-{
- if (interface == 1)
- {
- if (!(serial2_data.rxInProgress) && (serial2_data.rxWriteIndx > 0))
- {
- return true;
- }
- }
-
- if (interface == 2)
- {
- if (!(serial3_data.rxInProgress) && (serial3_data.rxWriteIndx > 0))
- {
- return true;
- }
- }
-
- return false;
-}
-
-pair<uint8_t, unique_ptr<PDU> > RtuSlave::readData(uint8_t fromInterface)
-{
- // uint8_t address = TODO incomplete?
-}
-
-void RtuSlave::timerInit()
-{
- TIM9->DIER |= TIM_DIER_CC1IE | TIM_DIER_CC2IE;
- TIM9->ARR = 0xFFFF;
- TIM9->CCMR1 = 0;
- TIM9->CCMR2 = 0;
- TIM9->CNT = 0;
-
- NVIC_SetPriority(TIM9_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(TIM9_IRQn);
- NVIC_EnableIRQ(TIM9_IRQn);
-
- uint32_t busFreq = SystemCoreClock;
- if (RCC->CFGR & RCC_CFGR_PPRE2_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 13) & 0x3) + 1);
- }
-
- /* Here we calculate the prescaler value based on baud rate value.
- * From the modbus RTU specification we have that, if the baud is greater
- * than 19200, the t1.5 and t3.5 are fixed as the baud is 19200.
- * The timer is set up to accept values multiple of t1.5. Its exact value is
- * given by the formula (1.5 * 11) / baud, since a modbus RTU character is
- * 11 bit long. Here we use an aproximate one (17/baud instead of 16.5/baud)
- * because we do all the calculations with ints.
- * The prescaler value is given by busFreq * t1.5, that is
- * (busFreq * 17) / baud. If this value falls above 65536, the maximum
- * acceptable for the prescaler, the latter is set to 0xFFFF and a suitable
- * value for the correction factor k is computed.
- */
- uint32_t prescaler = (busFreq / min(baud, 19200)) * 17;
- if (prescaler > 65536)
- {
- TIM9->PSC = 0xFFFF;
- timer_k = (static_cast<float>(busFreq) * 17.0f);
- timer_k /= (65536.0f * static_cast<float>(baud));
- }
- else
- {
- TIM9->PSC = prescaler - 1;
- timer_k = 1.0f;
- }
-
- TIM9->EGR |= TIM_EGR_UG; // generate update event to load values
- TIM9->CR1 |= TIM_CR1_CEN;
-}
-
-void RtuSlave::setNewTimeout(uint8_t channel, uint8_t ticks)
-{
- uint16_t incr = static_cast<uint16_t>((ticks * timer_k) + 0.5f);
- switch (channel)
- {
- case 1:
- TIM9->CCMR1 += incr;
- break;
-
- case 2:
- TIM9->CCMR2 += incr;
- break;
-
- default:
- break;
- }
-}
-
-void RtuSlave::IRQTimerInterrupt()
-{
- if (TIM9->SR | TIM_SR_CC1IF)
- {
- TIM9->SR &= ~TIM_SR_CC1IF;
- serial2_data.rxInProgress = false;
- }
-
- if (TIM9->SR | TIM_SR_CC2IF)
- {
- TIM9->SR &= ~TIM_SR_CC2IF;
- serial3_data.rxInProgress = false;
- }
-}
-
-void RtuSlave::IRQSerial2Interrupt()
-{
- if (USART2->SR & USART_SR_RXNE)
- {
- if (!serial2_data.rxInProgress && serial2_data.rxWriteIndx == 0)
- {
- serial2_data.rxInProgress = true;
- }
-
- if (serial2_data.rxInProgress)
- {
- serial2_data.rxBuffer[serial2_data.rxWriteIndx] = USART2->DR;
- serial2_data.rxWriteIndx++;
- // new character has to be received in 1.5*character_time instants
- setNewTimeout(1, 1);
- }
- }
-
- if (USART2->SR & USART_SR_TXE)
- {
- if (serial2_data.txReadIndx < serial2_data.txSize)
- {
- USART->DR = serial2_data.txBuffer[serial2_data.txReadIndx];
- serial2_data.txReadIndx++;
- }
- }
-}
diff --git a/old_examples/shared/drivers/modbus/slave/RtuSlave.h b/old_examples/shared/drivers/modbus/slave/RtuSlave.h
deleted file mode 100644
index 9c38eb66ee1fb25a644adbeb998effd0cca02827..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/RtuSlave.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <memory>
-
-#include "../../Common.h"
-#include "../PDU.h"
-#include "Timer.h"
-
-class RtuSlave : public Singleton<RtuSlave>
-{
-
- friend class Singleton<RtuSlave>;
-
-public:
- ~RtuSlave();
-
- void setBaud(uint32_t baud) throw();
-
- void sendReply(std::unique_ptr<PDU>& data, uint8_t fromInterface);
-
- bool newDataReceived(uint8_t interface);
-
- std::pair<uint8_t, std::unique_ptr<PDU>> readData(uint8_t fromInterface);
-
- void IRQSerial2Interrupt();
- void IRQSerial3Interrupt();
- void IRQTimerInterrupt();
-
-private:
- RtuSlave();
-
- void timerInit();
- void setNewTimeout(uint8_t channel, uint8_t ticks);
-
- typedef struct
- {
- uint8_t rxBuffer[256];
- uint8_t rxWriteIndx;
- uint16_t lastEvent;
- bool rxInProgress;
-
- uint8_t txBuffer[256];
- uint8_t txReadIndx;
- uint8_t txSize;
-
- } interf_data;
-
- interf_data serial2_data;
- interf_data serial3_data;
-
- float timer_k;
-
- RtuSlave(const RtuSlave& other) = delete;
- RtuSlave& operator=(const RtuSlave& other) = delete;
- bool operator==(const RtuSlave& other) = delete;
-};
diff --git a/old_examples/shared/drivers/modbus/slave/SlaveEngine.cpp b/old_examples/shared/drivers/modbus/slave/SlaveEngine.cpp
deleted file mode 100644
index c79dc182c07314069ee6cc4ef2a8fa7f49e8deae..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/SlaveEngine.cpp
+++ /dev/null
@@ -1,321 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "SlaveEngine.h"
-
-using namespace std;
-
-SlaveEngine::SlaveEngine(HooksInterface* hook)
-{
- if (hook == nullptr)
- {
- handlers = new HooksInterface();
- }
- else
- {
- handlers = hook;
- }
-}
-
-SlaveEngine::~SlaveEngine() { delete handlers; }
-
-unique_ptr<PDU> SlaveEngine::ProcessRequest(unique_ptr<PDU> request)
-{
- PDU* response = nullptr;
- uint8_t* data = (request->data()).second;
-
- switch (request->funcCode())
- {
- // read multiple coils
- case 0x01:
- response = DoReadCoils(data);
- break;
-
- // write single coil
- case 0x05:
- response = DoWriteCoil(data);
- break;
-
- // write multiple coils
- case 0x0F:
- response = DoWriteMultipleCoils(data);
- break;
-
- // read holding registers
- case 0x03:
- response = DoReadRegisters(data);
- break;
-
- // write single register
- case 0x06:
- response = DoWriteRegister(data);
- break;
-
- // write multiple registers
- case 0x10:
- response = DoWriteMultipleRegisters(data);
- break;
-
- default:
- // If we arrived here means that the function is not supported, so
- // reply with an exception packet
- uint8_t errc = modbus::EXC_ILLEGAL_FUN;
- uint8_t exceptCode = request->funcCode() + 0x80;
- response = new PDU(exceptCode, &errc, 1);
- }
-
- return unique_ptr<PDU>(response);
-}
-
-PDU* SlaveEngine::DoReadCoils(uint8_t* data)
-{
- /* In this case the packet is made of two fields, each 16 bit long.
- * So, its safe to cast data to uint16_t* and access it as a two element
- * array of uint16_t
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t startAddr = toLittleEndian16(ptr[0]) - 1;
- uint16_t coilsNum = toLittleEndian16(ptr[1]);
-
- if (coilsNum == 0 || coilsNum > 0x07D0)
- {
- uint8_t excCode = modbus::EXC_ILLEGAL_VAL;
- return new PDU(0x81, &excCode, 1);
- }
-
- bool result[coilsNum] = {false};
- uint8_t retVal = 0;
- for (uint16_t i = 0; i < coilsNum; i++)
- {
- retVal = handlers->ReadCoil(result[i], startAddr + i);
- if (retVal != 0)
- {
- break;
- }
- }
-
- // Bad things happened inside ReadCoil, report problem using and exception
- // packet
- if (retVal != 0)
- {
- return new PDU(0x81, &retVal, 1);
- }
-
- // Success, prepare a suitable response. For info about packing process
- // see the specification
- uint8_t byteCnt = coilsNum / 8 + 1;
- uint8_t reply[byteCnt + 1] = {0};
- reply[0] = byteCnt;
-
- for (uint16_t i = 0; i < coilsNum; i++)
- {
- uint8_t chunk = i / 8;
- uint8_t shift = i % 8;
- reply[chunk + 1] |= (result[i] ? 0x01 : 0x00) << shift;
- }
-
- return new PDU(0x01, &reply, byteCnt + 1);
-}
-
-PDU* SlaveEngine::DoWriteCoil(uint8_t* data)
-{
- /* In this case the packet is made of two fields, each 16 bit long.
- * So, its safe to cast data to uint16_t* and access it as a two element
- * array of uint16_t
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t address = toLittleEndian16(ptr[0]) - 1;
- uint16_t value = toLittleEndian16(ptr[1]);
-
- // value can be either 0x0000 or 0x00FF, other values are illegal.
- if ((value != 0x0000) && (value != 0x00FF))
- {
- uint8_t except = modbus::EXC_ILLEGAL_VAL;
- return new PDU(0x85, &except, 1);
- }
-
- // doing this is safe, because here we can have only 0x0000 or 0x00FF
- bool val = (value == 0x00FF) ? true : false;
- uint8_t retVal = handlers->WriteCoil(val, address);
-
- if (retVal != 0)
- {
- return new PDU(0x85, &retVal, 1);
- }
-
- // Success, return response
- return new PDU(0x05, data, 4);
-}
-
-PDU* SlaveEngine::DoWriteMultipleCoils(uint8_t* data)
-{
- /* Packet structure:
- * -> 2 bytes for starting address (data[0] and data[1])
- * -> 2 bytes for outputs quantity (data[2] and data[3])
- * -> 1 byte for byte count (data [4])
- * -> N bytes for outputs' values
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t startAddr = toLittleEndian16(ptr[0]) - 1;
- uint16_t outpCount = toLittleEndian16(ptr[1]);
- uint8_t byteCount = ptr[4];
-
- if (outpCount == 0x00 || outpCount > 0x07B0)
- {
- uint8_t excCode = modbus::EXC_ILLEGAL_VAL;
- return new PDU(0x8F, &excCode, 1);
- }
-
- uint8_t retVal = 0;
- for (uint16_t i = 0; i < outpCount; i++)
- {
- uint8_t chunk = i / 8;
- uint8_t mask = i % 8;
-
- // This is really bad: overflow
- if (chunk > byteCount)
- {
- retVal = modbus::EXC_ILLEGAL_VAL;
- break;
- }
-
- uint8_t elem = data[5 + chunk] & mask;
- bool val = (elem != 0) ? true : false;
- retVal = handlers->WriteCoil(val, startAddr + i);
-
- if (retVal != 0)
- {
- break;
- }
- }
-
- if (retVal != 0)
- {
- return new PDU(0x8F, &retVal, 1);
- }
-
- // success, return start address and output count
- return new PDU(0x0F, data, 4);
-}
-
-PDU* SlaveEngine::DoReadRegisters(uint8_t* data)
-{
- /* In this case the packet is made of two fields, each 16 bit long.
- * So, its safe to cast data to uint16_t* and access it as a two element
- * array of uint16_t
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t startAddr = toLittleEndian16(ptr[0]) - 1;
- uint16_t regsNum = toLittleEndian16(ptr[1]);
-
- if (regsNum == 0 || regsNum > 0x007D)
- {
- uint8_t excCode = modbus::EXC_ILLEGAL_VAL;
- return new PDU(0x83, &excCode, 1);
- }
-
- uint16_t result[regsNum] = {0};
- uint8_t retVal = 0;
-
- for (uint16_t i = 0; i < regsNum; i++)
- {
- uint16_t temp = 0;
- retVal = handlers->ReadRegister(temp, startAddr + i);
- result[i] = toBigEndian16(temp);
-
- if (retVal != 0)
- {
- break;
- }
- }
-
- if (retVal != 0)
- {
- return new PDU(0x83, &retVal, 1);
- }
-
- return new PDU(0x03, reinterpret_cast<uint8_t*>(&result), 2 * regsNum);
-}
-
-PDU* SlaveEngine::DoWriteRegister(uint8_t* data)
-{
- /* In this case the packet is made of two fields, each 16 bit long.
- * So, its safe to cast data to uint16_t* and access it as a two element
- * array of uint16_t
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t address = toLittleEndian16(ptr[0]) - 1;
- uint16_t value = toLittleEndian16(ptr[1]);
-
- uint8_t retVal = handlers->WriteRegister(value, address);
-
- if (retVal != 0)
- {
- return new PDU(0x86, &retVal, 1);
- }
-
- return new PDU(0x06, data, 4);
-}
-
-PDU* SlaveEngine::DoWriteMultipleRegisters(uint8_t* data)
-{
- /* Packet structure:
- * -> 2 bytes for starting address (data[0] and data[1])
- * -> 2 bytes for registers quantity (data[2] and data[2])
- * -> 1 byte for byte count (data [4])
- * -> 2*N bytes for registers' values
- */
- uint16_t* ptr = reinterpret_cast<uint16_t*>(data);
- uint16_t startAddr = toLittleEndian16(ptr[0]) - 1;
- uint16_t regsNum = toLittleEndian16(ptr[1]);
- uint8_t byteCount = ptr[4];
-
- bool outRange = (regsNum == 0x00 || regsNum > 0x07B);
- bool mismatch = ((byteCount / 2) != regsNum);
-
- if (outRange || mismatch)
- {
- uint8_t excCode = modbus::EXC_ILLEGAL_VAL;
- return new PDU(0x90, &excCode, 1);
- }
-
- // Data values begin from the 5th byte and are all 16 bit values, so this
- // conversion is safe
- uint16_t* values = reinterpret_cast<uint16_t*>(data + 5);
- uint8_t retVal = 0;
-
- for (uint16_t i = 0; i < byteCount; i++)
- {
- retVal = handlers->WriteRegister(values[i], startAddr + i);
- if (retVal != 0)
- {
- break;
- }
- }
-
- if (retVal != 0)
- {
- return new PDU(0x90, &retVal, 1);
- }
-
- return new PDU(0x10, data, 4);
-}
diff --git a/old_examples/shared/drivers/modbus/slave/SlaveEngine.h b/old_examples/shared/drivers/modbus/slave/SlaveEngine.h
deleted file mode 100644
index da8988392ff3a4aece3eeafb15c23ad3339f6cc8..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/SlaveEngine.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <interfaces/endianness.h>
-
-#include <memory>
-
-#include "../HooksInterface.h"
-#include "../PDU.h"
-#include "Common.h"
-
-class SlaveEngine
-{
-public:
- /**
- * Creates an instance of the engine
- * @param hook pointer to an instance of a HooksInterface class, if not
- * provided the SlaveEngine will use a default instance of HooksInterface
- * class.
- * The instance pointed by @param hook will be deleted when the destructor
- * of SlaveEngine is called
- */
- explicit SlaveEngine(HooksInterface* hook = nullptr);
-
- ~SlaveEngine();
-
- /**
- * Process a request received from the master.
- * @param request PDU that contains the master's request
- * @return a PDU with the either the response or the exception message
- */
- std::unique_ptr<PDU> ProcessRequest(std::unique_ptr<PDU> request);
-
-private:
- HooksInterface* handlers; ///< pointer to the handlers' class
-
- // Helper functions, one for each function code supported
- PDU* DoReadCoils(uint8_t* data);
- PDU* DoWriteCoil(uint8_t* data);
- PDU* DoWriteMultipleCoils(uint8_t* data);
- PDU* DoReadRegisters(uint8_t* data);
- PDU* DoWriteRegister(uint8_t* data);
- PDU* DoWriteMultipleRegisters(uint8_t* data);
-
- // Unsupported functions
- SlaveEngine(const SlaveEngine& other) = delete;
- SlaveEngine& operator=(const SlaveEngine& other) = delete;
- bool operator==(const SlaveEngine& other) = delete;
-};
diff --git a/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.cpp b/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.cpp
deleted file mode 100644
index da061518689b1ed3d9c60e844a7c8e4f8d65cced..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.cpp
+++ /dev/null
@@ -1,134 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "SlaveInterface.h"
-
-using namespace std;
-using namespace miosix;
-
-SlaveInterface::SlaveInterface(miosix::STM32Serial* phy, miosix::gpioPin* rxEn,
- uint8_t addr)
- : phy(phy), rxEn(rxEn), addr(addr)
-{
-
- if (addr == 0 || addr > 247)
- {
-#ifndef __NO_EXCEPTIONS
- throw invalid_argument("Slave address out of range!");
-#else
- puts("Slave address out of range!");
-#endif
- }
-
- rxEn->mode(Mode::OUTPUT);
- rxEn->low();
-}
-
-void SlaveInterface::receive()
-{
-
- /* The packet is structured as follows:
- * --------------------------------------------------
- * | slave addr | func code | data len | data | CRC |
- * --------------------------------------------------
- */
-
- uint8_t head[3] = {0}; // first of all get the header
- if (phy->readBlock(head, 3, 0) != 0)
- {
-
- size_t size = head[2];
- uint8_t payload[size + 2] = {0}; // payload size + 2 bytes of CRC
- phy->readBlock(payload, size + 2, 0);
-
- /* Here we have the first important check: is the packet addressed to
- * this slave? The check is done here in order to flush away the rx
- * buffer in case the packet is not for this slave
- */
- if (head[0] != addr)
- {
- return; // not for this slave, return
- }
-
- /* Since CRC is calculated on data len + data we have to pack all the
- * bytes in a suitable chunk on which calculate the CRC
- */
- uint8_t chunk[size + 1] = {0};
- chunk[0] = size;
- memcpy(&chunk[1], payload, size);
-
- // The CRC of the received packet is stored into the last two bytes of
- // the payload buffer, indexed at size and size + 1
- uint16_t pktCrc = *(reinterpret_cast<uint16_t*>(&payload[size]));
- if (pktCrc == CRC16(chunk, size + 1))
- {
- received.reset(PDU(head[1], payload, size));
- }
- }
-}
-
-unique_ptr<PDU> SlaveInterface::getPacket() { return move(received); }
-
-void SlaveInterface::sendReply(unique_ptr<PDU> reply)
-{
-
- auto payload = reply->data();
- size_t pktSize = payload.first + 4;
-
- uint8_t packet[pktSize] = {0};
- packet[0] = reply->funcCode();
- packet[1] = payload.first; // length of the data field
-
- std::memcpy(&packet[2], payload.second, payload.first);
- uint16_t crc = CRC16(&packet[1], payload.first + 1);
- packet[pktSize - 2] = static_cast<uint8_t>((crc >> 8) & 0xFF);
- packet[pktSize - 1] = static_cast<uint8_t>(crc & 0xFF);
-
- rxEn->high();
- phy->writeBlock(packet, pktSize, 0);
- rxEn->low();
-}
-
-uint16_t SlaveInterface::CRC16(uint8_t* data, size_t len)
-{
-
- uint16_t crc = 0xFFFF;
- for (size_t i = 0; i < len; i++)
- {
-
- crc ^= static_cast<uint16_t>(data[i]);
- for (int j = 0; j < 8; j++)
- {
-
- if (crc & 0x0001)
- {
- crc >>= 1;
- crc ^= 0xA001;
- }
- else
- {
- crc >>= 1;
- }
- }
- }
- return crc;
-}
diff --git a/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.h b/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.h
deleted file mode 100644
index 607e923a65bb5c3b7ea5e85928dd742f7973aa69..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/old/SlaveInterface.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/serial_stm32.h>
-
-#include <memory>
-#include <stdexcept>
-
-#include "../PDU.h"
-#include "Common.h"
-
-#if defined SERIAL_2_DMA
-#error Serial 2 has DMA enabled, modbus RTU interface requires it to be disabled
-#elif defined SERIAL_3_DMA
-#error Serial 3 has DMA enabled, modbus RTU interface requires it to be disabled
-#endif
-
-/**
- * This class provides an interface for Modbus RTU slave devices. The physical
- * interface is handled by using the STM32Serial driver class, so only USART 1
- * USART 2 and USART 3 are supported.
- * NOTE: this interface currently DOESN'T SUPPORT BROADCAST messages; any
- * message of this type will be ignored.
- */
-
-class SlaveInterface
-{
-public:
- /**
- * Constructor needs these parameters:
- * @param phy pointer to an STM32Serial class instance that manages the
- * serial port used for the communication
- * @param rxEn pointer to a GpioPin class that manages the pin used for
- * RS485 transceiver's RX/TX switching.
- * @param addr address assigned to the slave, must be in the range 1 - 247
- * otherwise a std::invalid_argument exception is thrown
- */
- SlaveInterface(miosix::STM32Serial *phy, miosix::gpioPin *rxEn,
- uint8_t addr);
- ~SlaveInterface();
-
- /**
- * Send a reply message to a server's request
- * @param reply std::unique_ptr to a PDU class that contains the body of
- * the message
- */
- void sendReply(std::unique_ptr<PDU> reply);
-
- /**
- * Check if new messages for this slave are arrived. User shoul periodically
- * call this function
- */
- void receive();
-
- /**
- * Get the latest packet received. If there is no new packet a nullptr is
- * returned.
- * @return std::unique_ptr to a PDU class contains the message's body
- */
- std::unique_ptr<PDU> getPacket();
-
- // Unused functions
- SlaveInterface(const SlaveInterface &other) = delete;
- SlaveInterface &operator=(const SlaveInterface &other) = delete;
- bool operator==(const SlaveInterface &other) = delete;
-
-private:
- std::unique_ptr<PDU> received; ///< last packet received
- uint8_t addr; ///< address of this slave
- miosix::STM32Serial *phy;
- miosix::gpioPin *rxEn;
-
- /**
- * This function calculates the CRC accordingly to the Modbus RTU
- * specification.
- */
- uint16_t CRC16(uint8_t *data, size_t len);
-};
diff --git a/old_examples/shared/drivers/modbus/slave/old/Timer.cpp b/old_examples/shared/drivers/modbus/slave/old/Timer.cpp
deleted file mode 100644
index 643fed3af7a520dc742400fb10ae2b2ce09816ce..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/old/Timer.cpp
+++ /dev/null
@@ -1,146 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "Timer.h"
-
-using namespace std;
-using namespace miosix;
-
-void __attribute__((naked)) TIM1_BRK_TIM9_IRQHandler()
-{
- saveContext();
- asm volatile("bl _Z10IRQHandlerv");
- restoreContext();
-}
-
-void __attribute__((used)) IRQHandler()
-{
-
- auto inst = Singleton<Timer>::getInstance();
-
- if (TIM9->SR | TIM_SR_CC1IF)
- {
- TIM9->SR &= ~TIM_SR_CC1IF;
- inst->expFlags[0] = true;
- }
-
- if (TIM9->SR | TIM_SR_CC2IF)
- {
- TIM9->SR &= ~TIM_SR_CC2IF;
- inst->expFlags[1] = true;
- }
-}
-
-Timer::Timer() : k(1.0f)
-{
- {
- FastInterruptDisableLock dLock;
- RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;
- RCC_SYNC();
- }
-
- TIM9->DIER |= TIM_DIER_CC1IE | TIM_DIER_CC2IE;
- TIM9->ARR = 0xFFFF;
- TIM9->CCMR1 = 0;
- TIM9->CCMR2 = 0;
- TIM9->CNT = 0;
- TIM9->EGR |= TIM_EGR_UG; // generate update event to load values
-
- NVIC_SetPriority(TIM9_IRQn, 15); // Lowest priority for serial
- NVIC_ClearPendingIRQ(TIM9_IRQn);
- NVIC_EnableIRQ(TIM9_IRQn);
-}
-
-Timer::~Timer()
-{
- stop();
- {
- FastInterruptDisableLock dLock;
- RCC->APB2ENR |= RCC_APB2ENR_TIM9EN;
- RCC_SYNC();
- }
-}
-
-void Timer::start() { TIM9->CR1 |= TIM_CR1_CEN; }
-
-void Timer::stop() { TIM9->CR1 &= ~TIM_CR1_CEN; }
-
-void Timer::init(uint32_t refBaud)
-{
- uint32_t busFreq = SystemCoreClock;
- if (RCC->CFGR & RCC_CFGR_PPRE2_2)
- {
- busFreq /= 1 << (((RCC->CFGR >> 13) & 0x3) + 1);
- }
-
- /* Here we calculate the prescaler value based on baud rate value.
- * From the modbus RTU specification we have that, if the baud is greater
- * than 19200, the t1.5 and t3.5 are fixed as the baud is 19200.
- * The timer is set up to accept values multiple of t1.5. Its exact value is
- * given by the formula (1.5 * 11) / baud, since a modbus RTU character is
- * 11 bit long. Here we use an aproximate one (17/baud instead of 16.5/baud)
- * because we do all the calculations with ints.
- * The prescaler value is given by busFreq * t1.5, that is
- * (busFreq * 17) / baud. If this value falls above 65536, the maximum
- * acceptable for the prescaler, the latter is set to 0xFFFF and a suitable
- * value for the correction factor k is computed.
- */
- uint32_t prescaler = (busFreq / min(refBaud, 19200)) * 17;
- if (prescaler > 65536)
- {
- TIM9->PSC = 0xFFFF;
- k = (static_cast<float>(busFreq) * 17.0f);
- k /= (65536.0f * static_cast<float>(refBaud));
- }
- else
- {
- TIM9->PSC = prescaler - 1;
- k = 1.0f;
- }
-
- TIM9->EGR |= TIM_EGR_UG; // generate update event to load values
-}
-
-bool Timer::expired(uint8_t channel)
-{
- bool temp = expFlags[channel];
- expFlags[channel] = false;
- return temp;
-}
-
-void Timer::newSetpoint(uint8_t channel, uint8_t ticks)
-{
- uint16_t incr = static_cast<uint16_t>((ticks * k) + 0.5f);
- switch (channel)
- {
- case 1:
- TIM9->CCMR1 += incr;
- break;
-
- case 2:
- TIM9->CCMR2 += incr;
- break;
-
- default:
- break;
- }
-}
diff --git a/old_examples/shared/drivers/modbus/slave/old/Timer.h b/old_examples/shared/drivers/modbus/slave/old/Timer.h
deleted file mode 100644
index 7453fc3e07767fd4fe5b82a4a1e011294a327fde..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/modbus/slave/old/Timer.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <algorithm>
-
-#include "Common.h"
-
-class Timer : public Singleton<Timer>
-{
-
- friend class Singleton<Timer>;
-
-public:
- ~Timer();
-
- /**
- * Initialize the timer prescaler in order to have a counter tick equals,
- * in time terms, to the time needed to send 1.5 11 bit long characters at
- * the speed specified by @param refBaud
- */
- void init(uint32_t refBaud);
-
- /**
- * Start the timer
- */
- void start();
-
- /**
- * Stop the timer
- */
- void stop();
-
- /**
- * Set a new expiring setpoint @param ticks ahead from now for channel
- * specified by @param channel
- */
- void newSetpoint(uint8_t channel, uint8_t ticks);
-
- /**
- * @return true if the timer's @param channel expired, calling this
- * function will reset to fals the internal flag.
- */
- bool expired(uint8_t channel);
-
-private:
- Timer();
-
- friend void IRQHandler(); ///< timer IRQ handler
-
- bool expFlags[2] = {false};
- float k; ///< conversion factor internally used, see implementation
-
- Timer(const Timer& other) = delete;
- Timer& operator=(const Timer& other) = delete;
- bool operator==(const Timer& other) = delete;
-};
diff --git a/old_examples/shared/drivers/piksi/piksi.cpp b/old_examples/shared/drivers/piksi/piksi.cpp
deleted file mode 100644
index 1ca1a7cc75c60d5c1911ecaed2d384ff8b8797b3..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/piksi/piksi.cpp
+++ /dev/null
@@ -1,285 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "piksi.h"
-
-#include <diagnostic/SkywardStack.h>
-#include <diagnostic/StackLogger.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#include <sys/types.h>
-#include <termios.h>
-#include <time.h>
-#include <unistd.h>
-#include <utils/Debug.h>
-
-#include <algorithm>
-#include <cmath>
-
-using namespace std;
-
-#ifdef _MIOSIX
-
-#include <miosix.h>
-
-using namespace miosix;
-
-#endif //_MIOSIX
-
-/*
- * Contrary to the standard CCITT CRC that starts from 0xffff, the Piksi
- * people decided to start from 0. So we need a special CRC16 just for them
- */
-
-static inline void crc16piksiUpdate(unsigned short &crc, unsigned char data)
-{
- unsigned short x = ((crc >> 8) ^ data) & 0xff;
- x ^= x >> 4;
- crc = (crc << 8) ^ (x << 12) ^ (x << 5) ^ x;
-}
-
-static unsigned short crc16piksi(const void *message, unsigned int length)
-{
- const unsigned char *m = reinterpret_cast<const unsigned char *>(message);
- unsigned short result = 0;
- for (unsigned int i = 0; i < length; i++)
- crc16piksiUpdate(result, m[i]);
- return result;
-}
-
-//
-// class Piksi
-//
-
-Piksi::Piksi(const char *serialPath)
-{
- // cppcheck-suppress memsetClassFloat
- memset(&data, 0, sizeof(PiksiGPSData));
- // cppcheck-suppress memsetClassFloat
- memset(&partialData, 0, sizeof(PiksiGPSData));
-
- fd = open(serialPath, O_RDWR);
- if (fd < 0)
- throw runtime_error(string("Cannot open ") + serialPath);
- if (isatty(fd))
- {
- termios t;
- tcgetattr(fd, &t);
- t.c_lflag &= ~(ISIG | ICANON | ECHO);
-#ifndef _MIOSIX
- cfsetospeed(&t, B115200);
- cfsetispeed(&t, B115200);
-#endif //_MIOSIX
- tcsetattr(fd, TCSANOW, &t);
- }
- pthread_attr_t attr;
- pthread_attr_init(&attr);
- pthread_attr_setstacksize(&attr, skywardStack(STACK_DEFAULT_FOR_PTHREAD));
-
- pthread_create(&thread, &attr, &threadLauncher, this);
-
- pthread_attr_destroy(&attr);
-
- pthread_mutex_init(&mutex, NULL);
- pthread_cond_init(&cond, NULL);
-}
-
-PiksiGPSData Piksi::getGpsData()
-{
- PiksiGPSData result;
- pthread_mutex_lock(&mutex);
- result = data;
-
- if (!firstFixReceived)
- {
- pthread_mutex_unlock(&mutex);
- throw runtime_error("No fix");
- }
-
- pthread_mutex_unlock(&mutex);
- return result;
-}
-
-PiksiGPSData Piksi::waitForGpsData()
-{
- PiksiGPSData result;
- pthread_mutex_lock(&mutex);
- pthread_cond_wait(&cond, &mutex);
- result = data;
- pthread_mutex_unlock(&mutex);
- return result;
-}
-
-Piksi::~Piksi()
-{
- quit = true;
- pthread_join(thread, NULL);
- pthread_mutex_destroy(&mutex);
- pthread_cond_destroy(&cond);
- close(fd);
-}
-
-void *Piksi::threadLauncher(void *arg)
-{
- reinterpret_cast<Piksi *>(arg)->run();
- return nullptr;
-}
-
-void Piksi::run()
-{
- do
- {
- bytes.added(readData(bytes.addEnd(), bytes.availableToAdd()));
- bytes.removed(
- lookForMessages(bytes.removeEnd(), bytes.availableToRemove()));
-
- StackLogger::getInstance().updateStack(THID_PIKSI);
-
- } while (quit == false);
-}
-
-unsigned int Piksi::readData(unsigned char *buffer, unsigned int size)
-{
- int result = read(fd, buffer, size);
- if (result > 0)
- return result;
- usleep(10000); // We want to retry but avoid 100% CPU utilization
- return 0; // To go to a loop of run() and notice the quit flag
-}
-
-unsigned int Piksi::lookForMessages(uint8_t *buffer, unsigned int size)
-{
- const uint8_t preamble = 0x55;
- unsigned int consumed = 0;
- auto consume = [&](unsigned int n)
- {
- consumed += n;
- buffer += n;
- size -= n;
- };
- for (;;)
- {
- uint8_t *index = find(buffer, buffer + size, preamble);
- consume(index - buffer); // Consume eventual characters between
- // messages
-
- if (size < sizeof(Header))
- return consumed; // We don't have the header
- auto header = reinterpret_cast<Header *>(buffer);
- unsigned int messageSize = sizeof(Header) + header->length + crcSize;
- if (messageSize > size)
- return consumed; // We don't have the entire message
-
- uint16_t crc;
- memcpy(&crc, buffer + messageSize - crcSize, sizeof(crc));
-
- if (crc16piksi(buffer + 1, messageSize - crcSize - 1) == crc)
- {
- processValidMessage(buffer, messageSize);
- consume(messageSize);
- }
- else
- {
- // TODO: fault counter?
- consume(1); // Consume the preamble of the invalid message
- }
- }
-}
-
-void Piksi::processValidMessage(uint8_t *buffer, unsigned int size)
-{
- Header *header = reinterpret_cast<Header *>(buffer);
- switch (header->type)
- {
- case MSG_POS_LLH:
- if (size < sizeof(MsgPosLlh)) /* TODO: fault counter? */
- ;
- else
- processPosLlh(reinterpret_cast<MsgPosLlh *>(buffer));
- break;
- case MSG_VEL_NED:
- if (size < sizeof(MsgVelNed)) /* TODO: fault counter? */
- ;
- else
- processVelNed(reinterpret_cast<MsgVelNed *>(buffer));
- break;
- default:
- // A valid message we're not interested in
- break;
- }
-}
-
-void Piksi::processPosLlh(Piksi::MsgPosLlh *msg)
-{
- partialData.latitude = msg->lat;
- partialData.longitude = msg->lon;
- partialData.height = msg->height;
- partialData.numSatellites = msg->n_sats;
-#ifdef _MIOSIX
- partialData.timestamp = getTick();
-#else //_MIOSIX
- partialData.timestamp = clock() / (CLOCKS_PER_SEC / 1000);
-#endif //_MIOSIX
-
- if (vel && gpsTimestamp == msg->ms)
- {
- vel = pos = false;
-
- pthread_mutex_lock(&mutex);
- data = partialData;
- firstFixReceived = true;
- pthread_cond_broadcast(&cond);
- pthread_mutex_unlock(&mutex);
- }
- else
- {
- pos = true;
- gpsTimestamp = msg->ms;
- }
-}
-
-void Piksi::processVelNed(Piksi::MsgVelNed *msg)
-{
- partialData.velocityNorth = static_cast<float>(msg->n) / 1000.f;
- partialData.velocityEast = static_cast<float>(msg->e) / 1000.f;
- partialData.velocityDown = static_cast<float>(msg->d) / 1000.f;
-
- partialData.speed = sqrtf(powf(partialData.velocityNorth, 2) +
- powf(partialData.velocityEast, 2) +
- powf(partialData.velocityDown, 2));
-
- if (pos && gpsTimestamp == msg->ms)
- {
- vel = pos = false;
-
- pthread_mutex_lock(&mutex);
- data = partialData;
- firstFixReceived = true;
- pthread_cond_broadcast(&cond);
- pthread_mutex_unlock(&mutex);
- }
- else
- {
- vel = true;
- gpsTimestamp = msg->ms;
- }
-}
diff --git a/old_examples/shared/drivers/piksi/piksi.h b/old_examples/shared/drivers/piksi/piksi.h
deleted file mode 100644
index 5c7eda3e0551017c034c3e3e4ddf479eea7a9fb3..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/piksi/piksi.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <pthread.h>
-#include <utils/collections/contiguous_queue.h>
-
-#include "piksi_data.h"
-
-/**
- * Class to access the Piksi GPS.
- *
- * Should be connected to the Piksi UARTB configured as
- * MODE SBP
- * SBP message mask 65280
- * telemetry radio on boot False
- * baudrate 115200
- */
-class Piksi
-{
-public:
- /**
- * Constructor
- * \param serialPath path to the device file of the Piksi serial port
- * \throws runtime_error if the serial port cannot be opened
- */
- explicit Piksi(const char *serialPath);
-
- /**
- * \return the latest GPS data, or throws if the GPS has not yet got a fix.
- * If the GPS has lost the fix, the same data is returned repeatedly,
- * use the timestamp field of the GPSData struct to know this.
- * \throws runtime_error is no data is available
- */
- PiksiGPSData getGpsData();
-
- /**
- * \return the latest GPS data. If the GPS has yet got a fix or has lost
- * the fix, this function will block until the fix is regained
- */
- PiksiGPSData waitForGpsData();
-
- /**
- * Destructor
- */
- ~Piksi();
-
-private:
- Piksi(const Piksi &) = delete;
- Piksi &operator=(const Piksi &) = delete;
-
- struct __attribute__((packed)) Header
- {
- uint8_t preamble;
- uint16_t type;
- uint16_t sender;
- uint8_t length;
- };
-
- static const unsigned int crcSize = 2;
-
- static const uint16_t MSG_POS_LLH = 0x0201;
-
- struct __attribute__((packed)) MsgPosLlh
- {
- Header header;
- uint32_t ms; // [ms]
- double lat; // [deg]
- double lon; // [deg]
- double height; // [m]
- uint16_t h_accuracy; // Piksi says unimplemented
- uint16_t v_accuracy; // Piksi says unimplemented
- uint8_t n_sats;
- uint8_t flags;
- };
-
- static const uint16_t MSG_VEL_NED = 0x0205;
-
- struct __attribute__((packed)) MsgVelNed
- {
- Header header;
- uint32_t ms; // [ms]
- int32_t n; // [mm/s]
- int32_t e; // [mm/s]
- int32_t d; // [mm/s]
- uint16_t h_accuracy; // Piksi says unimplemented
- uint16_t v_accuracy; // Piksi says unimplemented
- uint8_t n_sats;
- uint8_t flags;
- };
-
- /**
- * Launches run() from the background thread
- * \param arg this
- */
- static void *threadLauncher(void *arg);
-
- /**
- * Piksi main processing loop
- */
- void run();
-
- /**
- * Fill a buffer from the serial port where the piksi is connected
- * \param buffer where to store read data
- * \param size how many bytes to read
- */
- unsigned int readData(unsigned char *buffer, unsigned int size);
-
- /**
- * Tries to find one or more piksi message in the buffer. There are no
- * alignment requirements, the given buffer can begin and end in the middle
- * of a packet.
- * \param buffer buffer read from the serial port
- * \param size buffer size
- * \return the number of consumed characters. the last size-consumed bytes
- * of the buffer are not processed yet, most likely because they contain an
- * incomplete message, and must be prepended to the buffer given at the
- * next call in order not to miss some packets.
- */
- unsigned int lookForMessages(uint8_t *buffer, unsigned int size);
-
- /**
- * Called on a message that has already passed the CRC check.
- * \param buffer pointer to the first message byte (0x55)
- * \param size message size
- */
- void processValidMessage(uint8_t *buffer, unsigned int size);
-
- /**
- * Processes a POS_LLH message
- * \param msg the message
- */
- void processPosLlh(MsgPosLlh *msg);
-
- /**
- * Processes a VEL_NED message
- * \param msg the message
- */
- void processVelNed(MsgVelNed *msg);
-
- // The queue should be large enough to contain the largest message (256+8)
- ContiguousQueue<uint8_t, 384> bytes;
- int fd;
- pthread_t thread;
- pthread_mutex_t mutex;
- pthread_cond_t cond;
- PiksiGPSData data, partialData;
- uint32_t gpsTimestamp = 0;
- bool pos = false;
- bool vel = false;
- bool firstFixReceived = false;
- volatile bool quit = false;
-};
diff --git a/old_examples/shared/drivers/piksi/piksi_data.h b/old_examples/shared/drivers/piksi/piksi_data.h
deleted file mode 100644
index 66af60cdc24cf6a42d903ff7b17a56b815fb6cd8..0000000000000000000000000000000000000000
--- a/old_examples/shared/drivers/piksi/piksi_data.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* Copyright (c) 2017-2019 Skyward Experimental Rocketry
- * Author: Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-/**
- * The GPS information
- */
-struct PiksiGPSData
-{
- /// timestamp in ms (anakin time, not GPS time). getTick()-timestamp tells
- /// you how "old" the data is.
- long long timestamp;
-
- double latitude; ///< [deg] //TODO: cast to float??
- double longitude; ///< [deg] //TODO: cast to float??
- double height; ///< [m] //TODO: cast to float??
- float velocityNorth; ///< [m/s]
- float velocityEast; ///< [m/s]
- float velocityDown; ///< [m/s]
- float speed; ///< [m/s]
- int numSatellites; ///< [1]
-};
diff --git a/old_examples/shared/math/Matrix.cpp b/old_examples/shared/math/Matrix.cpp
deleted file mode 100644
index f8c67103ff945cec302b78cbe6e6959206440056..0000000000000000000000000000000000000000
--- a/old_examples/shared/math/Matrix.cpp
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include "Matrix.h"
-
-namespace Boardcore
-{
-
-/** Identity matrix constructor */
-Mat4::Mat4()
-{
- memset(d, 0, sizeof(d));
- d[0] = d[5] = d[10] = d[15] = 1;
-}
-
-/** Initialize from 4*4 float array */
-Mat4::Mat4(const float v[16]) { memcpy(d, v, 16 * sizeof(float)); }
-
-Vec3 Mat4::operator*(const Vec3 &vector) const
-{
- return Vec3(vector.x * d[0] + vector.y * d[1] + vector.z * d[2] + d[3],
-
- vector.x * d[4] + vector.y * d[5] + vector.z * d[6] + d[7],
-
- vector.x * d[8] + vector.y * d[9] + vector.z * d[10] + d[11]);
-}
-
-Mat4 Mat4::operator*(const Mat4 &o) const
-{
- /** Every Mat4 is supposed to be like
- * | r1 r2 r3 t1 |
- * | r4 r5 r6 t2 |
- * | r7 r8 r9 t3 |
- * | 0 0 0 1 |
- */
- Mat4 r;
- r.d[0] = (d[0] * o.d[0]) + (d[1] * o.d[4]) + (d[2] * o.d[8]);
- r.d[4] = (d[4] * o.d[0]) + (d[5] * o.d[4]) + (d[6] * o.d[8]);
- r.d[8] = (d[8] * o.d[0]) + (d[9] * o.d[4]) + (d[10] * o.d[8]);
-
- r.d[1] = (d[0] * o.d[1]) + (d[1] * o.d[5]) + (d[2] * o.d[9]);
- r.d[5] = (d[4] * o.d[1]) + (d[5] * o.d[5]) + (d[6] * o.d[9]);
- r.d[9] = (d[8] * o.d[1]) + (d[9] * o.d[5]) + (d[10] * o.d[9]);
-
- r.d[2] = (d[0] * o.d[2]) + (d[1] * o.d[6]) + (d[2] * o.d[10]);
- r.d[6] = (d[4] * o.d[2]) + (d[5] * o.d[6]) + (d[6] * o.d[10]);
- r.d[10] = (d[8] * o.d[2]) + (d[9] * o.d[6]) + (d[10] * o.d[10]);
-
- r.d[3] = (d[0] * o.d[3]) + (d[1] * o.d[7]) + (d[2] * o.d[11]) + d[3];
- r.d[7] = (d[4] * o.d[3]) + (d[5] * o.d[7]) + (d[6] * o.d[11]) + d[7];
- r.d[11] = (d[8] * o.d[3]) + (d[9] * o.d[7]) + (d[10] * o.d[11]) + d[11];
-
- return r;
-}
-
-Vec3 Mat4::transform(const Vec3 &vec) const { return (*this) * vec; }
-
-Vec3 Mat4::transformInverse(const Vec3 &vec) const
-{
- Mat4 temp;
- Vec3 tmp = vec;
-
- // Subtract the translation vector
- tmp.x -= d[3];
- tmp.y -= d[7];
- tmp.z -= d[11];
-
- // Multiply
- return Vec3(tmp.x * d[0] + tmp.y * d[4] + tmp.z * d[8],
-
- tmp.x * d[1] + tmp.y * d[5] + tmp.z * d[9],
-
- tmp.x * d[2] + tmp.y * d[6] + tmp.z * d[10]);
-}
-
-float Mat4::determinant() const
-{
- return -d[8] * d[5] * d[2] + d[4] * d[9] * d[2] + d[8] * d[1] * d[6] -
- d[0] * d[9] * d[6] - d[4] * d[1] * d[10] + d[0] * d[5] * d[10];
-}
-
-void Mat4::setInverse(const Mat4 &m)
-{
- float det = m.determinant();
- if (det == 0)
- return;
-
- det = ((float)1.0) / det;
-
- d[0] = (-m.d[9] * m.d[6] + m.d[5] * m.d[10]) * det;
- d[4] = (m.d[8] * m.d[6] - m.d[4] * m.d[10]) * det;
- d[8] = (-m.d[8] * m.d[5] + m.d[4] * m.d[9]) * det;
-
- d[1] = (m.d[9] * m.d[2] - m.d[1] * m.d[10]) * det;
- d[5] = (-m.d[8] * m.d[2] + m.d[0] * m.d[10]) * det;
- d[9] = (m.d[8] * m.d[1] - m.d[0] * m.d[9]) * det;
-
- d[2] = (-m.d[5] * m.d[2] + m.d[1] * m.d[6]) * det;
- d[6] = (+m.d[4] * m.d[2] - m.d[0] * m.d[6]) * det;
- d[10] = (-m.d[4] * m.d[1] + m.d[0] * m.d[5]) * det;
-
- d[3] = (m.d[9] * m.d[6] * m.d[3] - m.d[5] * m.d[10] * m.d[3] -
- m.d[9] * m.d[2] * m.d[7] + m.d[1] * m.d[10] * m.d[7] +
- m.d[5] * m.d[2] * m.d[11] - m.d[1] * m.d[6] * m.d[11]) *
- det;
-
- d[7] = (-m.d[8] * m.d[6] * m.d[3] + m.d[4] * m.d[10] * m.d[3] +
- m.d[8] * m.d[2] * m.d[7] - m.d[0] * m.d[10] * m.d[7] -
- m.d[4] * m.d[2] * m.d[11] + m.d[0] * m.d[6] * m.d[11]) *
- det;
-
- d[11] = (m.d[8] * m.d[5] * m.d[3] - m.d[4] * m.d[9] * m.d[3] -
- m.d[8] * m.d[1] * m.d[7] + m.d[0] * m.d[9] * m.d[7] +
- m.d[4] * m.d[1] * m.d[11] - m.d[0] * m.d[5] * m.d[11]) *
- det;
-}
-
-Mat3::Mat3()
-{
- memset(d, 0, sizeof(d));
- d[0] = d[4] = d[8] = 1;
-}
-
-Mat3::Mat3(const float v[9]) { memcpy(d, v, 9 * sizeof(float)); }
-
-Mat3 Mat3::operator*(const Mat3 &o) const
-{
- Mat3 r;
- r.d[0] = d[0] * o.d[0] + d[1] * o.d[3] + d[2] * o.d[6];
- r.d[1] = d[0] * o.d[1] + d[1] * o.d[4] + d[2] * o.d[7];
- r.d[2] = d[0] * o.d[2] + d[1] * o.d[5] + d[2] * o.d[8];
-
- r.d[3] = d[3] * o.d[0] + d[4] * o.d[3] + d[5] * o.d[6];
- r.d[4] = d[3] * o.d[1] + d[4] * o.d[4] + d[5] * o.d[7];
- r.d[5] = d[3] * o.d[2] + d[4] * o.d[5] + d[5] * o.d[8];
-
- r.d[6] = d[6] * o.d[0] + d[7] * o.d[3] + d[8] * o.d[6];
- r.d[7] = d[6] * o.d[1] + d[7] * o.d[4] + d[8] * o.d[7];
- r.d[8] = d[6] * o.d[2] + d[7] * o.d[5] + d[8] * o.d[8];
- return r;
-}
-
-Vec3 Mat3::operator*(const Vec3 &vector) const
-{
- return Vec3(vector.x * d[0] + vector.y * d[1] + vector.z * d[2],
- vector.x * d[3] + vector.y * d[4] + vector.z * d[5],
- vector.x * d[6] + vector.y * d[7] + vector.z * d[8]);
-}
-
-Vec3 Mat3::transform(const Vec3 &vec) const { return (*this) * vec; }
-
-void Mat3::setInverse(const Mat3 &m)
-{
- float t4 = m.d[0] * m.d[4];
- float t6 = m.d[0] * m.d[5];
- float t8 = m.d[1] * m.d[3];
- float t10 = m.d[2] * m.d[3];
- float t12 = m.d[1] * m.d[6];
- float t14 = m.d[2] * m.d[6];
-
- // Calculate the determinant
- float t16 = (t4 * m.d[8] - t6 * m.d[7] - t8 * m.d[8] + t10 * m.d[7] +
- t12 * m.d[5] - t14 * m.d[4]);
-
- // Make sure the determinant is non-zero.
- if (t16 == (float)0.0f)
- return;
- float t17 = 1 / t16;
-
- d[0] = (m.d[4] * m.d[8] - m.d[5] * m.d[7]) * t17;
- d[1] = -(m.d[1] * m.d[8] - m.d[2] * m.d[7]) * t17;
- d[2] = (m.d[1] * m.d[5] - m.d[2] * m.d[4]) * t17;
- d[3] = -(m.d[3] * m.d[8] - m.d[5] * m.d[6]) * t17;
- d[4] = (m.d[0] * m.d[8] - t14) * t17;
- d[5] = -(t6 - t10) * t17;
- d[6] = (m.d[3] * m.d[7] - m.d[4] * m.d[6]) * t17;
- d[7] = -(m.d[0] * m.d[7] - t12) * t17;
- d[8] = (t4 - t8) * t17;
-}
-
-void Mat3::setTranspose(const Mat3 &m)
-{
- d[0] = m.d[0];
- d[1] = m.d[3];
- d[2] = m.d[6];
- d[3] = m.d[1];
- d[4] = m.d[4];
- d[5] = m.d[7];
- d[6] = m.d[2];
- d[7] = m.d[5];
- d[8] = m.d[8];
-}
-
-} // namespace Boardcore
diff --git a/old_examples/shared/math/Matrix.h b/old_examples/shared/math/Matrix.h
deleted file mode 100644
index 817eac9c77ae09dc3dd2f2e9f33b09673c33a421..0000000000000000000000000000000000000000
--- a/old_examples/shared/math/Matrix.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <cstring>
-
-#include "Vec3.h"
-
-namespace Boardcore
-{
-
-/* TODO: double and triple check routines in these classes!!!
- *
- * This class works with matrices having the following pattern:
- * | a11 a12 a13 a14 |
- * | a21 a22 a23 a24 |
- * | a31 a32 a33 a34 |
- * | 0 0 0 1 |
- *
- * Remember that [Vec3] = [Mat4 * Vec3];
- * Where multiplication converts the Vec3 to a Vec4 like this: [x y z 1]
- */
-
-class Mat4
-{
-public:
- Mat4();
- explicit Mat4(const float v[16]);
-
- Mat4 operator*(const Mat4 &o) const;
-
- Vec3 operator*(const Vec3 &vector) const;
- Vec3 transform(const Vec3 &vec) const;
- Vec3 transformInverse(const Vec3 &vec) const;
-
- float determinant() const;
- void setInverse(const Mat4 &m);
-
- float d[16];
-};
-
-class Mat3
-{
-public:
- Mat3();
- explicit Mat3(const float v[9]);
-
- Mat3 operator*(const Mat3 &o) const;
-
- Vec3 operator*(const Vec3 &vector) const;
- Vec3 transform(const Vec3 &vec) const;
-
- void setInverse(const Mat3 &m);
- void setTranspose(const Mat3 &m);
-
- void setVertComponents(const Vec3 &f, const Vec3 &s, const Vec3 &t);
-
- float d[9];
-};
-
-} // namespace Boardcore
diff --git a/old_examples/shared/math/Vec3.h b/old_examples/shared/math/Vec3.h
deleted file mode 100644
index bd942277f005e953ee556b266715c5374176670a..0000000000000000000000000000000000000000
--- a/old_examples/shared/math/Vec3.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <cmath>
-
-namespace Boardcore
-{
-
-class Vec3
-{
- friend class Mat4;
- friend class Mat3;
-
-public:
- Vec3() { clear(); }
-
- Vec3(const Vec3 &rhs)
- {
- x = rhs.x;
- y = rhs.y;
- z = rhs.z;
- }
-
- Vec3(float x, float y, float z)
- {
- this->x = x;
- this->y = y;
- this->z = z;
- }
-
- float getX() const { return x; }
- float getY() const { return y; }
- float getZ() const { return z; }
-
- void setX(float value) { x = value; }
- void setY(float value) { y = value; }
- void setZ(float value) { z = value; }
-
- void clear() { x = y = z = 0.0f; }
-
- float magnitude() const { return sqrt(dot(*this)); }
-
- bool normalize()
- {
- float l = magnitude();
- if (l <= 0)
- return false;
-
- (*this) *= 1.0f / l;
- return true;
- }
-
- void operator=(const Vec3 &rhs)
- {
- x = rhs.x;
- y = rhs.y;
- z = rhs.z;
- }
-
- void operator*=(float value)
- {
- x *= value;
- y *= value;
- z *= value;
- }
-
- void operator/=(float value)
- {
- x /= value;
- y /= value;
- z /= value;
- }
-
- void operator+=(const Vec3 &v)
- {
- x += v.getX();
- y += v.getY();
- z += v.getZ();
- }
-
- void operator-=(const Vec3 &v)
- {
- x -= v.getX();
- y -= v.getY();
- z -= v.getZ();
- }
-
- Vec3 operator*(float t) const { return Vec3(x * t, y * t, z * t); }
-
- Vec3 operator/(float t) const { return Vec3(x / t, y / t, z / t); }
-
- Vec3 operator+(const Vec3 &v) const
- {
- return Vec3(x + v.getX(), y + v.getY(), z + v.getZ());
- }
-
- Vec3 operator-(const Vec3 &v) const
- {
- return Vec3(x - v.getX(), y - v.getY(), z - v.getZ());
- }
-
- Vec3 operator-() const { return Vec3(-x, -y, -z); }
-
- float dot(const Vec3 &v) const
- {
- return x * v.getX() + y * v.getY() + z * v.getZ();
- }
-
- Vec3 cross(const Vec3 &v) const
- {
- return Vec3(y * v.getZ() - z * v.getY(), z * v.getX() - x * v.getZ(),
- x * v.getY() - y * v.getX());
- }
-
-private:
- float x, y, z;
-};
-
-} // namespace Boardcore
diff --git a/old_examples/shared/sensors/ADIS16405/ADIS16405.h b/old_examples/shared/sensors/ADIS16405/ADIS16405.h
deleted file mode 100644
index 9c075f79039fc74c8bb4b21add8fc8e87e9aacff..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/ADIS16405/ADIS16405.h
+++ /dev/null
@@ -1,354 +0,0 @@
-/* Copyright (c) 2018-2019 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-#include <sensors/Sensor.h>
-#include <utils/Debug.h>
-
-#include "ADIS16405Data.h"
-
-template <typename BusSPI, typename rstPin>
-class ADIS16405 : public AccelSensor,
- public GyroSensor,
- public CompassSensor,
- public TemperatureSensor
-{
-public:
- ADIS16405(uint8_t gyroFullScale) { gyroFS = gyroFullScale; }
- virtual ~ADIS16405() {}
-
- std::vector<SPIRequest> buildDMARequest() override
- {
- // clang-format off
- std::vector<uint8_t> v =
- {
- ADIS_GLOB_CMD, 0, // System command
- 0,0, // Power supply measurement
- 0,0, // X-axis gyroscope output
- 0,0, // Y-axis gyroscope output
- 0,0, // Z-axis gyroscope output
- 0,0, // X-axis accelerometer output
- 0,0, // Y-axis accelerometer output
- 0,0, // Z-axis accelerometer output
- 0,0, // X-axis magnetometer measurement
- 0,0, // Y-axis magnetometer measurement
- 0,0, // Z-axis magnetometer measurement
- 0,0, // Temperature output
- 0,0, // Auxiliary ADC measurement
- };
- // clang-format on
-
- return {SPIRequest(0, BusSPI::getCSPin(), v)};
- }
-
- bool init() override
- {
- // Ensure right SPI frequency
- // Burst mode SPI < 1 MHz
- // Low power mode SPI < 300 kHz
-
- rstPin::mode(miosix::Mode::OUTPUT);
- rstPin::high(); // Turn on the device
-
- miosix::delayMs(220); // 220 ms start-up time
-
- uint16_t product_id = readReg(ADIS_PRODUCT_ID);
- if (product_id != product_id_value)
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- // TODO: test it -- config the dynamic range
- uint16_t sensorAvg = readReg(ADIS_SENS_AVG);
- writeReg(ADIS_SENS_AVG, sensorAvg | (1 << (8 + gyroFS)));
-
- return true;
- }
-
- void readTest()
- {
- // uint16_t product_id = readReg(ADIS_PRODUCT_ID);
- // TRACE("product_id: %d\n", product_id);
-
- // float accel = normalizeAccel(signExtend(readReg(ADIS_YACCL_OUT) &
- // 0x3FFF, 14)); TRACE("temperature: %f\n", accel);
-
- // float temperature = normalizeTemp(signExtend(readReg(ADIS_TEMP_OUT) &
- // 0x0FFF, 12)); TRACE("temperature: %f\n", temperature);
-
- // float voltage = normalizePower(readReg(ADIS_SUPPLY_OUT) & 0x3FFF);
- // TRACE("voltage: %f\n", voltage);
-
- // writewriteReg(ADIS_ZMAGN_SIF,0x0800);
- // miosix::delayMs(1);
- // uint16_t reg_value = readReg(ADIS_ZMAGN_SIF);
- // TRACE("reg value: %d\n", reg_value);
- // miosix::delayMs(200);
- }
-
- void burstTest()
- {
- ADIS16405Data burstData;
- burstDataCollect(&burstData);
- // TRACE("%f\t",normalizeSupply(burstData.supply_out));
- // TRACE("%f\t",normalizeGyro(burstData.xgyro_out));
- // TRACE("%f\t",normalizeGyro(burstData.ygyro_out));
- TRACE("%f\t", normalizeGyro(burstData.zgyro_out));
- // TRACE("%f\t",normalizeAccel(burstData.xaccl_out));
- // TRACE("%f\t",normalizeAccel(burstData.yaccl_out));
- // TRACE("%f\t",normalizeAccel(burstData.zaccl_out));
- // TRACE("%f\t",normalizeMagneto(burstData.xmagn_out));
- // TRACE("%f\t",normalizeMagneto(burstData.ymagn_out));
- // TRACE("%f\t",normalizeMagneto(burstData.zmagn_out));
- // TRACE("%f\t",normalizeTemp(burstData.temp_out));
- // TRACE("%f\t",normalizeADC(burstData.aux_adc));
- TRACE("\n");
- }
-
- // Exercises all inertial sensors, measures each response,
- // makes pass/fail decisions, and reports them to error flags
- // in the DIAG_STAT register
- bool selfTest() override
- {
- // DIAG_STAT clears after each read so we read to clear it
- uint16_t diagstat = readReg(ADIS_DIAG_STAT);
-
- uint16_t msc = readReg(ADIS_MSC_CTRL);
- writeReg(ADIS_MSC_CTRL, msc | 1 << 10);
- // msc = readReg(ADIS_MSC_CTRL);
-
- // writeReg(ADIS_MSC_CTRL, 0x3504); // Config and start self test
-
- // MSC_CTRL[10] resets itself to 0 after completing the self test
- // routine
- do
- {
- msc = readReg(ADIS_MSC_CTRL);
- } while (msc & 1 << 10);
-
- diagstat = readReg(ADIS_DIAG_STAT);
- return (diagstat ==
- 0); // All bits are cleared if the test was successful
- }
-
- void onDMAUpdate(const SPIRequest& req) override
- {
- const std::vector<uint8_t>& r = req.readResponseFromPeripheral();
-
- uint8_t raw_data[sizeof(ADIS16405Data)];
- memcpy(&raw_data, &(r[2]), sizeof(ADIS16405Data));
-
- for (uint8_t i = 0; i < sizeof(ADIS16405Data); i++)
- raw_data[i] = fromBigEndian16(raw_data[i]);
-
- ADIS16405Data data;
- parseBurstData(raw_data, &data);
-
- mLastGyro.setX(normalizeGyro(data.xgyro_out));
- mLastGyro.setY(normalizeGyro(data.ygyro_out));
- mLastGyro.setZ(normalizeGyro(data.zgyro_out));
-
- mLastAccel.setX(normalizeAccel(data.xaccl_out));
- mLastAccel.setY(normalizeAccel(data.yaccl_out));
- mLastAccel.setZ(normalizeAccel(data.zaccl_out));
-
- mLastCompass.setX(normalizeMagneto(data.xmagn_out));
- mLastCompass.setY(normalizeMagneto(data.ymagn_out));
- mLastCompass.setZ(normalizeMagneto(data.zmagn_out));
-
- mLastTemp = normalizeTemp(data.temp_out);
- }
-
- bool onSimpleUpdate() override
- {
- ADIS16405Data data;
- burstDataCollect(&data);
-
- mLastGyro.setX(normalizeGyro(data.xgyro_out));
- mLastGyro.setY(normalizeGyro(data.ygyro_out));
- mLastGyro.setZ(normalizeGyro(data.zgyro_out));
-
- mLastAccel.setX(normalizeAccel(data.xaccl_out));
- mLastAccel.setY(normalizeAccel(data.yaccl_out));
- mLastAccel.setZ(normalizeAccel(data.zaccl_out));
-
- mLastCompass.setX(normalizeMagneto(data.xmagn_out));
- mLastCompass.setY(normalizeMagneto(data.ymagn_out));
- mLastCompass.setZ(normalizeMagneto(data.zmagn_out));
-
- mLastTemp = normalizeTemp(data.temp_out);
-
- return true;
- }
-
- enum gyroFullScale
- {
- GYRO_FS_75 = 0, // 75°/sec
- GYRO_FS_150 = 1, // 150°/sec
- GYRO_FS_300 = 2 // 300°/sec (default condition)
- };
-
-private:
- // There's a typo in the datasheet saying the value is 0x4105,
- // when it's 0x4015 (== 16405)
- constexpr static uint16_t product_id_value = 0x4015;
-
- constexpr static float gyroFSMAP[] = {0.25, 0.5, 1};
-
- uint8_t gyroFS;
-
- // ADIS Register map
- enum adis_regaddr : uint8_t
- {
- // clang-format off
- // Name address default function
- ADIS_FLASH_CNT = 0x00, // N/A Flash memory write count
- ADIS_SUPPLY_OUT = 0x02, // N/A Power supply measurement
- ADIS_XGYRO_OUT = 0x04, // N/A X-axis gyroscope output
- ADIS_YGYRO_OUT = 0x06, // N/A Y-axis gyroscope output
- ADIS_ZGYRO_OUT = 0x08, // N/A Z-axis gyroscope output
- ADIS_XACCL_OUT = 0x0A, // N/A X-axis accelerometer output
- ADIS_YACCL_OUT = 0x0C, // N/A Y-axis accelerometer output
- ADIS_ZACCL_OUT = 0x0E, // N/A Z-axis accelerometer output
- ADIS_XMAGN_OUT = 0x10, // N/A X-axis magnetometer measurement
- ADIS_YMAGN_OUT = 0x12, // N/A Y-axis magnetometer measurement
- ADIS_ZMAGN_OUT = 0x14, // N/A Z-axis magnetometer measurement
- ADIS_TEMP_OUT = 0x16, // N/A Temperature output
- ADIS_AUX_ADC = 0x18, // N/A Auxiliary ADC measurement
- ADIS_XGYRO_OFF = 0x1A, // 0x0000 X-axis gyroscope bias offset factor
- ADIS_YGYRO_OFF = 0x1C, // 0x0000 Y-axis gyroscope bias offset factor
- ADIS_ZGYRO_OFF = 0x1E, // 0x0000 Z-axis gyroscope bias offset factor
- ADIS_XACCL_OFF = 0x20, // 0x0000 X-axis acceleration bias offset factor
- ADIS_YACCL_OFF = 0x22, // 0x0000 Y-axis acceleration bias offset factor
- ADIS_ZACCL_OFF = 0x24, // 0x0000 Z-axis acceleration bias offset factor
- ADIS_XMAGN_HIF = 0x26, // 0x0000 X-axis magnetometer, hard-iron factor
- ADIS_YMAGN_HIF = 0x28, // 0x0000 Y-axis magnetometer, hard-iron factor
- ADIS_ZMAGN_HIF = 0x2A, // 0x0000 Z-axis magnetometer, hard-iron factor
- ADIS_XMAGN_SIF = 0x2C, // 0x0800 X-axis magnetometer, soft-iron factor
- ADIS_YMAGN_SIF = 0x2E, // 0x0800 Y-axis magnetometer, soft-iron factor
- ADIS_ZMAGN_SIF = 0x30, // 0x0800 Z-axis magnetometer, soft-iron factor
- ADIS_GPIO_CTRL = 0x32, // 0x0000 Auxiliary digital input/output control
- ADIS_MSC_CTRL = 0x34, // 0x0006 Miscellaneous control
- ADIS_SMPL_PRD = 0x36, // 0x0001 Internal sample period (rate) control
- ADIS_SENS_AVG = 0x38, // 0x0402 Dynamic range and digital filter control
- ADIS_SLP_CNT = 0x3A, // 0x0000 Sleep mode control
- ADIS_DIAG_STAT = 0x3C, // 0x0000 System status
- ADIS_GLOB_CMD = 0x3E, // 0x0000 System command
- ADIS_ALM_MAG1 = 0x40, // 0x0000 Alarm 1 amplitude threshold
- ADIS_ALM_MAG2 = 0x42, // 0x0000 Alarm spi_master_xact_data* caller,
- // spi_master_xact_data* spi_xact, void*
- // data2 amplitude threshold
- ADIS_ALM_SMPL1 = 0x44, // 0x0000 Alarm 1 sample size
- ADIS_ALM_SMPL2 = 0x46, // 0x0000 Alarm 2 sample size
- ADIS_ALM_CTRL = 0x48, // 0x0000 Alarm control
- ADIS_AUX_DAC = 0x4A, // 0x0000 Auxiliary DAC data
- // = 0x4C to 0x55 Reserved
- ADIS_PRODUCT_ID = 0x56 // 0x4015 Product identifier
- // clang-format on
- };
-
- uint16_t readReg(adis_regaddr addr)
- {
- uint8_t rxbuf[2];
- BusSPI::write(addr, 0);
- miosix::delayUs(9); // This delay should be 75 us for low power mode
- BusSPI::read(rxbuf, 2);
- miosix::delayUs(9); // This delay should be 75 us for low power mode
- return rxbuf[0] << 8 | rxbuf[1];
- }
-
- void writeReg(adis_regaddr addr, uint16_t value)
- {
- BusSPI::write((addr + 1) | 0x80, (uint8_t)(value >> 8));
- BusSPI::write(addr | 0x80, (uint8_t)value);
- }
-
- void burstDataCollect(ADIS16405Data* data)
- {
- uint8_t raw_data[sizeof(ADIS16405Data)];
- BusSPI::read16((ADIS_GLOB_CMD) << 8, raw_data, sizeof(ADIS16405Data));
- parseBurstData(raw_data, data);
- }
-
- void parseBurstData(uint8_t* raw, ADIS16405Data* data)
- {
- // TODO: check nd and ea bits
- data->supply_out = (raw[0] << 8 | raw[1]) & 0x3FFF;
- data->xgyro_out = signExtend((raw[2] << 8 | raw[3]) & 0x3FFF, 14);
- data->ygyro_out = signExtend((raw[4] << 8 | raw[5]) & 0x3FFF, 14);
- data->zgyro_out = signExtend((raw[6] << 8 | raw[7]) & 0x3FFF, 14);
- data->xaccl_out = signExtend((raw[8] << 8 | raw[9]) & 0x3FFF, 14);
- data->yaccl_out = signExtend((raw[10] << 8 | raw[11]) & 0x3FFF, 14);
- data->zaccl_out = signExtend((raw[12] << 8 | raw[13]) & 0x3FFF, 14);
- data->xmagn_out = signExtend((raw[14] << 8 | raw[15]) & 0x3FFF, 14);
- data->ymagn_out = signExtend((raw[16] << 8 | raw[17]) & 0x3FFF, 14);
- data->zmagn_out = signExtend((raw[18] << 8 | raw[19]) & 0x3FFF, 14);
- data->temp_out = signExtend((raw[20] << 8 | raw[21]) & 0x0FFF, 12);
- data->aux_adc = (raw[22] << 8 | raw[23]) & 0x0FFF;
- }
-
- int16_t signExtend(uint16_t val, uint8_t bits)
- {
- if ((val & (1 << (bits - 1))) != 0)
- {
- val = val - (1 << bits);
- }
- return val;
- }
-
- inline float normalizeSupply(uint16_t val)
- {
- return static_cast<float>(val) * 2.418e-3f; // [V]
- }
-
- inline float normalizeAccel(int16_t val)
- {
- return static_cast<float>(val) * 3.33e-3f * EARTH_GRAVITY; // [g]
- }
-
- inline float normalizeGyro(int16_t val)
- {
- return static_cast<float>(val) * 0.05f * gyroFSMAP[gyroFS] *
- DEGREES_TO_RADIANS; // [rad/s]
- }
-
- inline float normalizeMagneto(int16_t val)
- {
- return static_cast<float>(val) * 0.5e-3f; // [gausss]
- }
-
- inline float normalizeTemp(int16_t val)
- {
- return static_cast<float>((val)*0.14f + 25); // [C deg]
- }
-
- inline float normalizeADC(uint16_t val)
- {
- return static_cast<float>(val) * 0.806e-6f; // [V]
- }
-};
-
-template <typename BusSPI, typename rstPin>
-constexpr float ADIS16405<BusSPI, rstPin>::gyroFSMAP[];
diff --git a/old_examples/shared/sensors/ADIS16405/ADIS16405Data.h b/old_examples/shared/sensors/ADIS16405/ADIS16405Data.h
deleted file mode 100644
index c9e2e1ab4cfe3a428d584b3f843349037eac24ec..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/ADIS16405/ADIS16405Data.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <cstdint>
-#include <ostream>
-#include <string>
-
-/*
- * Burst data collection. This establishes right datatype for
- * the registers because trying to work with 12 or 14 bit twos
- * complement that doesn't sign extend to 16 bits is unpleasant.
- */
-#pragma pack(1)
-struct ADIS16405Data
-{
- uint16_t supply_out; // Power supply measurement
- int16_t xgyro_out; // X-axis gyroscope output
- int16_t ygyro_out; // Y-axis gyroscope output
- int16_t zgyro_out; // Z-axis gyroscope output
- int16_t xaccl_out; // X-axis accelerometer output
- int16_t yaccl_out; // Y-axis accelerometer output
- int16_t zaccl_out; // Z-axis accelerometer output
- int16_t xmagn_out; // X-axis magnetometer measurement
- int16_t ymagn_out; // Y-axis magnetometer measurement
- int16_t zmagn_out; // Z-axis magnetometer measurement
- int16_t temp_out; // Temperature output
- uint16_t aux_adc; // Auxiliary ADC measurement
-
- static std::string header()
- {
- return "supply_out,xgyro_out,ygyro_out,zgyro_out,xaccl_out,yaccl_out,"
- "zaccl_out,xmagn_out,ymagn_out,zmagn_out,temp_out,aux_adc\n";
- }
-
- void print(std::ostream& os) const
- {
- os << supply_out << "," << xgyro_out << "," << ygyro_out << ","
- << zgyro_out << "," << xaccl_out << "," << yaccl_out << ","
- << zaccl_out << "," << xmagn_out << "," << ymagn_out << ","
- << zmagn_out << "," << temp_out << "," << aux_adc << "\n";
- }
-};
-#pragma pack()
diff --git a/old_examples/shared/sensors/FXAS21002.h b/old_examples/shared/sensors/FXAS21002.h
deleted file mode 100644
index 6eddc14cf97123848f31e1e5f67aaa2189fe4b6d..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/FXAS21002.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Authors: Alain Carlucci, Matteo Piazzolla, Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Sensor.h"
-
-template <typename Bus>
-class FXAS21002 : public GyroSensor
-{
-public:
- FXAS21002(uint8_t curScale) : mCurScale(curScale & 0x03) {}
-
- bool init() override
- {
- uint8_t whoami = Bus::read(REG_WHO_AM_I);
-
- if (whoami != who_am_i_value)
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- Bus::write(REG_CTRL1, 0b01000000);
- uint8_t timeout = 20;
- while ((Bus::read(REG_CTRL1) & 0b01000000) && --timeout > 0)
- {
- miosix::Thread::sleep(1);
- }
-
- if (timeout == 0)
- {
- last_error = ERR_RESET_TIMEOUT;
- return false;
- }
-
- // Set current scale
- Bus::write(REG_CTRL0, mCurScale);
-
- // Datarate 100HZ + Enable READY bit
- Bus::write(REG_CTRL1, (DR_100HZ << 2) | 0x02);
-
- // Enable data ready interrupt and set as active high
- Bus::write(REG_CTRL2, 0b00000110);
-
- // Enable wrap to one function
- // Auto increment rolls back from z_axis_lsb to x_axis_msb
- Bus::write(REG_CTRL3, Bus::read(REG_CTRL3) | 0b00001000);
-
- // Wait until boot is completed
- timeout = 20;
- while (!(Bus::read(REG_INT_SRC_FLAG) & 0b00001000) && --timeout > 0)
- {
- miosix::Thread::sleep(1);
- }
-
- if (timeout == 0)
- {
- last_error = ERR_RESET_TIMEOUT;
- return false;
- }
-
- return true;
- }
-
- // Performs a device self test, see datasheet for further details
- bool selfTest() override
- {
- // Trigger a self test
- Bus::write(REG_CTRL1, Bus::read(REG_CTRL1) | 0b00010000);
-
- int16_t xAxis =
- (Bus::read(REG_OUT_X_MSB) << 8) | Bus::read(REG_OUT_X_LSB);
- int16_t yAxis =
- (Bus::read(REG_OUT_Y_MSB) << 8) | Bus::read(REG_OUT_Y_LSB);
- int16_t zAxis =
- (Bus::read(REG_OUT_Z_MSB) << 8) | Bus::read(REG_OUT_Z_LSB);
-
- if (xAxis < 7000 || xAxis > 25000)
- {
- last_error = ERR_X_SELFTEST_FAIL;
- return false;
- }
-
- if (yAxis < 7000 || yAxis > 25000)
- {
- last_error = ERR_Y_SELFTEST_FAIL;
- return false;
- }
-
- if (zAxis < 7000 || zAxis > 25000)
- {
- last_error = ERR_Z_SELFTEST_FAIL;
- return false;
- }
-
- return true;
- }
-
- std::vector<SPIRequest> buildDMARequest() override
- {
- std::vector<uint8_t> data = {REG_OUT_X_MSB | 0x80, 0, 0, 0, 0, 0, 0};
-
- return {SPIRequest(0, Bus::getCSPin(), data)};
- }
-
- void onDMAUpdate(const SPIRequest& req) override
- {
- const auto& r = req.readResponseFromPeripheral();
- int16_t data[3];
- memcpy(data, &r[1], sizeof(data));
-
- for (int i = 0; i < 3; i++)
- data[i] = fromBigEndian16(data[i]);
-
- mLastGyro.setX(normalizeGyro(data[0]));
- mLastGyro.setY(normalizeGyro(data[1]));
- mLastGyro.setZ(normalizeGyro(data[2]));
- }
-
- bool onSimpleUpdate() override { return false; }
-
- /* UNUSED CODE
-
- // Set operating mode. Modes available are: STANDBY, READY, ACTIVE
- void setPowerMode(uint8_t mode)
- {
- uint8_t regCtrl1 = Bus::read(REG_CTRL1);
-
- regCtrl1 &= ~0x03; //clear last two bits
- regCtrl1 |= mode; //set mode
-
- Bus::write(REG_CTRL1, regCtrl1);
- }
-
- void setSampleRate(uint8_t rate)
- {
- uint8_t regCtrl1 = Bus::read(REG_CTRL1);
-
- regCtrl1 &= ~0b00011100; //clear sample rate bits
- regCtrl1 |= rate; //set rate
-
- Bus::write(REG_CTRL1, regCtrl1);
- }
-
- void setFullScaleRange(uint8_t range)
- {
- uint8_t regCtrl0 = Bus::read(REG_CTRL0);
- range &= 0x03;
-
- regCtrl0 &= ~(0x03); //clear full scale range bits
- regCtrl0 |= range; //set range
-
- mCurScale = range;
- Bus::write(REG_CTRL0, regCtrl0);
- }
-
- // Set internal low pass filter bandwidth.
- // See datasheet at page 39 for further details
- void setBandwidth(uint8_t bandwidth)
- {
- uint8_t regCtrl0 = Bus::read(REG_CTRL0);
-
- regCtrl0 &= ~0b11000000; //clear bandwidth bits
- regCtrl0 |= bandwidth; //set range
-
- Bus::write(REG_CTRL0, regCtrl0);
- }
-
- // Set internal high pass filter bandwidth.
- // See datasheet at page 39 for further details
- void setHiPassFreq(uint8_t freq)
- {
- uint8_t regCtrl0 = Bus::read(REG_CTRL0);
-
- regCtrl0 &= ~0b00011000; //clear full hi pass freq bits
- regCtrl0 |= freq; //set freq
-
- Bus::write(REG_CTRL0, regCtrl0);
- }
-
- void enableHiPassFiter()
- {
- Bus::write(REG_CTRL0, Bus::read(REG_CTRL0) | 0b00000100);
- }
-
- void disableHiPassFiter()
- {
- Bus::write(REG_CTRL0, Bus::read(REG_CTRL0) & (~0b00000100));
- }
- */
-
- // clang-format off
- enum dataRates
- {
- DR_800HZ = 0,
- DR_400HZ = 1,
- DR_200HZ = 2,
- DR_100HZ = 3,
- DR_50HZ = 4,
- DR_25HZ = 5,
- DR_12_5HZ = 6
- };
-
- enum opModes
- {
- STANDBY = 0x00,
- READY = 0x01,
- ACTIVE = 0x02
- };
-
- enum gyroFullScale
- {
- DPS2000 = 0x00,
- DPS1000 = 0x01,
- DPS500 = 0x02,
- DPS250 = 0x03
- };
- // clang-format on
-
-private:
- constexpr static uint8_t who_am_i_value = 0xD7;
- constexpr static float gyroFSMAP[] = {2000, 1000, 500, 250};
- uint8_t mCurScale;
-
- // clang-format off
- enum regMap
- {
- REG_STATUS = 0x00,
- REG_OUT_X_MSB = 0x01,
- REG_OUT_X_LSB = 0x02,
- REG_OUT_Y_MSB = 0x03,
- REG_OUT_Y_LSB = 0x04,
- REG_OUT_Z_MSB = 0x05,
- REG_OUT_Z_LSB = 0x06,
- REG_DR_STATUS = 0x07,
- REG_FIFO_STATUS = 0x08,
- REG_FIFO_SETUP = 0x09,
- REG_FIFO_EVENT = 0x0A,
- REG_INT_SRC_FLAG = 0x0B,
- REG_WHO_AM_I = 0x0C,
- REG_CTRL0 = 0x0D,
- REG_RT_CFG = 0x0E,
- REG_RT_SRC = 0x0F,
- REG_RT_THF = 0x10,
- REG_RT_CNT = 0x11,
- REG_TEMP = 0x12,
- REG_CTRL1 = 0x13,
- REG_CTRL2 = 0x14,
- REG_CTRL3 = 0x15
- };
- // clang-format on
-
- inline constexpr float normalizeGyro(int16_t val)
- {
- return static_cast<float>(val) / 32768.0f * gyroFSMAP[mCurScale] *
- DEGREES_TO_RADIANS;
- }
-};
-
-template <typename Bus>
-constexpr float FXAS21002<Bus>::gyroFSMAP[];
diff --git a/old_examples/shared/sensors/LM75B.h b/old_examples/shared/sensors/LM75B.h
deleted file mode 100644
index 4643fcf0d36eb48e9479d768b3cbfbc6c67cfbe4..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/LM75B.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Alessio Galluccio
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-// TODO sistemare la codifica di {0x80, 0x00}, che
-// per qualche ragione, diventa positiva
-
-#pragma once
-
-#include <math/Stats.h>
-
-#include "Sensor.h"
-
-template <typename BusType>
-class LM75B : public TemperatureSensor
-{
-public:
- // @param slaveAddr address of the sensor you want to use
- LM75B(uint8_t slaveAddr) : slave_addr(static_cast<uint8_t>(slaveAddr))
- {
- mLastTemp = 7;
- }
-
- bool selfTest() override
- {
- bool flag_self_test = 1; // 1 if test are passed, 0 if not
-
- // TEST: reading default value of THYST register
- uint8_t value_thyst;
- BusType::read(slave_addr, REG_THYST, &value_thyst, sizeof(uint8_t));
- if (value_thyst == default_value_thyst)
- {
- TRACE("\nReading correct value of THYST register in LM75B");
- }
- else
- {
- TRACE("\nWarning: reading wrong value of THYST register in LM75B");
- flag_self_test = 0;
- }
-
- // TEST: reading default value of TOS register
- uint8_t value_tos;
- BusType::read(slave_addr, REG_TOS, &value_tos, sizeof(uint8_t));
- if (value_tos == default_value_tos)
- {
- TRACE("\nReading correct value of TOS register in LM75B");
- }
- else
- {
- TRACE("\nWarning: reading wrong value of TOS register in LM75B");
- flag_self_test = 0;
- }
-
- // TEST: standard deviation of temperature value
- float stdev;
- Stats calc_stats;
-
- for (int i = 0; i < SELF_TEST_NUM_SAMPLES; i++)
- {
- onSimpleUpdate();
- sample[i] = mLastTemp;
- }
-
- for (int i = 0; i < SELF_TEST_NUM_SAMPLES; i++)
- {
- // temperature can't be out of range of sensor
- if (sample[i] < -125.0 && sample[i] > 125.0)
- {
- return false;
- }
- }
-
- for (int i = 0; i < SELF_TEST_NUM_SAMPLES; i++)
- {
- calc_stats.add(sample[i]);
- }
- stdev = calc_stats.getStats().stdev;
-
- if (stdev < MAX_STDEV_VALUE)
- {
- TRACE("\nStandard deviation of temperature is correct in LM75B");
- }
- else
- {
- TRACE(
- "\nWarning: Standard deviation of temparature is out of range "
- "in LM75B");
- flag_self_test = 0;
- }
-
- if (flag_self_test == 1)
- {
- return 1;
- }
- else
- {
- return 0;
- }
- }
-
- bool init() override
- {
- uint8_t conf = static_cast<uint8_t>(CONF_NORM);
- BusType::write(slave_addr, REG_CONF, &conf, sizeof(uint8_t));
-
- // Check if the register was set correctly
- BusType::read(slave_addr, REG_CONF, &conf, sizeof(uint8_t));
- bool conf_ok = (conf == static_cast<uint8_t>(CONF_NORM));
-
- return conf_ok;
- }
-
- bool onSimpleUpdate() override
- {
- mLastTemp = updateTemp();
- return true;
- }
-
- float getTemp() { return mLastTemp; }
-
- enum SlaveAddress : uint8_t
- {
- ADDR_1 = 0x48, // first TempSensor
- ADDR_2 = 0x49, // second TempSensor
- ADDR_3 = 0x50 // third TempSensor (not in Rocksanne)
- };
-
-private:
- static constexpr int SELF_TEST_NUM_SAMPLES = 10;
- const uint8_t slave_addr;
- uint8_t temp_array[2] = {0, 0};
-
- enum Registers
- {
- REG_CONF = 0x01, // R/W
- REG_TEMP = 0x00, // R only
- REG_TOS = 0x03, // R/W
- REG_THYST = 0x02 // R/W
- };
-
- enum ConfCommands
- {
- CONF_NORM = 0x00
- };
-
- // for testing
- const uint8_t default_value_thyst = 75;
- const uint8_t default_value_tos = 80;
- const float MAX_STDEV_VALUE =
- 100; // max Standard deviation value accepted for temperature samples
- float sample[SELF_TEST_NUM_SAMPLES];
-
- float updateTemp()
- {
- BusType::read(slave_addr, REG_TEMP, temp_array, sizeof(uint16_t));
- // TRACE("Read: %x %x\n", temp_array[0], temp_array[1]);
- return computeTemp(temp_array);
- }
-
- // the temperature is saved in two bytes of the temp register
- // they must be swapped, concatenated and shifted right by 5 bits.
- // The resulting value must be multiplicated by 0.125
- float computeTemp(uint8_t *temp_array)
- {
- bool isNegative = false;
-
- // if most significant bit is 1, temperature is negative
- constexpr int MS_BIT_VALUE = 0x80;
- if (temp_array[0] >= MS_BIT_VALUE)
- {
- isNegative = true;
- }
-
- // they must be swapped, because the software reads the LSByte before
- // MSByte
- uint8_t temp_for_swap;
- temp_for_swap = temp_array[0];
- temp_array[0] = temp_array[1];
- temp_array[1] = temp_for_swap;
-
- int16_t temp;
-
- // TRACE("After swap: %x %x\n", temp_array[0], temp_array[1]);
- memcpy(&temp, temp_array, sizeof(int16_t));
- // TRACE("UINT16: %x\n", temp);
-
- if (isNegative)
- {
- // Two's complement
- temp = ~(temp);
- temp += 1;
- }
-
- // the five least significant bits must be eliminated
- uint16_t rightShift;
- constexpr int16_t RIGHT_SHIFT_5 = 0x20;
-
- rightShift = temp / RIGHT_SHIFT_5;
- // TRACE("After right shift: %x, %d\n", rightShift, rightShift);
- if (isNegative)
- {
- // TRACE("negative value returned");
- return -float(int16_t(rightShift)) * 0.125;
- }
- else
- {
- return float(int16_t(rightShift)) * 0.125;
- }
- }
-};
diff --git a/old_examples/shared/sensors/LPS331AP.h b/old_examples/shared/sensors/LPS331AP.h
deleted file mode 100644
index 69fd700f76dd55d2b27a5ca49b2c7f06564c0906..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/LPS331AP.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Sensor.h"
-
-template <typename Bus>
-class LPS331AP : public PressureSensor, public TemperatureSensor
-{
- struct data_t
- {
- int32_t press;
- int16_t temp;
- };
-
-public:
- LPS331AP(uint8_t samplingSpeed)
- {
- mLastPressure = 0.0f;
- mLastTemp = 0.0f;
- mHighSpeed = (samplingSpeed == SS_25HZ);
- }
-
- bool init()
- {
- uint8_t whoami = Bus::read(REG_WHO_AM_I);
-
- if (whoami != who_am_i_value)
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- uint8_t reg1 = mHighSpeed ? 0xf0 : 0xe0;
- uint8_t reg2 = mHighSpeed ? 0x69 : 0x7a;
- Bus::write(REG_CTRL1, reg1); // Power on, 3-wire SPI
- Bus::write(REG_RES_CONF, reg2); // AVG_P: 384, AVG_T: 64
-
- return true;
- }
-
- bool selfTest() { return false; }
-
- std::vector<SPIRequest> buildDMARequest() override
- {
- return {
- SPIRequest(0, Bus::getCSPin(),
- {
- REG_STATUS | 0xc0, 0, 0, 0, 0, // pressure (int32_t)
- 0, 0 // temperature (int16_t)
- })};
- }
-
- void onDMAUpdate(const SPIRequest& req) override
- {
- const auto& r = req.readResponseFromPeripheral();
- const data_t* data = (const data_t*)&r[1];
-
- // Remove status and realign bytes
- int32_t pressure = data->press >> 8;
-
- mLastPressure = normalizePressure(pressure);
- mLastTemp = normalizeTemp(data->temp);
- }
-
- bool onSimpleUpdate() override { return false; }
-
- // clang-format off
- enum samplingSpeed
- {
- SS_25HZ = 0, // 25Hz
- SS_12HZ5 = 1, // 12.5Hz
- };
- // clang-format on
-
-private:
- constexpr static uint8_t who_am_i_value = 0xbb;
- uint8_t mHighSpeed;
-
- inline constexpr float normalizePressure(int32_t val)
- {
- // Page 28 @ Datasheet
- return static_cast<float>(val) / 4096.0f;
- }
-
- inline constexpr float normalizeTemp(int16_t val)
- {
- // Page 29 @ Datasheet
- return static_cast<float>(val) / 480.0f + 42.5f;
- }
-
- // clang-format off
- enum regMap {
- REG_WHO_AM_I = 0x0f,
- REG_RES_CONF = 0x10,
-
- REG_CTRL1 = 0x20,
- REG_CTRL2 = 0x21,
- REG_CTRL3 = 0x22,
- REG_INT_CFG = 0x23,
-
- REG_STATUS = 0x27,
-
- REG_PRESS_OUT = 0x28,
- REG_TEMP_OUT = 0x2b,
- };
- // clang-format on
-};
diff --git a/old_examples/shared/sensors/LSM6DS3H/LSM6DS3H.h b/old_examples/shared/sensors/LSM6DS3H/LSM6DS3H.h
deleted file mode 100644
index d36bf2a582f7598efa6d358a5ecb342cd91d8069..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/LSM6DS3H/LSM6DS3H.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-#include <utils/Debug.h>
-
-#include "../Sensor.h"
-#include "Common.h"
-#include "miosix.h"
-
-/** ********ATTENTION***********
- * @warning Once upon a time, this driver was working, but due to hardware
- * problems we were unable to confirm it and test it properly. If you need this,
- * you should test it a bit before using it in production code.
- */
-
-template <typename Bus>
-class LSM6DS3H : public GyroSensor,
- public AccelSensor,
- public CompassSensor,
- public TemperatureSensor
-{
-#pragma pack(1)
- // __extension__ is needed to prevent compiler warnings for anonymous
- // structs
- typedef union
- {
- __extension__ struct
- {
- int16_t temp;
- int16_t gyro[3];
- int16_t accel[3];
- };
- int16_t buf[8];
- } lsmData_t;
-
-#pragma pack()
-
-public:
- LSM6DS3H(uint8_t accelFullScale, uint16_t gyroFullScale)
- {
- accelFS = accelFullScale;
- gyroFS = gyroFullScale;
- }
-
- bool init() override
- {
- // SPI clock frequency up to 10 MHz
- // The device is compatible with SPI modes 0 and 3
-
- uint8_t whoami = Bus::read(RegMap::WHO_AM_I);
- TRACE("[LSM] expected: %x actual: %x\n", whoami_value, whoami);
- if (whoami != whoami_value)
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- // Reset device
- uint8_t reg = Bus::read(RegMap::CTRL3_C);
- Bus::write(reg | 0x01);
-
- miosix::Thread::sleep(100);
-
- // clang-format off
- uint8_t init_data[][2] =
- {
- {RegMap::CTRL3_C, 0x44}, // Register address automatically incremented during a multiple
- // byte access with a serial interface; LSB @ lower address;
- // SPI 4 wire; Output registers not updated until MSB and LSB
- // have been read
- {RegMap::CTRL1_XL, (uint8_t) (0x70 | (accelFS << 2))}, // Accel ODR to 833 Hz,
- // Anti-aliasing filter to 400 hz
- // {RegMap::CTRL5_C, 0x60}, // Rounding read enabled for both accel and gyro
- {RegMap::CTRL2_G, (uint8_t) (0x70 | (gyroFS << 2))}, // Gyro ODR to 833 Hz
- };
- // clang-format on
-
- for (size_t i = 0; i < sizeof(init_data) / sizeof(init_data[0]); i++)
- Bus::write(init_data[i][0], init_data[i][1]);
-
- return true;
- }
-
- bool selfTest() override { return true; }
-
- bool onSimpleUpdate()
- {
- lsmData_t raw_data;
- uint8_t buf[20];
-
- // Read temp, gyro, accel
- Bus::read(RegMap::OUT_TEMP_L, buf, 14);
- memcpy(&raw_data.buf, buf, 14);
-
- mLastTemp = normalizeTemp(raw_data.temp);
-
- mLastGyro.setX(normalizeGyro(raw_data.gyro[0]));
- mLastGyro.setY(normalizeGyro(raw_data.gyro[1]));
- mLastGyro.setZ(normalizeGyro(raw_data.gyro[2]));
-
- mLastAccel.setX(normalizeAccel(raw_data.accel[0]));
- mLastAccel.setY(normalizeAccel(raw_data.accel[1]));
- mLastAccel.setZ(normalizeAccel(raw_data.accel[2]));
-
- return true;
- }
-
- // clang-format off
- enum gyroFullScale
- {
- GYRO_FS_250 = 0,
- GYRO_FS_500 = 1,
- GYRO_FS_1000 = 2,
- GYRO_FS_2000 = 3
- };
-
- enum accelFullScale
- {
- ACC_FS_2G = 0, // Do not change this sequence
- ACC_FS_4G = 2,
- ACC_FS_8G = 3,
- ACC_FS_16G = 1
- };
- // clang-format on
-
-private:
- constexpr static uint8_t whoami_value = 0x69;
- constexpr static float accelFSMAP[4] = {0.061, 0.488, 0.122, 0.244};
- constexpr static float gyroFSMAP[4] = {8.75, 17.50, 35.0, 70.0};
- uint8_t accelFS;
- uint16_t gyroFS;
-
- inline float normalizeAccel(int16_t val)
- {
- return static_cast<float>(val) / 1000.0f * accelFSMAP[accelFS] *
- EARTH_GRAVITY; // [m/ss]
- }
-
- inline float normalizeGyro(int16_t val)
- {
- return static_cast<float>(val) / 1000.0f * gyroFSMAP[gyroFS] *
- DEGREES_TO_RADIANS; // [rad/s]
- }
-
- inline float normalizeTemp(int16_t val)
- {
- return static_cast<float>(val) / 16.0f + 25.0f; // [deg C]
- }
-
- enum RegMap
- {
- WHO_AM_I = 0x0F, // default value
-
- // Accelerometer and gyroscope control registers
- CTRL1_XL = 0x10,
- CTRL2_G = 0x11,
- CTRL3_C = 0x12,
- CTRL4_C = 0x13,
- CTRL5_C = 0x14,
- CTRL6_C = 0x15,
- CTRL7_G = 0x16,
- CTRL8_XL = 0x17,
- CTRL9_XL = 0x18,
- CTRL10_C = 0x19,
-
- // Temperature output registers
- OUT_TEMP_L = 0x20,
- OUT_TEMP_H = 0x21,
-
- // Gyro data registers
- OUT_X_L_G = 0x22,
- OUT_X_H_G = 0x23,
- OUT_Y_L_G = 0x24,
- OUT_Y_H_G = 0x25,
- OUT_Z_L_G = 0x26,
- OUT_Z_H_G = 0x27,
-
- // Accelerometer output registers
- OUT_X_L_XL = 0x28,
- OUT_X_H_XL = 0x29,
- OUT_Y_L_XL = 0x2A,
- OUT_Y_H_XL = 0x2B,
- OUT_Z_L_XL = 0x2C,
- OUT_Z_H_XL = 0x2D,
-
- // STATUS register
- STATUS_REG = 0X1E
- };
-};
-
-template <typename Bus>
-constexpr float LSM6DS3H<Bus>::accelFSMAP[];
-
-template <typename Bus>
-constexpr float LSM6DS3H<Bus>::gyroFSMAP[];
diff --git a/old_examples/shared/sensors/LSM6DS3H/LSM6DS3HData.h b/old_examples/shared/sensors/LSM6DS3H/LSM6DS3HData.h
deleted file mode 100644
index 128707df272bcdda304895018fa35f71c28b5cea..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/LSM6DS3H/LSM6DS3HData.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <math/Vec3.h>
-
-#include <ostream>
-
-struct LSM6DS3HData
-{
- long long timestamp;
- Vec3 accel;
- Vec3 gyro;
- float temp;
-
- static std::string header()
- {
- return "timestamp,acc_x,acc_y,acc_z,angularSpeedX,angularSpeedY,"
- "angularSpeedZ\n";
- }
-
- void print(std::ostream& os) const
- {
- os << timestamp << "," << accel.getX() << "," << accel.getY() << ","
- << accel.getZ() << "," << gyro.getX() << "," << gyro.getY() << ","
- << gyro.getZ() << "\n";
- }
-};
diff --git a/old_examples/shared/sensors/MAX21105.h b/old_examples/shared/sensors/MAX21105.h
deleted file mode 100644
index e8fe63d01f021c2bbbdeee23944c7f6157d0ac57..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/MAX21105.h
+++ /dev/null
@@ -1,316 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Authors: Matteo Piazzolla, Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-#include <interfaces/endianness.h>
-
-#include "Sensor.h"
-
-template <class Bus>
-class MAX21105 : public AccelSensor, public GyroSensor, public TemperatureSensor
-{
-#pragma pack(1)
- union rawdata_t
- {
- __extension__ struct
- {
- int16_t gyro[3];
- int16_t accel[3];
- int16_t temp;
- };
- int16_t raw[7];
- };
-#pragma pack()
-public:
- MAX21105(uint8_t accelFullScale, uint8_t gyroFullScale)
- {
- accelFS = accelFullScale & 0x03;
- gyroFS = gyroFullScale & 0x03;
- mLastTemp = 0.0f;
- }
-
- ~MAX21105() {}
-
- bool init() override
- {
- uint8_t who_am_i = Bus::read(WHO_AM_I);
-
- if (who_am_i != who_am_i_value)
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- // Init this sensor
- uint8_t init_data[][2] = {
- {MIF_CFG, 0x29}, // SPI 4 wire, I2C OFF (important!)
- {EXT_STATUS, 0x00}, // Choose the bank 0
- {SET_PWR, 0x00}, // Power down
-
- // Gyro: 2kHz BW
- {SNS_CFG_1, (uint8_t)(0x20 | gyroFS)},
- {SNS_CFG_2, 0x10},
-
- // Accel: Set scale & no self test
- {SET_ACC_PWR, (uint8_t)(0x00 | (accelFS << 6))},
- {ACC_CFG_1, 0x02}, // 400Hz
- {ACC_CFG_2, 0x00}, // Low pass filter
- {SET_PWR, 0x78}, // Power up (Accel + Gyro) Low-Noise
- };
-
- for (size_t i = 0; i < sizeof(init_data) / sizeof(init_data[0]); i++)
- {
- Bus::write(init_data[i][0], init_data[i][1]);
- miosix::Thread::sleep(1);
- }
-
- return true;
- }
-
- bool selfTest() override
- {
- /*
- if(!SelfTestAcc()) {
- last_error = ERR_ACCEL_SELFTEST;
- return false;
- }
- if(!SelfTestGyro()) {
- last_error = ERR_GYRO_SELFTEST;
- return false;
- }
- return true;
- */
- return false;
- }
-
- std::vector<SPIRequest> buildDMARequest() override
- {
- return {SPIRequest(0, Bus::getCSPin(),
- {
- (GYRO_X_H | 0x80), 0, 0, 0, 0, 0, 0, // gyro
- 0, 0, // accel
- 0, 0, 0, 0, 0, 0, // temp
- })};
- }
-
- void onDMAUpdate(const SPIRequest& req) override
- {
- const auto& r = req.readResponseFromPeripheral();
- const int16_t* ptr = (const int16_t*)&r[1];
- rawdata_t raw_data;
-
- constexpr size_t dSize = 7; // 3 (gyro) + 3 (accel) + 1 (temp)
- for (size_t i = 0; i < dSize; i++)
- raw_data.raw[i] = fromBigEndian16(ptr[i]);
-
- mLastAccel.setX(normalizeAccel(raw_data.accel[0]));
- mLastAccel.setY(normalizeAccel(raw_data.accel[1]));
- mLastAccel.setZ(normalizeAccel(raw_data.accel[2]));
-
- mLastGyro.setX(normalizeGyro(raw_data.gyro[0]));
- mLastGyro.setY(normalizeGyro(raw_data.gyro[1]));
- mLastGyro.setZ(normalizeGyro(raw_data.gyro[2]));
-
- mLastTemp = normalizeTemp(raw_data.temp);
- }
-
- bool onSimpleUpdate() override { return false; }
-
- // clang-format off
- enum accelFullScale
- {
- ACC_FS_16G = 0,
- ACC_FS_8G = 1,
- ACC_FS_4G = 2,
- ACC_FS_2G = 3,
- };
-
- enum gyroFullScale
- {
- GYRO_FS_2000 = 0,
- GYRO_FS_1000 = 1,
- GYRO_FS_500 = 2,
- GYRO_FS_250 = 3,
- };
- // clang-format on
-
-private:
- uint8_t accelFS, gyroFS;
-
- static constexpr const uint8_t who_am_i_value = 0xb4;
- static constexpr const float accelFSMAP[] = {16.0, 8.0, 4.0, 2.0};
- static constexpr const float gyroFSMAP[] = {2000, 1000, 500, 250};
-
- inline constexpr float normalizeAccel(int16_t val)
- {
- return static_cast<float>(val) / 32768.0f * accelFSMAP[accelFS] *
- EARTH_GRAVITY;
- }
-
- inline constexpr float normalizeGyro(int16_t val)
- {
- return static_cast<float>(val) / 32768.0f * gyroFSMAP[gyroFS] *
- DEGREES_TO_RADIANS;
- }
-
- inline constexpr float normalizeTemp(int16_t val)
- {
- return static_cast<float>(val) / 256.0f;
- }
-
- // clang-format off
- enum regMap
- {
- SET_PWR = 0x00,
- SNS_CFG_1 = 0x01,
- SNS_CFG_2 = 0x02,
- SNS_CFG_3 = 0x03,
- SET_ACC_PWR = 0x04,
- ACC_CFG_1 = 0x05,
- ACC_CFG_2 = 0x06,
- SET_TEMP_DR = 0x13,
- MIF_CFG = 0x16,
- OTP_STS_CFG = 0x1C,
-
- WHO_AM_I = 0x20,
- EXT_STATUS = 0x22,
-
- GYRO_X_H = 0x24,
- GYRO_X_L = 0x25,
- GYRO_Y_H = 0x26,
- GYRO_Y_L = 0x27,
- GYRO_Z_H = 0x28,
- GYRO_Z_L = 0x29,
- ACCE_X_H = 0x2A,
- ACCE_X_L = 0x2B,
- ACCE_Y_H = 0x2C,
- ACCE_Y_L = 0x2D,
- ACCE_Z_H = 0x2E,
- ACCE_Z_L = 0x2F,
- TEMP_H = 0x30,
- TEMP_L = 0x31,
-
- TRM_BNK_REG = 0x38,
- FIFO_COUNT = 0x3C,
- FIFO_STATUS = 0x3D,
- FIFO_DATA = 0x3E,
- RST_REG = 0x3F
- };
- // clang-format on
-
- // -------------------- the hell down here
-
- // TODO: capire se ha senso
- /*
- Self Test del Gyroscopio,
- Prendo 5 campioni del giroscopio e ne faccio la media,
- imposto la modalità self test e ne prendo altri 5 facendone nuovamente la
- media. Se la distanza è maggiore di quella nel datasheet o non passa la
- condizione X>0, Y<0, Z>0 il test fallisce e ritorna falso
- */
- /*
- bool SelfTestGyro() {
- constexpr uint8_t min_x = 8;
- constexpr uint8_t min_y = -50;
- constexpr uint8_t min_z = 8;
- constexpr uint8_t max_x = 50;
- constexpr uint8_t max_y = -8;
- constexpr uint8_t max_z = 50;
-
- // Self Test Gyroscopio
- float Ax_no_test=0;
- float Ay_no_test=0;
- float Az_no_test=0;
-
- for(int i=0;i<5;++i){
- //sleep
- Ax_no_test+=readGyroX();
- Ay_no_test+=readGyroY();
- Az_no_test+=readGyroZ();
- }
-
- Ax_no_test=Ax_no_test/5;
- Ay_no_test=Ay_no_test/5;
- Az_no_test=Az_no_test/5;
-
- //seleziono il bank 0 dei registri
- writeReg(EXT_STATUS,0x00);
- //Power Down
- writeReg(SET_PWR,0x78);
- // Gyro: 2kHz BW, 1000dps FS
- //Testing Positive sign {+X, -Y, +Z}
- writeReg(SNS_CFG_1,0x7c);
- writeReg(SNS_CFG_2,0x10);
- // Acc Low-Noise + Gyro Low-Noise
- writeReg(SET_PWR,0x78);
- //sleep
-
- float Ax_test=0;
- float Ay_test=0;
- float Az_test=0;
-
- for(int i=0;i<5;++i){
- Ax_test+=readGyroX();
- Ay_test+=readGyroY();
- Az_test+=readGyroZ();
- }
-
- Ax_test=Ax_test/5;
- Ay_test=Ay_test/5;
- Az_test=Az_test/5;
-
- float deltaX,deltaY,deltaZ;
- deltaX = std::abs(Ax_test - Ax_no_test);
- deltaY = -std::abs(Ay_test - Ay_no_test);
- deltaZ = std::abs(Az_test - Az_no_test);
-
- if ((min_x <= deltaX && deltaX <= max_x) &&
- (min_y <= deltaY && deltaY <= max_y) &&
- (min_z <= deltaZ && deltaZ <= max_z))
- return true;
- return false;
- }
-
- Vec3 readGyro() {
- return Vec3(readGyroX(), readGyroY(), readGyroZ());
- }
-
- Vec3 readAccelerometer() {
- return Vec3(readAccX(), readAccY(), readAccZ());
- }
-
- bool SelfTestAcc(){
- //16g X positive force
- writeReg(SET_ACC_PWR,0x8);
- //TODO: test acc
- return true;
- }
- */
-};
-
-template <typename Bus>
-constexpr float MAX21105<Bus>::accelFSMAP[];
-
-template <typename Bus>
-constexpr float MAX21105<Bus>::gyroFSMAP[];
diff --git a/old_examples/shared/sensors/MAX31856.h b/old_examples/shared/sensors/MAX31856.h
deleted file mode 100644
index 6dc77071c4adc9b82c1a1b29c7d8e94e9dcd9d85..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/MAX31856.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* Copyright (c) 2015-2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Sensor.h"
-
-/** This is a thermocouple reading chip */
-
-template <class BusType>
-class MAX31856 : public TemperatureSensor
-{
-public:
- MAX31856() : lastTemperature(0.0f), cjEnabled(true) {}
-
- bool init()
- {
-
- // NOTE: this sensor seems doesn't have a WHOAMI register
-
- uint8_t cr0val = bus.read(REG_CR0); // get CR0 register actual value
-
- cr0val |= 0x01; // select 50Hz noise rejection
-
- bus.write(REG_CR0, cr0val);
-
- return true;
- }
-
- /* The only self test that can be performed is checking if any
- * fault condition has occurred, this is done simply verifyng
- * that fault status register is nonzero
- */
- bool selfTest()
- {
- uint8_t status = bus.read(REG_SR);
-
- return (status == 0);
- }
-
- bool onSimpleUpdate()
- {
- requestConversion();
- lastTemperature = getColdJunctionTemp() + getThermocoupleTemp();
-
- return true;
- }
-
- // ----------- BELOW THERMOCOUPLE TUNING FUNCTIONS. ------------
-
- /**
- * @param mode true to set auto conversion mode, that stands
- * for continuous conversion, one every 100ms
- */
- void setConversionMode(bool mode)
- {
- uint8_t regVal = bus.read(REG_CR0);
-
- if (mode)
- regVal |= 0x80; // conversion mode is the 8-th bit of CR0 register
- else
- regVal &= ~0x80;
-
- bus.write(REG_CR0, regVal);
- }
-
- /**
- * @param mode true to enable internal cold junction temperature
- * sensor, false to disable it
- */
- void enableCjSensor(bool mode)
- {
- uint8_t regVal = bus.read(REG_CR0);
-
- if (mode)
- {
- regVal |= 0x08; // CJ temp. sensor is the 4-th bit of CR0 register
- cjEnabled = true;
- }
- else
- {
- regVal &= ~0x08;
- cjEnabled = false;
- }
-
- bus.write(REG_CR0, regVal);
- }
-
- /**
- * Trigger a one-shot conversion
- */
- void requestConversion()
- {
- uint8_t regVal = bus.read(REG_CR0);
-
- // conversion trigger is the 7-th bit of CR0 register
- bus.write(REG_CR0, regVal | 0x40);
- }
-
- /**
- * Set the number of samples that are averaged in order to
- * achieve one masure
- * @param samplesNum number of samples, that are: 1,2,4,8,16
- */
- void setSamples(uint8_t samplesNum)
- {
- uint8_t regVal = bus.read(REG_CR1);
- regVal &= 0x8F; // clear bits from 7-th to 5-th
-
- switch (samplesNum)
- {
- // 1: do nothing, since single conversion
- // is set writing 000 to the register
- case 1:
- break;
- case 2:
- regVal |= 0b00000001 << 4;
- break;
- case 4:
- regVal |= 00000010 << 4;
- break;
- case 8:
- regVal |= 00000011 << 4;
- break;
- case 16:
- regVal |= 00000100 << 4;
- break;
- default:
- break;
- }
- bus.write(REG_CR1, regVal);
- }
-
- /**
- * Set Thermocouple type
- */
- void setThermoType(uint8_t type)
- {
- uint8_t regVal = bus.read(REG_CR1);
- bus.write(REG_CR1, regVal | type);
- }
-
- /**
- * @return cold junction temperature
- */
- float getColdJunctionTemp()
- {
- int16_t temp = (bus.read(REG_CJTH) << 8) | bus.read(REG_CJTL);
- return static_cast<float>(temp) * 0.015625;
- }
-
- /**
- * Set cold junction temperature, this is possible
- * only if internal cold junction temperature sensor is disabled
- */
- void setColdJunctionTemp(float temp)
- {
- if (!cjEnabled)
- {
- int16_t setTemp = static_cast<int16_t>(temp / 0.015625);
- bus.write(REG_CJTH, (setTemp & 0xFF00) >> 16);
- bus.write(REG_CJTL, setTemp & 0x00FF);
- }
- }
-
- /**
- * @return thermocouple temperature value, 19 bit right-aligned
- */
- float getThermocoupleTemp()
- {
- int32_t temp = (bus.read(REG_LTCBH) << 16) |
- (bus.read(REG_LTCBM) << 8) | bus.read(REG_LTCBL);
- return static_cast<float>(temp) * 0.0078125;
- }
-
-private:
- float lastTemperature;
- BusType bus;
-
- // clang-format off
- enum eRegMap
- {
- REG_CR0 = 0x00,
- REG_CR1 = 0x01,
- REG_MASK = 0x02,
- REG_CJHF = 0x03,
- REG_CJLF = 0x04,
- REG_LTHFTH = 0x05,
- REG_LTHFTL = 0x06,
- REG_LTLFTH = 0x07,
- REG_LTLFTL = 0x08,
- REG_CJTO = 0x09,
- REG_CJTH = 0x0A,
- REG_CJTL = 0x0B,
- REG_LTCBH = 0x0C,
- REG_LTCBM = 0x0D,
- REG_LTCBL = 0x0E,
- REG_SR = 0x0F,
- };
-
- enum eTypes
- {
- TH_B = 0x00,
- TH_E = 0x01,
- TH_J = 0x02,
- TH_K = 0x03,
- TH_N = 0x04,
- TH_R = 0x05,
- TH_S = 0x06,
- TH_T = 0x07,
- };
- // clang-format on
-
- // flag to determine if internal cold junction temp sensor is enabled,
- // by default is enabled
- bool cjEnabled;
-};
diff --git a/old_examples/shared/sensors/MPL3115.h b/old_examples/shared/sensors/MPL3115.h
deleted file mode 100644
index 2ebd88f3bbec3afe874d90c52f220d7eb68037a5..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/MPL3115.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Sensor.h"
-
-template <typename BusType>
-class MPL3115 : public PressureSensor,
- public TemperatureSensor,
- public AltitudeSensor
-{
-
-public:
- MPL3115()
- {
- mLastPressure = 0.0f;
- mLastTemp = 0.0f;
- mLastAltitude = 0.0f;
- }
-
- bool init()
- {
- setMode(MODE_BAROMETER);
-
- // raise and event flag on new pressure/altitude
- // data and on new temperature data
- uint8_t value = 0x03;
- BusType::write(devAddr, PT_DATA_CFG, &value, 1);
-
- return true;
- }
-
- bool selfTest()
- {
- uint8_t value = 0;
- BusType::read(devAddr, WHO_AM_I, &value, 1);
-
- if (value == 0xC4)
- return true;
-
- last_error = ERR_NOT_ME;
- return false;
- }
-
- bool onSimpleUpdate()
- {
- /* To start a new one-shot conversion we have to set OST bit whith
- * SBYB bit cleared; these bit are, respectively, the second and
- * first bits from right in control register 1.
- * After having done this, we poll data register status register
- * checking if PDR and TDR bits are set, meaning that we have new data
- * both for pressure / altitude and for temperature.
- * PDR bit is the second from right, while TDR is the first one
- */
-
- uint8_t temp;
-
- BusType::read(devAddr, CTRL_REG1, &temp, 1);
- temp &= ~0x03; // clear first and second bits
- temp |= 0x02; // set second bit
- BusType::write(devAddr, CTRL_REG1, &temp, 1);
-
- do
- {
- BusType::read(devAddr, CTRL_REG1, &temp, 1);
- miosix::Thread::sleep(6); // minimum sample time is 6 ms
- } while (!(temp & 0x02));
-
- /* This device supports register pointer auto-increment when reading
- * registers from 0x00 to 0x05, so with one read of 6 bytes we get
- * status, pressure and temperature registers values
- */
-
- /* FIXME: this below is NOT A MISTAKE! Due to a strange quirk present
- * in hardware i2c driver when working in non DMA mode, reading the
- * exact number of bytes (5) causes the temperature MSB to be read as
- * zero. Reading 7 or more bytes seems to avoid the problem, so, until
- * the problem is fixed at his roots DON'T MODIFY the index below !!!!
- */
-
- uint8_t data[7];
- BusType::read(devAddr, OUT_P_MSB, data, 7);
-
- if (sensorMode == MODE_BAROMETER)
- {
-
- // See datasheet at page 21 for more informations about
- // calculations below
- uint32_t press = (static_cast<uint32_t>(data[0]) << 16) |
- (static_cast<uint32_t>(data[1]) << 8) |
- static_cast<uint32_t>(data[2]);
- mLastPressure = static_cast<float>(press) / 64;
- }
-
- if (sensorMode == MODE_ALTIMETER)
- {
- uint32_t altitude = (static_cast<uint32_t>(data[0]) << 24) |
- (static_cast<uint32_t>(data[1]) << 16) |
- (static_cast<uint32_t>(data[2]) << 8);
- mLastAltitude = static_cast<float>(altitude) / 65536;
- }
-
- uint16_t temperature = (static_cast<uint16_t>(data[3]) << 8) |
- static_cast<uint16_t>(data[4]);
- mLastTemp = static_cast<float>(temperature) / 256;
-
- return true;
- }
-
- /**
- * Set sensor mode: altimeter or barometer
- * true is returned in case of success, false if
- * the value passed in @param mode was not recognized
- */
- bool setMode(uint8_t mode)
- {
- if (sensorMode == mode)
- return true;
-
- uint8_t temp;
- BusType::read(devAddr, CTRL_REG1, &temp, 1);
-
- if (mode == MODE_ALTIMETER)
- temp |= 0x80;
- else if (mode == MODE_BAROMETER)
- temp &= ~0x80;
- else
- return false;
-
- BusType::write(devAddr, CTRL_REG1, &temp, 1);
- sensorMode = mode;
- return true;
- }
-
- /**
- * Correction factor used to trim temperature output value
- * @param offset offset trim value as 8 bit two's complement number.
- * Range is from -8 to +7.9375°C, 0.0625°C per LSB
- */
- void setTempOffset(int8_t offset)
- {
- BusType::write(devAddr, TEMP_OFFSET, &offset, 1);
- }
-
- /**
- * Correction factor used to trim pressure output value
- * @param offset offset trim value as 8 bit two's complement number.
- * Range is from -512 to +508 Pa, 4 Pa per LSB
- */
- void setPressOffset(int8_t offset)
- {
- BusType::write(devAddr, PRESS_OFFSET, &offset, 1);
- }
-
- /**
- * Correction factor used to trim altitude output value
- * @param offset offset trim value as 8 bit two's complement number.
- * The range of values are from -128 to +127 meters
- */
- void setAltOffset(int8_t offset)
- {
- BusType::write(devAddr, ALTIT_OFFSET, &offset, 1);
- }
-
- /**
- * Set oversampling ratio. Allowed values are: 1,2,4,8,16,32,64,128
- * Higher the oversample ratio, lower the sample rate allowed.
- * For further informations about minimum time between samples and its
- * relation with oversampling ratio see datasheet at page 31
- */
- void setOversampleRatio(uint8_t ratio)
- {
- uint8_t temp, osr = 0;
-
- BusType::read(devAddr, CTRL_REG1, &temp, 1);
- temp &= ~0b00111000; // oversample ratio bits are 4th to 6th
-
- switch (ratio)
- {
- case 1:
- osr = 0x00;
- break;
- case 2:
- osr = 0x01;
- break;
- case 4:
- osr = 0x02;
- break;
- case 8:
- osr = 0x03;
- break;
- case 16:
- osr = 0x04;
- break;
- case 32:
- osr = 0x05;
- break;
- case 64:
- osr = 0x06;
- break;
- case 128:
- osr = 0x07;
- break;
- default:
- break;
- }
-
- temp |= osr << 3;
- BusType::write(devAddr, CTRL_REG1, &temp, 1);
- }
-
- // clang-format off
- enum sensMode
- {
- MODE_BAROMETER = 0x01,
- MODE_ALTIMETER = 0x02
- };
- // clang-format on
-
-private:
- static constexpr uint8_t devAddr = 0xC0;
-
- uint8_t sensorMode;
- float lastTemp;
- float lastPress;
- float lastAlt;
-
- //clang-format off
- enum registers
- {
- STATUS = 0x00,
- OUT_P_MSB = 0x01,
- OUT_P_CSB = 0x02,
- OUT_P_LSB = 0x03,
- OUT_T_MSB = 0x04,
- OUT_T_LSB = 0x05,
- DR_STATUS = 0x06,
- OUT_P_DELTA_MSB = 0x07,
- OUT_P_DELTA_CSB = 0x08,
- OUT_P_DELTA_LSB = 0x09,
- OUT_T_DELTA_MSB = 0x0A,
- OUT_T_DELTA_LSB = 0x0B,
- WHO_AM_I = 0x0C,
- FIFO_STATUS = 0x0D,
- FIFO_DATA = 0x0E,
- FIFO_SETUP = 0x0F,
- TIME_DELAY = 0x10,
- SYSMOD = 0x11,
- INT_SOURCE = 0x12,
- PT_DATA_CFG = 0x13,
- BARO_IN_MSB = 0x14,
- BARO_IN_LSB = 0x15,
- P_TGT_MSB = 0x16,
- P_TGT_LSB = 0x17,
- T_TGT = 0x18,
- P_WND_MSB = 0x19,
- P_WND_LSB = 0x1A,
- T_WND = 0x1B,
- P_MIN_MSB = 0x1C,
- P_MIN_CSB = 0x1D,
- P_MIN_LSB = 0x1E,
- T_MIN_MSB = 0x1F,
- T_MIN_LSB = 0x20,
- P_MAX_MSB = 0x21,
- P_MAX_CSB = 0x22,
- P_MAX_LSB = 0x23,
- T_MAX_MSB = 0x24,
- T_MAX_LSB = 0x25,
- CTRL_REG1 = 0x26,
- CTRL_REG2 = 0x27,
- CTRL_REG3 = 0x28,
- CTRL_REG4 = 0x29,
- CTRL_REG5 = 0x2A,
- PRESS_OFFSET = 0x2B,
- TEMP_OFFSET = 0x2C,
- ALTIT_OFFSET = 0x2D
- };
- //clang-format on
-};
diff --git a/old_examples/shared/sensors/Si7021.h b/old_examples/shared/sensors/Si7021.h
deleted file mode 100644
index 33e74d2dbfbaac25d61f9b641eed3097e52272f2..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/Si7021.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* Copyright (c) 2016 Skyward Experimental Rocketry
- * Author: Silvano Seva
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Sensor.h"
-
-template <typename BusType>
-class Si7021 : public HumiditySensor, public TemperatureSensor
-{
-
-public:
- Si7021()
- {
- mLastHumidity = 0;
- mLastTemp = 0;
- }
-
- bool init() { return true; }
-
- bool selfTest()
- {
-
- // test the whoami value
- uint8_t buf[6];
-
- /* To get the second serial number we have to
- * send CMD_READ_ID1_2 and CMD_READ_ID2_2, so we
- * set the first as register address and the second
- * as payload data and then we send them */
-
- buf[0] = CMD_READ_ID2_2;
-
- BusType::write(slaveAddr, CMD_READ_ID2_1, buf, 1);
- BusType::read(slaveAddr, 0, buf, 6);
-
- // if(buf[0] != 0x15) {
- // last_error = ERR_NOT_ME;
- // return false;
- // }
-
- return true;
- }
-
- bool onSimpleUpdate()
- {
-
- uint8_t buf[2];
- BusType::read(slaveAddr, CMD_MEAS_HUM, buf, 2);
- mLastHumidity =
- ((static_cast<float>((buf[0] << 8) | buf[1]) * 125) / 65536) - 6;
-
- BusType::read(slaveAddr, CMD_MEAS_TEMP_PREV_HUM, buf, 2);
- mLastTemp =
- ((static_cast<float>((buf[0] << 8) | buf[1]) * 175.72) / 65536) -
- 46.85;
-
- return true;
- }
-
- /**
- * \return temperature measurement made along the previous
- * humidity measurement.
- * \code
- * getHumidity(); //reads current humidity
- * getTempRh(); //returns temperature reading made along
- * the humidity reading
- * \endcode
- */
- float getTempRh()
- {
-
- uint8_t buf[2];
- BusType::read(CMD_MEAS_TEMP_PREV_HUM, buf, 2);
-
- uint16_t retVal = (buf[0] << 8) | buf[1];
-
- float temp = (172.72 * retVal) / 65535;
- return temp - 46.85;
- }
-
- void heaterOn()
- {
-
- uint8_t regValue;
- BusType::read(slaveAddr, CMD_READ_USR1, ®Value, 1);
-
- regValue |= 0b00000100;
-
- BusType::write(slaveAddr, CMD_WRITE_USR1, ®Value, 1);
- }
-
- void heaterOff()
- {
-
- uint8_t regValue;
- BusType::read(slaveAddr, CMD_READ_USR1, ®Value, 1);
-
- regValue &= ~0b00000100;
-
- BusType::write(slaveAddr, CMD_WRITE_USR1, ®Value, 1);
- }
-
- /**
- * Set internal heater draw current value, it also can be used to
- * turn on/off the internal heater
- *
- * @param level current draw level, between 0 and 16:
- * 0 -> heater off, 16 -> heater at max power
- */
- void setHeaterLevel(uint8_t level)
- {
-
- if (level == 0)
- heaterOff();
- else if (level <= 16)
- {
- heaterOn();
- uint8_t lvl = level - 1;
-
- BusType::write(slaveAddr, CMD_WRITE_HEAT_CTL, &lvl, 1);
- }
- }
-
-private:
- static constexpr uint8_t slaveAddr = 0x40 << 1;
-
- float temperature;
- float humidity;
-
- // clang-format off
- enum eCommands
- {
- CMD_MEAS_HUM = 0xE5,
- CMD_MEAS_TEMP = 0xE3,
- CMD_MEAS_TEMP_PREV_HUM = 0xE0, // Read temperature value from
- // previous RH measurement
- CMR_RESET = 0xFE,
- CMD_WRITE_USR1 = 0xE6,
- CMD_READ_USR1 = 0xE7,
- CMD_WRITE_HEAT_CTL = 0x51,
- CMD_READ_HEAT_CTL = 0x11,
- CMD_READ_ID1_1 = 0xFA,
- CMD_READ_ID1_2 = 0x0F,
- CMD_READ_ID2_1 = 0xFC,
- CMD_READ_ID2_2 = 0xC9,
- CMD_READ_FW_REV = 0x84,
- };
- // clang-format on
-};
diff --git a/old_examples/shared/sensors/iNemo.h b/old_examples/shared/sensors/iNemo.h
deleted file mode 100644
index d264ca7be2340f696c515d3f5e7cd8c06d8a59d4..0000000000000000000000000000000000000000
--- a/old_examples/shared/sensors/iNemo.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/* Copyright (c) 2016-2017 Skyward Experimental Rocketry
- * Authors: Matteo Piazzolla, Alain Carlucci
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <drivers/BusTemplate.h>
-
-#include "Common.h"
-#include "Sensor.h"
-
-template <typename BusG, typename BusXM>
-class iNEMOLSM9DS0 : public GyroSensor,
- public AccelSensor,
- public CompassSensor,
- public TemperatureSensor
-{
-
-public:
- iNEMOLSM9DS0(uint8_t accelFullScale, uint8_t gyroFullScale,
- uint8_t compassFullScale)
- {
- accelFS = accelFullScale & 0x07;
- gyroFS = gyroFullScale & 0x03;
- compassFS = compassFullScale & 0x03;
- mLastTemp = 0.0f;
- }
-
- bool init()
- {
- uint8_t whoami_g = BusG::read(RegMap::WHO_AM_I_G);
- uint8_t whoami_xm = BusXM::read(RegMap::WHO_AM_I_XM);
-
- if ((whoami_g != whoami_g_value) || (whoami_xm != whoami_xm_value))
- {
- last_error = ERR_NOT_ME;
- return false;
- }
-
- // gyro configuration
- // 95 ODR 25 cutoff normal mode, xyz enabled
- BusG::write(CTRL_REG1_G, 0x0F);
- BusG::write(CTRL_REG2_G, 0x00);
-
- // TODO: CTRL_REG2_G
- // INT_G pin interrupt enable Fifo overrun interrupt
- BusG::write(CTRL_REG3_G, 0x88);
-
- //[5:4] scale
- //(00: 245 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)
- // continuous update, 2000dps
- BusG::write(CTRL_REG4_G, 0x00 | (gyroFS << 4));
-
- // FIFO enabled, get data after the first low pass filter
- BusG::write(CTRL_REG5_G, 0x00);
-
- // accelerometer configuration
- // reset internal memory
- BusXM::write(CTRL_REG0_XM, 0x80);
-
- uint8_t timeout = 10;
-
- while (BusXM::read(CTRL_REG0_XM) != 0x00 && --timeout > 0)
- miosix::Thread::sleep(1);
-
- if (timeout == 0)
- {
- last_error = ERR_RESET_TIMEOUT;
- return false;
- }
-
- // 100Hz data rate, continuous update, xyz enabled
- BusXM::write(CTRL_REG1_XM, 0x67);
- // antialias filter 773 Hz, normal mode no test
- BusXM::write(CTRL_REG2_XM, (0x01 << 6) | (accelFS << 3));
-
- // interrupt not enabled
- BusXM::write(CTRL_REG3_XM, 0x00);
- BusXM::write(CTRL_REG4_XM, 0x00);
-
- // temperature sensor enabled, 50hz magnetic data rate, 2 gauss
- BusXM::write(CTRL_REG5_XM, 0xF0);
-
- // 2 gauss
- BusXM::write(CTRL_REG6_XM, 0x00 | (compassFS << 5));
- BusXM::write(CTRL_REG7_XM, 0x80);
-
- return true;
- }
-
- bool selfTest() { return false; }
-
- std::vector<SPIRequest> buildDMARequest() override
- {
- return {
- SPIRequest(DMA_GYRO, BusG::getCSPin(),
- {OUT_X_L_G | 0xc0, 0, 0, 0, 0, 0, 0}),
- SPIRequest(DMA_ACC, BusXM::getCSPin(),
- {OUT_X_L_A | 0xc0, 0, 0, 0, 0, 0, 0}),
- SPIRequest(DMA_COMP, BusXM::getCSPin(),
- {OUT_X_L_M | 0xc0, 0, 0, 0, 0, 0, 0}),
- SPIRequest(DMA_TEMP, BusXM::getCSPin(),
- {OUT_TEMP_L_XM | 0xc0, 0, 0}),
- };
- }
-
- void onDMAUpdate(const SPIRequest& req) override
- {
- const auto& r = req.readResponseFromPeripheral();
-
- int16_t data[3] = {0};
- memcpy(data, &r[1], r.size() - 1);
-
- switch (req.id())
- {
- case DMA_GYRO:
- mLastGyro.setX(normalizeGyro(data[0]));
- mLastGyro.setY(normalizeGyro(data[1]));
- mLastGyro.setZ(normalizeGyro(data[2]));
- break;
- case DMA_ACC:
- mLastAccel.setX(normalizeAccel(data[0]));
- mLastAccel.setY(normalizeAccel(data[1]));
- mLastAccel.setZ(normalizeAccel(data[2]));
- break;
- case DMA_COMP:
- mLastCompass.setX(normalizeCompass(data[0]));
- mLastCompass.setY(normalizeCompass(data[1]));
- mLastCompass.setZ(normalizeCompass(data[2]));
- break;
- case DMA_TEMP:
- mLastTemp = static_cast<float>(data[0]) / 8.0f + 21.0f;
- break;
- }
- }
-
- bool onSimpleUpdate() { return false; }
-
- // clang-format off
- enum DMAType
- {
- DMA_GYRO = 0,
- DMA_ACC = 1,
- DMA_COMP = 2,
- DMA_TEMP = 3
- };
-
- enum accelFullScale
- {
- ACC_FS_16G = 4,
- ACC_FS_8G = 3,
- ACC_FS_6G = 2,
- ACC_FS_4G = 1,
- ACC_FS_2G = 0,
- };
-
- enum gyroFullScale
- {
- GYRO_FS_245 = 0,
- GYRO_FS_500 = 1,
- GYRO_FS_2000 = 2,
- };
-
- enum compassFullScale
- {
- COMPASS_FS_12 = 0,
- COMPASS_FS_8 = 1,
- COMPASS_FS_4 = 2,
- COMPASS_FS_2 = 3,
- };
- // clang-format on
-
-private:
- uint8_t accelFS, gyroFS, compassFS;
-
- constexpr static uint8_t whoami_g_value = 0xD4;
- constexpr static uint8_t whoami_xm_value = 0x49;
-
- static constexpr const float accelFSMAP[] = {2.0, 4.0, 6.0, 8.0, 16.0};
- static constexpr const float compassFSMAP[] = {12.0, 8.0, 4.0, 2.0};
- static constexpr const float gyroFSMAP[] = {245, 500, 2000};
-
- inline constexpr float normalizeAccel(int16_t val)
- {
- return static_cast<float>(val) * (accelFSMAP[accelFS] / 32768.0f) *
- EARTH_GRAVITY;
- }
-
- inline constexpr float normalizeGyro(int16_t val)
- {
- return static_cast<float>(val) * (gyroFSMAP[gyroFS] / 32768.0f) *
- DEGREES_TO_RADIANS;
- }
-
- inline constexpr float normalizeCompass(int16_t val)
- {
- return static_cast<float>(val) * (compassFSMAP[compassFS] / 32768.0f);
- }
-
- inline constexpr float normalizeTemp(int16_t val)
- {
- return static_cast<float>(val) / 256.0f;
- }
-
- // clang-format off
- enum RegMap
- {
- WHO_AM_I_G = 0x0F, // default value 0xD4,
- CTRL_REG1_G = 0x20,
- CTRL_REG2_G = 0x21,
- CTRL_REG3_G = 0x22,
- CTRL_REG4_G = 0x23,
- CTRL_REG5_G = 0x24,
- STATUS_REG_G = 0x27,
-
- // magnetic data registers
- OUT_X_L_M = 0x08,
- OUT_X_H_M = 0x09,
- OUT_Y_L_M = 0x0A,
- OUT_Y_H_M = 0x0B,
- OUT_Z_L_M = 0x0C,
- OUT_Z_H_M = 0x0D,
-
- WHO_AM_I_XM = 0x0F, // default value = 0x49
-
- OUT_TEMP_L_XM = 0x05,
- OUT_TEMP_H_XM = 0x06,
-
- // gyro data registers
- OUT_X_L_G = 0x28,
- OUT_X_H_G = 0x29,
- OUT_Y_L_G = 0x2A,
- OUT_Y_H_G = 0x2B,
- OUT_Z_L_G = 0x2C,
- OUT_Z_H_G = 0x2D,
-
- // accelerometer control registers
- CTRL_REG0_XM = 0x1F,
- CTRL_REG1_XM = 0x20,
- CTRL_REG2_XM = 0x21,
- CTRL_REG3_XM = 0x22,
- CTRL_REG4_XM = 0x23,
- CTRL_REG5_XM = 0x24,
- CTRL_REG6_XM = 0x25,
- CTRL_REG7_XM = 0x26,
-
- // accelerometer data registers
- OUT_X_L_A = 0x28,
- OUT_X_H_A = 0x29,
- OUT_Y_L_A = 0x2A,
- OUT_Y_H_A = 0x2B,
- OUT_Z_L_A = 0x2C,
- OUT_Z_H_A = 0x2D
- };
- // clang-format on
-};
-
-template <typename BusG, typename BusXM>
-constexpr float iNEMOLSM9DS0<BusG, BusXM>::accelFSMAP[];
-
-template <typename BusG, typename BusXM>
-constexpr float iNEMOLSM9DS0<BusG, BusXM>::gyroFSMAP[];
-
-template <typename BusG, typename BusXM>
-constexpr float iNEMOLSM9DS0<BusG, BusXM>::compassFSMAP[];
diff --git a/old_examples/tests/catch/example-test-fsm.cpp b/old_examples/tests/catch/example-test-fsm.cpp
deleted file mode 100644
index 9c69e2b3000ca19754a076f3c52b379bb12e66b1..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/example-test-fsm.cpp
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-// Define STANDALONE_CATCH1_TEST in sbs.conf if you want to run this test alone
-// Otherwise, include this file in the sources and compile the
-// catch1-tests-entry.cpp entrypoint. This test will be run automatically
-// togheter with all the others. Learn more on the skyward-boardcore wiki at:
-// https://git.skywarder.eu/r2a/skyward-boardcore/wikis/Testing
-#ifdef STANDALONE_CATCH1_TEST
-#include "catch-tests-entry.cpp"
-#endif
-
-// We need access to the handleEvent(...) function in state machines in order to
-// test them synchronously
-#define protected public
-
-#include <miosix.h>
-#include <utils/TestUtils/TestHelper.h>
-
-#include <catch2/catch.hpp>
-
-#include "example-test-fsm.h"
-
-using miosix::Thread;
-
-TEST_CASE("Testing S1 transitions")
-{
- FSMExample fsm;
-
- SECTION("S1 -> EV_A -> S2")
- {
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S2));
- }
-
- SECTION("S1 -> EV_A -> S4 if we go to S3 before")
- {
- // Go to S3 and then back to S1
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S2));
- REQUIRE(testFSMTransition(fsm, Event{EV_C}, &FSMExample::state_S3));
- REQUIRE(testFSMTransition(fsm, Event{EV_D}, &FSMExample::state_S1));
-
- // Test if EV_A now puts us in S4
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S4));
- }
-}
-
-TEST_CASE("Testing S2 Transitions")
-{
- // These lines are repeated every time we enter a "SECTION". This means that
- // the state machine will be in state S2 at the beginning of every section.
- FSMExample fsm;
- // Move to S2 before testing
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S2));
-
- // Test S2 to S3
- SECTION("S2 -> EV_C -> S3")
- {
- REQUIRE(testFSMTransition(fsm, Event{EV_C}, &FSMExample::state_S3));
- }
-}
-
-TEST_CASE("Testing S3 transitions")
-{
- // First move to S3
- FSMExample fsm;
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S2));
- REQUIRE(testFSMTransition(fsm, Event{EV_C}, &FSMExample::state_S3));
-
- // Then test S3 transitions
-
- SECTION("S3 -> EV_D -> S1")
- {
- REQUIRE(testFSMTransition(fsm, Event{EV_D}, &FSMExample::state_S1));
- }
-
- SECTION("S3 -> EV_A -> S3")
- {
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S3));
- }
-}
-
-TEST_CASE("Testing S4 transitions")
-{
- // First move to S4
- FSMExample fsm;
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S2));
- REQUIRE(testFSMTransition(fsm, Event{EV_C}, &FSMExample::state_S3));
- REQUIRE(testFSMTransition(fsm, Event{EV_D}, &FSMExample::state_S1));
- REQUIRE(testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S4));
-
- // Then test S4 transitions
-
- SECTION("S4 -> EV_D -> S3")
- {
- REQUIRE(testFSMTransition(fsm, Event{EV_D}, &FSMExample::state_S3));
- }
-
- SECTION("S4 -> EV_A -> S1 (Should not happen)")
- {
- REQUIRE_FALSE(
- testFSMTransition(fsm, Event{EV_A}, &FSMExample::state_S1));
- }
-}
-
-/**
- * @brief Test fixture to perform creation / termination of the FSMExample
- * thread, RAII style
- */
-class FSMTestFixture
-{
-public:
- // Start the thread in the constructor
- FSMTestFixture()
- {
- EventBroker::getInstance().start();
- fsm.start();
- }
- // Stop the thread in the destructor
- ~FSMTestFixture() { fsm.stop(); }
-
-protected:
- FSMExample fsm;
-};
-
-// Incredibly, this method is part of a class derived from the "FSMTestFixture"
-// class. So it can access all its protected members. For each section in this
-// method, the class is created and destroyed, so all sections start exactly at
-// the same state.
-TEST_CASE_METHOD(FSMTestFixture, "Testing async transitions")
-{
- REQUIRE(testFSMAsyncTransition(fsm, Event{EV_A}, TOPIC_T1,
- &FSMExample::state_S2));
-
- REQUIRE(testFSMAsyncTransition(fsm, Event{EV_C}, TOPIC_T1,
- &FSMExample::state_S3));
- SECTION("Automatic transition")
- {
- SECTION("S3 --> S1 after 1 seconds")
- {
- // Should automatically move to S1 after 1 second.
- Thread::sleep(995);
- // Transition should not have occured yet
- REQUIRE(fsm.testState(&FSMExample::state_S3));
-
- Thread::sleep(10);
- // Now it should
- REQUIRE(fsm.testState(&FSMExample::state_S1));
- }
-
- SECTION("S3 --> S4 if EV_B. Delayed event should be removed")
- {
- EventCounter counter{*EventBroker::getInstance()};
-
- // Post EV_B before EV_D fires. should move to S4 and remove EV_D
- // from the delayed events
- REQUIRE(testFSMAsyncTransition(fsm, Event{EV_B}, TOPIC_T1,
- &FSMExample::state_S4));
-
- // Subscribe the counter to TOPIC_1 to see if EV_D still fires
- counter.subscribe(TOPIC_T1);
-
- // Wait for EV_D to fire
- Thread::sleep(1005);
-
- // Should not have received EV_D, since S3 should have removed the
- // delayed event on exit. Spoiler: S3 didn't remove it, and the
- // check will fail (CHECK works just like REQUIRE, but it will not
- // stop the execution of the test in case it fails)
- CHECK(counter.getCount(EV_D) == 0);
-
- // Since S3 did not remove the delyaed event on exit, the event is
- // fired when we are in S4, causing an unexpected transition back to
- // S3, failing this test
- REQUIRE(fsm.testState(&FSMExample::state_S4));
- }
- }
-}
diff --git a/old_examples/tests/catch/example-test-fsm.h b/old_examples/tests/catch/example-test-fsm.h
deleted file mode 100644
index 03f46222db911c7304992b33a1ee525771567b5e..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/example-test-fsm.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-/**
- * Basic State Machine example. Explaination of this example and a graphical
- * representation of the state machine can be found on the Skyward Boardcore
- * Wiki on Gitlab:
- * https://git.skywarder.eu/r2a/skyward-boardcore/blob/master/src/entrypoints/examples/state-machines-examples.md
- *
- * https://git.skywarder.eu/r2a/skyward-boardcore/wikis/State-Machines-Examples-and-Best-Practices
- */
-
-#pragma once
-
-#include <events/EventBroker.h>
-#include <events/FSM.h>
-
-/*
- * Enum containing custom events definitions
- */
-enum ExampleEvents : uint8_t
-{
- EV_A = EV_FIRST_CUSTOM, // The first event must always have value
- // EV_FIRST_CUSTOM
- EV_B, // Values for the following event can be manually specified or
- // assigned automatically
- EV_C,
- EV_D,
- EV_E
-};
-
-enum ExampleTopics : uint8_t
-{
- TOPIC_T1
-};
-
-/**
- * @brief Logs every event received by the state machine
- * This function can be expanded to log every event / transition of the state
- * machine for later analysis, and as an aid for testing the state machine.
- *
- * @param state Current state of the state machine
- * @param ev The event being handled
- */
-void traceState(uint8_t state, const Event& ev)
-{
- // Do not output anything for this test
- /* switch (ev.sig)
- {
- case EV_ENTRY:
- {
- printf("(S%d) Entering state\n", state);
- break;
- }
- case EV_EXIT:
- {
- printf("(S%d) Exiting state\n", state);
- break;
- }
- default:
- {
- printf("(S%d) Received event %d\n", state, ev.sig);
- break;
- }
- }*/
-}
-
-/*
- * Simple State machine definition
- *
- * The class inherits publicly from the FSM class, and must pass itself as a
- * template argument to the parent class.
- */
-class FSMExample : public FSM<FSMExample>
-{
-public:
- enum States : uint8_t
- {
- STATE_S1 = 1,
- STATE_S2,
- STATE_S3,
- STATE_S4
- };
-
- /*
- * FSMExample constructor. The initial state of the state machine is passed
- * to the FSM superclass via the member initializer list.
- *
- * Initial conditions are also applied here. In this example, v is set to 0
- */
- FSMExample() : FSM(&FSMExample::state_S1), v(0)
- {
- // Subscribe for events posted on TOPIC_T1
- EventBroker::getInstance().subscribe(this, TOPIC_T1);
- }
-
- ~FSMExample() { EventBroker::getInstance().unsubscribe(this); }
-
- /*
- * State function definitions.
- * EV_ENTRY and EV_EXIT are automatically dispatched by the state machine
- * when a transition occurs, and must be always handled even in the case of
- * no-op
- */
-
- void state_S1(const Event& ev)
- {
- // Print every event we receive in order to see the behaviour of the
- // state machine on the terminal.
- traceState(STATE_S1, ev);
-
- switch (ev.sig)
- {
- // It's always good to add braces to every single case statement, to
- // avoid problems
- case EV_ENTRY:
- {
- // no-op
- break;
- }
- case EV_EXIT:
- {
- // no-op
- break;
- }
- case EV_A:
- {
- if (v == 0)
- {
- // perform a state transition to S2 when receiving EV_A and
- // v == 0
- transition(&FSMExample::state_S2);
- }
- else
- {
- // else, transition to S4
- transition(&FSMExample::state_S4);
- }
- break;
- }
- default:
- {
- break;
- }
- }
- }
-
- void state_S2(const Event& ev)
- {
- traceState(STATE_S2, ev);
-
- switch (ev.sig)
- {
- case EV_ENTRY:
- {
- break;
- }
- case EV_EXIT:
- {
- break;
- }
- case EV_C: // perform a state transition to S3 when receiving EV_C
- {
- transition(&FSMExample::state_S3);
- break;
- }
- case EV_E: // print hello world when receiving EV_E
- {
- printf("Hello world!\n");
- break;
- }
- default:
- {
- break;
- }
- }
- }
-
- void state_S3(const Event& ev)
- {
- traceState(STATE_S3, ev);
-
- switch (ev.sig)
- {
- case EV_ENTRY:
- {
- // Set v = 1
- v = 1;
-
- // Post EV_D to itself in 1 seconds
- delayed_ev_id = EventBroker::getInstance().postDelayed(
- Event{EV_D}, TOPIC_T1, 1000);
-
- break;
- }
- case EV_EXIT:
- {
- // Remove the delayed event in case it has not fired yet
- // !!! This line is commented to show what can happen if we
- // don't remove a delayed event. This is an error! Uncomment to
- // fix, see the wiki for further information !!!
-
- // EventBroker::getInstance().removeDelayed(delayed_ev_id);
- break;
- }
- case EV_B:
- {
- transition(&FSMExample::state_S4);
- break;
- }
- case EV_D: // We will receive this event 1 second after entering
- // this state.
- {
- transition(&FSMExample::state_S1);
- break;
- }
- default:
- {
- break;
- }
- }
- }
-
- // Final state: No outbound transitions, so the state machine cannot exit
- // this state
- void state_S4(const Event& ev)
- {
- traceState(STATE_S4, ev);
-
- switch (ev.sig)
- {
- case EV_ENTRY:
- {
- break;
- }
- case EV_EXIT:
- {
- break;
- }
- case EV_D:
- {
- transition(&FSMExample::state_S3);
- break;
- }
- default:
- {
- break;
- }
- }
- }
-
-public:
- uint16_t delayed_ev_id;
- int v;
-};
diff --git a/old_examples/tests/catch/misc/xbee-bitrate.cpp b/old_examples/tests/catch/misc/xbee-bitrate.cpp
deleted file mode 100644
index 47f40a10fce5ea70e4060026333041251e2c4db4..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/misc/xbee-bitrate.cpp
+++ /dev/null
@@ -1,168 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/spi/SPIDriver.h>
-#include <interfaces-impl/hwmapping.h>
-#include <miosix.h>
-#include <radio/Xbee/Xbee.h>
-#include <utils/Stats/Stats.h>
-
-#include <cstdio>
-#include <iostream>
-#include <string>
-
-using std::cin;
-using std::cout;
-using std::string;
-
-static constexpr int MAX_PKT_SIZE = 255;
-static constexpr int PKT_NUM = 100;
-
-using namespace miosix;
-using namespace interfaces;
-
-// WARNING: If flashing on stm32f49 discovery board (with screen removed) use
-// SPI1 as the 2nd isnt working.
-
-// Discovery
-SPIBus bus{SPI1};
-GpioPin cs = sensors::lsm6ds3h::cs::getPin();
-GpioPin attn = xbee::attn::getPin();
-GpioPin rst = xbee::reset::getPin();
-
-// Death stack
-// SPIBus bus{SPI2};
-// GpioPin cs = xbee::cs::getPin();
-// GpioPin attn = xbee::attn::getPin();
-// GpioPin rst = xbee::reset::getPin();
-
-Xbee::Xbee* xbee_transceiver;
-
-void __attribute__((used)) EXTI10_IRQHandlerImpl()
-{
- Xbee::handleATTNInterrupt();
-}
-
-void enableXbeeInterrupt()
-{
- {
- FastInterruptDisableLock l;
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
- }
- // Refer to the datasheet for a detailed description on the procedure and
- // interrupt registers
-
- // Clear the mask on the wanted line
- EXTI->IMR |= EXTI_IMR_MR10;
-
- // Trigger the interrupt on a falling edge
- EXTI->FTSR |= EXTI_FTSR_TR10;
-
- // Trigger the interrupt on a rising edge
- // EXTI->RTSR |= EXTI_RTSR_TR0;
-
- EXTI->PR |= EXTI_PR_PR10; // Reset pending register
-
- // Enable interrupt on PF10 in SYSCFG
- SYSCFG->EXTICR[2] = 0x5U << 8;
-
- // Enable the interrput in the interrupt controller
- NVIC_EnableIRQ(EXTI15_10_IRQn);
- NVIC_SetPriority(EXTI15_10_IRQn, 15);
-}
-
-uint8_t snd_buf[MAX_PKT_SIZE];
-int snd_cntr = 0;
-
-bool sendPacket(uint8_t size)
-{
- snd_buf[0] = '{';
- snd_buf[size - 1] = '}';
-
- for (int i = 0; i < size - 2; i++)
- {
- snd_buf[i + 1] = ((snd_cntr + i) % 75) + 48; // ASCII char from 0 to z
- }
- ++snd_cntr;
-
- if (!xbee_transceiver->send(snd_buf, size))
- {
- return false;
- }
- return true;
-}
-
-void resetXBee()
-{
- xbee::reset::low();
- delayUs(500);
- xbee::reset::high();
-}
-
-int main()
-{
- enableXbeeInterrupt();
- xbee_transceiver = new Xbee::Xbee(bus, cs, attn, rst);
-
- xbee_transceiver->start();
- resetXBee();
-
- printf("XBee bitrate measurement\n");
- printf(
- "Send 100 packets of a certain size (from 16 to 256, step 16) and "
- "reporting send time.\n");
- printf("Press enter to start\n");
- string s;
- std::getline(cin, s);
-
- int pkt_size = 16;
- while (pkt_size <= MAX_PKT_SIZE)
- {
- printf("Testing %d byte packets:\n", pkt_size);
- long long results[PKT_NUM];
-
- for (int i = 0; i < PKT_NUM; i++)
- {
- long long start = getTick();
- if (!sendPacket(pkt_size))
- {
- printf("Error sending packet %d (size: %d)\n", i, pkt_size);
- goto end;
- }
- results[i] = getTick() - start;
- }
- printf("Results for %d byte packet size:\n", pkt_size);
- for (int i = 0; i < PKT_NUM; i++)
- {
- printf("%d\n", (int)results[i]);
- }
- pkt_size += 16;
- if (pkt_size == 256)
- pkt_size = 255; // Max we can send is 255
- }
-
-end:
- printf("End\n");
- for (;;)
- Thread::sleep(1000);
- return 0;
-}
diff --git a/old_examples/tests/catch/misc/xbee-send-rcv.cpp b/old_examples/tests/catch/misc/xbee-send-rcv.cpp
deleted file mode 100644
index 87c8c8335961362424518bfb8cdf842bca50d559..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/misc/xbee-send-rcv.cpp
+++ /dev/null
@@ -1,184 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/spi/SPIDriver.h>
-#include <interfaces-impl/hwmapping.h>
-#include <miosix.h>
-#include <radio/Xbee/Xbee.h>
-#include <utils/Stats/Stats.h>
-
-#include <cstdio>
-#include <iostream>
-#include <string>
-
-using std::cin;
-using std::cout;
-using std::string;
-
-static const unsigned int PKT_SIZE = 128;
-
-using namespace miosix;
-using namespace interfaces;
-
-// WARNING: If flashing on stm32f49 discovery board (with screen removed) use
-// SPI1 as the 2nd isnt working.
-
-// Discovery
-SPIBus bus{SPI1};
-GpioPin cs = sensors::lsm6ds3h::cs::getPin();
-GpioPin attn = xbee::attn::getPin();
-GpioPin rst = xbee::reset::getPin();
-
-// Death stack
-// SPIBus bus{SPI2};
-// GpioPin cs = xbee::cs::getPin();
-// GpioPin attn = xbee::attn::getPin();
-// GpioPin rst = xbee::reset::getPin();
-
-Xbee::Xbee* xbee_transceiver;
-
-void __attribute__((used)) EXTI10_IRQHandlerImpl()
-{
- Xbee::handleATTNInterrupt();
-}
-
-void enableXbeeInterrupt()
-{
- {
- FastInterruptDisableLock l;
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
- }
- // Refer to the datasheet for a detailed description on the procedure and
- // interrupt registers
-
- // Clear the mask on the wanted line
- EXTI->IMR |= EXTI_IMR_MR10;
-
- // Trigger the interrupt on a falling edge
- EXTI->FTSR |= EXTI_FTSR_TR10;
-
- // Trigger the interrupt on a rising edge
- // EXTI->RTSR |= EXTI_RTSR_TR0;
-
- EXTI->PR |= EXTI_PR_PR10; // Reset pending register
-
- // Enable interrupt on PF10 in SYSCFG
- SYSCFG->EXTICR[2] = 0x5U << 8;
-
- // Enable the interrput in the interrupt controller
- NVIC_EnableIRQ(EXTI15_10_IRQn);
- NVIC_SetPriority(EXTI15_10_IRQn, 15);
-}
-
-void send()
-{
- uint8_t buf[PKT_SIZE];
- buf[0] = '/';
- buf[PKT_SIZE - 1] = '\\';
-
- int fail = 0;
- char c = 48;
- for (;;)
- {
- memset(buf + 1, c++, PKT_SIZE - 2);
- if (c > 122)
- {
- c = 48;
- }
-
- if (!xbee_transceiver->send(buf, PKT_SIZE))
- {
- printf("[%d] Send error %d\n", (int)getTick(), ++fail);
- }
- else
- {
- if (c % 5 == 0)
- {
- printf("Send ok.\n");
- }
- }
-
- Thread::sleep(1000);
- }
-}
-
-void receive(void*)
-{
- uint8_t buf[512];
- for (;;)
- {
- ssize_t len = xbee_transceiver->receive(buf, 512);
- if (len <= 0)
- {
- printf("Receive failed.\n");
- }
- else
- {
- for (ssize_t i = 0; i < len; i++)
- {
- // Only print displayable ascii chars
- if (buf[i] >= 32 && buf[i] <= 126)
- {
- printf("%c", buf[i]);
- }
- }
- printf("\n");
- for (ssize_t i = 0; i < len; i++)
- {
- printf("%02X ", buf[0]);
- }
- printf("\n\n");
- }
- }
-}
-
-void resetx()
-{
- xbee::reset::mode(Mode::OPEN_DRAIN);
- xbee::reset::low();
- delayUs(500);
- xbee::reset::high();
- // xbee::reset::mode(Mode::INPUT);
-}
-
-int main()
-{
- enableXbeeInterrupt();
- resetx();
-
- // xbee::sleep_req::mode(Mode::OUTPUT);
- // xbee::sleep_req::low();
-
- // reset();
-
- xbee_transceiver = new Xbee::Xbee(bus, cs, attn, rst);
-
- xbee_transceiver->start();
-
- // Send & receive
- Thread::create(receive, 2048);
- // for(;;)
- // Thread::sleep(1000);
- send();
-
- return 0;
-}
diff --git a/old_examples/tests/catch/misc/xbee-time-to-send.cpp b/old_examples/tests/catch/misc/xbee-time-to-send.cpp
deleted file mode 100644
index eb08047f3087a7fe5b9aa00aaaecaaf006836e79..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/misc/xbee-time-to-send.cpp
+++ /dev/null
@@ -1,177 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/BusTemplate.h>
-#include <interfaces-impl/hwmapping.h>
-#include <miosix.h>
-#include <radio/Xbee/Xbee.h>
-#include <utils/Stats/Stats.h>
-
-#include <cstdio>
-#include <iostream>
-#include <string>
-
-using std::cin;
-using std::cout;
-using std::string;
-
-static constexpr int PKT_SIZE = 108;
-static constexpr int WITH_LR_PKT_SIZE = PKT_SIZE + 45;
-static constexpr int PKTS_PER_SECOND = 4;
-
-using namespace miosix;
-using namespace interfaces;
-
-// WARNING: If flashing on stm32f49 discovery board (with screen removed) use
-// SPI1 as the 2nd isnt working.
-
-// Discovery
-SPIBus bus{SPI1};
-GpioPin cs = sensors::lsm6ds3h::cs::getPin();
-GpioPin attn = xbee::attn::getPin();
-GpioPin rst = xbee::reset::getPin();
-
-// Death stack
-// SPIBus bus{SPI2};
-// GpioPin cs = xbee::cs::getPin();
-// GpioPin attn = xbee::attn::getPin();
-// GpioPin rst = xbee::reset::getPin();
-
-Xbee::Xbee* xbee_transceiver;
-
-void __attribute__((used)) EXTI10_IRQHandlerImpl()
-{
- Xbee::handleATTNInterrupt();
-}
-
-void enableXbeeInterrupt()
-{
- {
- FastInterruptDisableLock l;
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
- }
- // Refer to the datasheet for a detailed description on the procedure and
- // interrupt registers
-
- // Clear the mask on the wanted line
- EXTI->IMR |= EXTI_IMR_MR10;
-
- // Trigger the interrupt on a falling edge
- EXTI->FTSR |= EXTI_FTSR_TR10;
-
- // Trigger the interrupt on a rising edge
- // EXTI->RTSR |= EXTI_RTSR_TR0;
-
- EXTI->PR |= EXTI_PR_PR10; // Reset pending register
-
- // Enable interrupt on PF10 in SYSCFG
- SYSCFG->EXTICR[2] = 0x5U << 8;
-
- // Enable the interrput in the interrupt controller
- NVIC_EnableIRQ(EXTI15_10_IRQn);
- NVIC_SetPriority(EXTI15_10_IRQn, 15);
-}
-
-uint8_t snd_buf[255];
-int snd_cntr = 0;
-
-bool sendPacket(uint8_t size)
-{
- snd_buf[0] = '{';
- snd_buf[size - 1] = '}';
-
- for (int i = 0; i < size - 2; i++)
- {
- snd_buf[i + 1] = ((snd_cntr + i) % 75) + 48; // ASCII char from 0 to z
- }
- ++snd_cntr;
-
- if (!xbee_transceiver->send(snd_buf, size))
- {
- return false;
- }
- return true;
-}
-
-int main()
-{
- enableXbeeInterrupt();
-
- xbee_transceiver = new Xbee::Xbee(bus, cs, attn, rst);
-
- xbee_transceiver->start();
-
- printf("XBee time-to-send-measurement\n");
- printf(
- "Send N packets per second with the specified size. See if it is "
- "possible to send them in a timely manner. (must not take more than 1 "
- "sec to send)\n");
- printf("Press enter to start\n");
- string s;
- std::getline(cin, s);
-
- for (;;)
- {
- long long cycle_start = getTick();
- long long cycle_silence = 0;
-
- for (int i = 0; i < PKTS_PER_SECOND; i++)
- {
- printf("T: %d\n", (int)(getTick() - cycle_start));
- if (i == PKTS_PER_SECOND - 1)
- {
- // One every PKTS_PER_SECOND packets is bigger (for example if
- // LR_TM is added to the packet)
- if (!sendPacket(WITH_LR_PKT_SIZE))
- {
- printf("Error sending packet(size: %d)\n", PKT_SIZE);
- goto end;
- }
- }
- else
- {
- if (!sendPacket(PKT_SIZE))
- {
- printf("Error sending packet(size: %d)\n", PKT_SIZE);
- goto end;
- }
- }
-
- long long silence_start = getTick();
- Thread::sleepUntil(cycle_start +
- (i + 1) * (1000 / PKTS_PER_SECOND));
- cycle_silence += (getTick() - silence_start);
- }
-
- long long cycle_time = getTick() - cycle_start;
-
- printf("Cycle time: %d, Silence: %d, Duty: %.2f\n", (int)cycle_time,
- (int)cycle_silence,
- (1.0f - (cycle_silence * 1.0f / cycle_time)) * 100);
- }
-
-end:
- printf("End\n");
- for (;;)
- Thread::sleep(1000);
- return 0;
-}
diff --git a/old_examples/tests/catch/spidriver/test-spidriver.cpp b/old_examples/tests/catch/spidriver/test-spidriver.cpp
deleted file mode 100644
index 35041ec450fb6e12b998d74d1bf00067df3c357e..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/spidriver/test-spidriver.cpp
+++ /dev/null
@@ -1,548 +0,0 @@
-/* Copyright (c) 2020 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifdef STANDALONE_CATCH1_TEST
-#include "../catch-tests-entry.cpp"
-#endif
-
-#ifndef USE_MOCK_PERIPHERALS
-#error \
- "This test requires SpiBusInterface built with MockGpioPin (-DUSE_MOCK_PERIPHERALS)"
-#endif
-
-#include <drivers/spi/SPIBus.h>
-#include <drivers/spi/SPIDriver.h>
-#include <drivers/spi/test/FakeSpiTypedef.h>
-#include <drivers/spi/test/MockSPIBus.h>
-
-#include <catch2/catch.hpp>
-
-template <typename T1, typename T2>
-bool bufcmp(T1* buf1, T2* buf2, size_t size)
-{
- for (size_t i = 0; i < size; i++)
- {
- if (*buf1 != *buf2)
- return false;
-
- buf1++;
- buf2++;
- }
- return true;
-}
-
-TEST_CASE("SPIBus - Bus Configuration")
-{
- FakeSpiTypedef spi;
-
- SPIBus bus{&spi};
-
- REQUIRE(spi.CR1 == 0);
-
- SECTION("Configure & check CR1")
- {
- SPIBusConfig config;
- REQUIRE(spi.CR1 == 0);
-
- SECTION("Mode")
- {
- config.mode = SPI::Mode::MODE_0;
- uint32_t expected_CR1 = 0x0344;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.mode = SPI::Mode::MODE_1;
- expected_CR1 = 0x0345;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.mode = SPI::Mode::MODE_2;
- expected_CR1 = 0x0346;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.mode = SPI::Mode::MODE_3;
- expected_CR1 = 0x0347;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
- }
-
- SECTION("Clock Divider")
- {
- config.clockDivider = SPI::ClockDivider::DIV_2;
- uint32_t expected_CR1 = 0x0344;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_4;
- expected_CR1 = 0x034C;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_8;
- expected_CR1 = 0x0354;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_16;
- expected_CR1 = 0x035C;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_32;
- expected_CR1 = 0x0364;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_64;
- expected_CR1 = 0x036C;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_128;
- expected_CR1 = 0x0374;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.clockDivider = SPI::ClockDivider::DIV_256;
- expected_CR1 = 0x037C;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
- }
-
- SECTION("Bit order")
- {
- config.bit_order = SPIBitOrder::MSB_FIRST;
- uint32_t expected_CR1 = 0x0344;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
-
- config.bit_order = SPIBitOrder::LSB_FIRST;
- expected_CR1 = 0x03C4;
- bus.acquire(config);
- REQUIRE(spi.CR1 == expected_CR1);
- bus.release();
- }
- }
-
- SECTION("Disable configuration")
- {
- SPIBusConfig config;
- config.clockDivider = SPI::ClockDivider::DIV_16;
-
- config.mode = SPI::Mode::MODE_3;
- config.bit_order = SPIBitOrder::LSB_FIRST;
-
- bus.disableBusConfiguration();
- bus.acquire(config);
- REQUIRE(spi.CR1 == 0);
- bus.release();
- }
-}
-
-TEST_CASE("SPIBus - Chip select")
-{
- FakeSpiTypedef spi;
-
- SPIBus bus{&spi};
-
- REQUIRE(spi.cs.value() == 1);
-
- bus.select(spi.cs);
- REQUIRE(spi.cs.value() == 0);
-
- bus.deselect(spi.cs);
- REQUIRE(spi.cs.value() == 1);
-}
-
-TEST_CASE("SPIBus - One byte operations")
-{
- FakeSpiTypedef spi;
-
- spi.DR.in_buf = {1, 2, 3, 4, 5, 6, 7, 8, 9};
- spi.CR1_expected = 0x03DF;
-
- SPIBus bus{&spi};
-
- SPIBusConfig config;
- config.clockDivider = SPI::ClockDivider::DIV_16;
-
- config.mode = SPI::Mode::MODE_3;
- config.bit_order = SPIBitOrder::LSB_FIRST;
-
- bus.acquire(config);
- bus.select(spi.cs);
-
- SECTION("Write")
- {
- bus.write(1);
- REQUIRE(spi.DR.out_buf.back() == 1);
- REQUIRE(spi.DR.out_buf.size() == 1);
-
- bus.write(2);
- REQUIRE(spi.DR.out_buf.back() == 2);
- REQUIRE(spi.DR.out_buf.size() == 2);
- }
- SECTION("Read")
- {
- REQUIRE(bus.read() == spi.DR.in_buf[0]);
- REQUIRE(spi.DR.out_buf.size() == 1);
- REQUIRE(spi.DR.out_buf.back() == 0);
-
- REQUIRE(bus.read() == spi.DR.in_buf[1]);
- REQUIRE(spi.DR.out_buf.size() == 2);
- REQUIRE(spi.DR.out_buf.back() == 0);
- }
-
- SECTION("Transfer")
- {
- REQUIRE(bus.transfer(55) == spi.DR.in_buf[0]);
- REQUIRE(spi.DR.out_buf.back() == 55);
- REQUIRE(spi.DR.out_buf.size() == 1);
-
- REQUIRE(bus.transfer(255) == spi.DR.in_buf[1]);
- REQUIRE(spi.DR.out_buf.back() == 255);
- REQUIRE(spi.DR.out_buf.size() == 2);
- }
-
- bus.deselect(spi.cs);
- bus.release();
-}
-
-TEST_CASE("SPIBus - Multi byte operations")
-{
- FakeSpiTypedef spi;
-
- spi.DR.in_buf = {100, 101, 102, 103, 104, 105, 106, 107, 108};
- spi.CR1_expected = 0x03DF;
-
- SPIBus bus{&spi};
-
- SPIBusConfig config;
- config.clockDivider = SPI::ClockDivider::DIV_16;
-
- config.mode = SPI::Mode::MODE_3;
- config.bit_order = SPIBitOrder::LSB_FIRST;
-
- bus.acquire(config);
- bus.select(spi.cs);
-
- // 2 identical buffers
- uint8_t buf[] = {5, 4, 3, 2, 1};
- uint8_t bufc[] = {5, 4, 3, 2, 1};
-
- SECTION("Write")
- {
- bus.write(buf, 0);
- REQUIRE(spi.DR.out_buf.size() == 0);
-
- bus.write(buf, 1);
- REQUIRE(spi.DR.out_buf.size() == 1);
- REQUIRE(spi.DR.out_buf.back() == bufc[0]);
-
- bus.write(buf, 4);
- REQUIRE(spi.DR.out_buf.size() == 5);
- REQUIRE(bufcmp(bufc, spi.DR.out_buf.data() + 1, 4));
- }
-
- SECTION("Read")
- {
- bus.read(buf, 0);
- // Nothing read
- REQUIRE(bufcmp(bufc, buf, 5));
-
- bus.read(buf, 1);
- REQUIRE(bufcmp(buf, spi.DR.in_buf.data(), 1));
- // No overflows
- REQUIRE(bufcmp(bufc + 1, buf + 1, 4));
-
- bus.read(buf, 4);
- REQUIRE(bufcmp(buf, spi.DR.in_buf.data() + 1, 4));
- // No overflows
- REQUIRE(bufcmp(bufc + 4, buf + 4, 1));
- }
-
- SECTION("Transfer")
- {
- bus.transfer(buf, 0);
- // Nothing read
- REQUIRE(bufcmp(bufc, buf, 4));
- // Nothing written
- REQUIRE(spi.DR.out_buf.size() == 0);
-
- bus.transfer(buf, 1);
- REQUIRE(spi.DR.out_buf.size() == 1);
- REQUIRE(bufcmp(bufc, spi.DR.out_buf.data(), 1));
- REQUIRE(bufcmp(buf, spi.DR.in_buf.data(), 1));
- // No overflows
- REQUIRE(bufcmp(bufc + 1, buf + 1, 4));
-
- bus.transfer(buf + 1, 3);
- REQUIRE(spi.DR.out_buf.size() == 4);
- REQUIRE(bufcmp(bufc + 1, spi.DR.out_buf.data() + 1, 3));
- REQUIRE(bufcmp(buf + 1, spi.DR.in_buf.data() + 1, 3));
- // No overflows
- REQUIRE(bufcmp(bufc + 4, buf + 4, 1));
- }
-
- bus.deselect(spi.cs);
- bus.release();
-}
-
-TEST_CASE("SPITransaction - writes")
-{
- SPIBusConfig config1{};
-
- config1.mode = SPI::Mode::MODE_1;
- config1.clockDivider = SPI::ClockDivider::DIV_32;
-
- MockSPIBus bus(config1);
- MockGpioPin cs;
-
- SECTION("Transaction")
- {
- SPITransaction spi(bus, cs, config1);
-
- REQUIRE(bus.getOutBuf().size() == 0);
-
- SECTION("cmd write")
- {
- spi.write(9);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 1);
- REQUIRE(bus.getOutBuf().back() == 9);
- }
-
- SECTION("1 byte reg write")
- {
- spi.write(10, 77);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 2);
- REQUIRE(bus.getOutBuf()[0] == 10);
- REQUIRE(bus.getOutBuf()[1] == 77);
- }
-
- SECTION("multi byte reg write")
- {
- uint8_t buf[] = {1, 2, 3, 4, 5, 6};
-
- SECTION("0 size write")
- {
- spi.write(10, buf, 0);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 1);
- REQUIRE(bus.getOutBuf()[0] == 10);
- }
-
- SECTION("2 writes")
- {
- spi.write(10, buf, 4);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 5);
-
- REQUIRE(bus.getOutBuf()[0] == 10);
- REQUIRE(bufcmp(buf, bus.getOutBuf().data() + 1, 4));
-
- spi.write(99, buf, 6);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 12);
-
- REQUIRE(bus.getOutBuf()[5] == 99);
- REQUIRE(bufcmp(buf, bus.getOutBuf().data() + 6, 6));
- }
- }
-
- SECTION("raw write")
- {
- uint8_t buf[] = {1, 2, 3, 4, 5, 6};
-
- spi.write(buf, 0);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 0);
-
- spi.write(buf, 4);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 4);
-
- REQUIRE(bufcmp(buf, bus.getOutBuf().data(), 4));
-
- spi.write(buf, 6);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 10);
-
- REQUIRE(bufcmp(buf, bus.getOutBuf().data() + 4, 6));
- }
- }
-}
-
-TEST_CASE("SPITransaction - reads")
-{
- SPIBusConfig config1;
-
- config1.mode = SPI::Mode::MODE_1;
- config1.clockDivider = SPI::ClockDivider::DIV_32;
-
- MockSPIBus bus(config1);
- MockGpioPin cs;
-
- uint8_t in_data[10] = {100, 101, 102, 103, 104, 105, 106, 107, 108, 109};
- bus.push(in_data, 10);
-
- SECTION("Transaction")
- {
- SPISlave slave(bus, cs, config1);
- SPITransaction spi(slave);
-
- REQUIRE(bus.getOutBuf().size() == 0);
-
- SECTION("1 byte reg read")
- {
-
- REQUIRE(spi.read(0x05) == in_data[0]);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 1);
- REQUIRE(bus.getOutBuf().back() == 0x85);
-
- REQUIRE(spi.read(0x05, true) == in_data[1]);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 2);
- REQUIRE(bus.getOutBuf().back() == 0x85);
-
- REQUIRE(spi.read(0x05, false) == in_data[2]);
- REQUIRE_FALSE(bus.isSelected());
-
- REQUIRE(bus.getOutBuf().size() == 3);
- REQUIRE(bus.getOutBuf().back() == 0x05);
- }
-
- SECTION("multi byte reg read")
- {
- const int buf_size = 7;
- uint8_t buf[] = {1, 2, 3, 4, 5, 6, 7};
- uint8_t cmp[] = {1, 2, 3, 4, 5, 6, 7};
-
- spi.read(0x05, buf, 0);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 1);
- REQUIRE(bus.getOutBuf().back() == 0x85);
- REQUIRE(bufcmp(buf, cmp, buf_size));
-
- spi.read(0x05, buf, 3);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 2);
- REQUIRE(bus.getOutBuf().back() == 0x85);
- REQUIRE(bufcmp(buf, &in_data[0], 3));
- REQUIRE(bufcmp(buf + 3, cmp + 3, buf_size - 3));
-
- spi.read(0x05, buf, 3, true);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 3);
- REQUIRE(bus.getOutBuf().back() == 0x85);
- REQUIRE(bufcmp(buf, &in_data[3], 3));
- REQUIRE(bufcmp(buf + 3, cmp + 3, buf_size - 3));
-
- spi.read(0x05, buf, 4, false);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 4);
- REQUIRE(bus.getOutBuf().back() == 0x05);
- REQUIRE(bufcmp(buf, &in_data[6], 4));
- REQUIRE(bufcmp(buf + 4, cmp + 4, buf_size - 4));
- }
-
- SECTION("multi byte raw read")
- {
- const int buf_size = 7;
- uint8_t buf[] = {1, 2, 3, 4, 5, 6, 7};
- uint8_t cmp[] = {1, 2, 3, 4, 5, 6, 7};
-
- spi.read(buf, 0);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 0);
- REQUIRE(bufcmp(buf, cmp, buf_size));
-
- spi.read(buf, 3);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 0);
- REQUIRE(bufcmp(buf, &in_data[0], 3));
- REQUIRE(bufcmp(buf + 3, cmp + 3, buf_size - 3));
- }
- }
-}
-
-TEST_CASE("SPITransaction - transfer")
-{
- SPIBusConfig config1;
-
- config1.mode = SPI::Mode::MODE_1;
- config1.clockDivider = SPI::ClockDivider::DIV_32;
-
- MockSPIBus bus(config1);
- MockGpioPin cs;
-
- uint8_t data[10] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
-
- bus.push(data, 10);
-
- SECTION("Transaction")
- {
- SPISlave slave(bus, cs, config1);
- SPITransaction spi(slave);
-
- const int buf_size = 7;
- uint8_t buf[] = {1, 2, 3, 4, 5, 6, 7};
- uint8_t cmp[] = {1, 2, 3, 4, 5, 6, 7};
-
- spi.transfer(buf, 0);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 0);
- REQUIRE(bufcmp(buf, cmp, buf_size));
-
- spi.transfer(buf, 4);
- REQUIRE_FALSE(bus.isSelected());
- REQUIRE(bus.getOutBuf().size() == 4);
- REQUIRE(bufcmp(buf, &data[0], 4));
- REQUIRE(bufcmp(cmp, bus.getOutBuf().data(), 4));
- REQUIRE(bufcmp(buf + 4, cmp + 4, buf_size - 4));
- }
-}
diff --git a/old_examples/tests/catch/test-xbee.cpp b/old_examples/tests/catch/test-xbee.cpp
deleted file mode 100644
index 3ec81dfba6464ce558d983edec75abb2cbde0d2c..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/test-xbee.cpp
+++ /dev/null
@@ -1,327 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifdef STANDALONE_CATCH1_TEST
-#include "catch-tests-entry.cpp"
-#endif
-
-#include <catch2/catch.hpp>
-#include <vector>
-
-#define private public
-
-#include <radio/Xbee/Xbee.h>
-#include <utils/TestUtils/BusTemplateMock.h>
-
-using std::vector;
-
-// No-op GPIO mock
-class GpioMock
-{
-public:
- static int value() { return 0; }
-
- static void high() { (void)0; }
-
- static void low() { (void)0; }
-};
-
-typedef Xbee::Xbee<BusSPIMock, GpioMock, GpioMock> xbee_t;
-
-class XbeeTestFixture
-{
-public:
- XbeeTestFixture() {}
-
- ~XbeeTestFixture() { BusSPIMock::getInstance().restoreState(); }
-
-protected:
- BusSPIMock& spi = *BusSPIMock::getInstance();
- xbee_t xbee;
-};
-
-void buildRxPacket(vector<uint8_t>& packet, const vector<uint8_t>& payload)
-{
- using namespace Xbee;
- packet.reserve(API_HEADER_SIZE + RX_FRAME_HEADER_SIZE + payload.size() + 1);
-
- packet.push_back(START_DELIMITER);
- uint16_t frame_size = RX_FRAME_HEADER_SIZE + payload.size();
- packet.push_back((frame_size & 0xFF00) >> 8);
- packet.push_back(frame_size & 0xFF);
-
- packet.push_back(xbee_t::FRAMETYPE_RX_PACKET);
- uint64_t address = 0xFFFF;
-
- for (int i = 7; i >= 0; i--)
- {
- packet.push_back((address >> i * 8) & 0xFF);
- }
-
- packet.push_back(0xFF);
- packet.push_back(0xFE);
- packet.push_back(0x40);
-
- packet.insert(packet.end(), payload.begin(), payload.end());
-
- uint8_t checksum = 0;
- for (auto it = packet.begin() + 3; it != packet.end(); it++)
- {
- checksum += *it;
- }
- packet.push_back(0xFF - checksum);
-}
-
-TEST_CASE_METHOD(XbeeTestFixture, "[Xbee] Receive with transferData()")
-{
- SECTION("Test single receive")
- {
- vector<uint8_t> packet, payload;
- payload.resize(25, 0x55);
- buildRxPacket(packet, payload);
-
- REQUIRE(spi.getMOSI().size() == 0);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- REQUIRE(spi.getMOSI().size() == packet.size());
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
-
- /* SECTION("Test single receive with no payload")
- {
- vector<uint8_t> packet, payload;
- buildRxPacket(packet, payload);
-
- REQUIRE(spi.getMOSI().size() == 0);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- REQUIRE(spi.getMOSI().size() == packet.size());
-
- REQUIRE(xbee.rx_frame.size() == 0);
- }
-
- SECTION("Test double consecutive receive")
- {
- vector<uint8_t> packet, payload;
- payload.resize(25, 0x55);
- buildRxPacket(packet, payload);
-
- REQUIRE(spi.getMOSI().size() == 0);
-
- spi.addMISO(packet);
- spi.addMISO(packet);
-
- xbee.transferData();
- xbee.transferData();
-
- REQUIRE(spi.getMOSI().size() == packet.size() * 2);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
- }
-
- TEST_CASE_METHOD(XbeeTestFixture, "[Xbee] Full duplex with transferData()")
- {
- SECTION("Simple transmit")
- {
- vector<uint8_t> out(20, 0x55);
- REQUIRE(xbee.tx_buf.size() == 0);
-
- xbee.setTxBuf(out.data(), out.size());
- REQUIRE(xbee.tx_buf.size() == out.size());
-
- xbee.transferData();
- REQUIRE(xbee.tx_buf.size() == 0);
-
- REQUIRE(spi.getMOSI() == out);
- }
-
- SECTION("Transmit + Smaller receive starting at the same time")
- {
- vector<uint8_t> out(40, 0x44);
- xbee.setTxBuf(out.data(), out.size());
-
- vector<uint8_t> packet, payload;
- payload.resize(5, 0x55);
- buildRxPacket(packet, payload);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- REQUIRE(spi.getMOSI() == out);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
-
- SECTION("Transmit + 2 receives")
- {
- vector<uint8_t> out(40, 0x44);
- xbee.setTxBuf(out.data(), out.size());
-
- vector<uint8_t> packet, payload;
- payload.resize(5, 0x55);
- buildRxPacket(packet, payload);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- REQUIRE(spi.getMOSI() == out);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
-
- // Receive 2
-
- // Expcted output
- spi.restoreState();
- xbee_payload.clear();
-
- vector<uint8_t> expectedMOSI(packet.size(), 0x00);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- REQUIRE(spi.getMOSI() == expectedMOSI);
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
-
- SECTION("Transmit + Bigger receive starting at the same time")
- {
- vector<uint8_t> out(20, 0x44);
- xbee.setTxBuf(out.data(), out.size());
-
- vector<uint8_t> packet, payload;
- payload.resize(20, 0x55);
- buildRxPacket(packet, payload);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- out.resize(packet.size(), 0);
- REQUIRE(spi.getMOSI() == out);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
-
- SECTION("Transmit + Bigger receive starting later")
- {
- vector<uint8_t> out(20, 0x44);
- xbee.setTxBuf(out.data(), out.size());
-
- vector<uint8_t> packet, payload;
- payload.resize(20, 0x55);
- buildRxPacket(packet, payload);
- packet.insert(packet.begin(), 10, 0x00);
-
- spi.addMISO(packet);
-
- xbee.transferData();
-
- out.resize(packet.size(), 0);
- REQUIRE(spi.getMOSI() == out);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
- }
-
- SECTION("Transmit + Receive starting at incrementing bytes later")
- {
- for (int i = 0; i <= 20; i++)
- {
- vector<uint8_t> out(20, 0x44);
- xbee.setTxBuf(out.data(), out.size());
-
- vector<uint8_t> packet, payload;
- payload.resize(2, 0x55);
-
- buildRxPacket(packet, payload);
-
- packet.insert(packet.begin(), i, 0x00);
- spi.addMISO(packet);
-
- xbee.transferData();
- if(i == 20)
- {
- xbee.transferData();
- }
-
- if (out.size() < packet.size())
- {
- out.resize(packet.size(), 0x00);
- }
-
- REQUIRE(spi.getMOSI() == out);
-
- vector<uint8_t> xbee_payload;
-
- xbee_payload.insert(xbee_payload.end(), xbee.rx_frame.begin(),
- xbee.rx_frame.end());
-
- REQUIRE(xbee_payload == payload);
-
- spi.restoreState();
- }
- }*/
-}
diff --git a/old_examples/tests/catch/xbee/test-xbee-driver.cpp b/old_examples/tests/catch/xbee/test-xbee-driver.cpp
deleted file mode 100644
index f6ccad0ccc1cdf050be6baa3988429dd2184e0e8..0000000000000000000000000000000000000000
--- a/old_examples/tests/catch/xbee/test-xbee-driver.cpp
+++ /dev/null
@@ -1,421 +0,0 @@
-/* Copyright (c) 2021 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#ifdef STANDALONE_CATCH1_TEST
-#include "../catch-tests-entry.cpp"
-#endif
-#include <drivers/spi/SPIDriver.h>
-#include <radio/Xbee/Xbee.h>
-
-#include <catch2/catch.hpp>
-#include <ctime>
-#include <future>
-#include <memory>
-
-#include "MockXbeeSPIBus.h"
-
-using namespace Xbee;
-using std::async;
-using std::unique_ptr;
-
-using uint8_ptr = unique_ptr<uint8_t>;
-
-/**
- * @brief Generates a sequence of incremental bytes
- */
-uint8_ptr incrementalBytes(size_t length, uint8_t start_from = 0)
-{
- uint8_ptr bytes(new uint8_t[length]);
-
- for (size_t i = 0; i < length; i++)
- {
- bytes.get()[i] = (start_from + i) % 256;
- }
-
- return bytes;
-}
-
-class XbeeWrapper
-{
-public:
- XbeeWrapper(unsigned int tx_timeout)
- : bus(new MockXbeeSPIBus(xbee_cfg, attn)),
- xbee(new Xbee::Xbee(*bus.get(), xbee_cfg, cs, attn, rst, tx_timeout))
- {
- attn.high();
- }
-
- MockGpioPin cs;
- MockGpioPin attn;
-
- MockGpioPin rst;
-
- SPIBusConfig xbee_cfg{};
-
- unique_ptr<MockXbeeSPIBus> bus;
- unique_ptr<Xbee::Xbee> xbee;
-};
-
-TEST_CASE("[Xbee] Test xbee.send(...) by itself")
-{
- uint8_ptr pkt = incrementalBytes(Xbee::MAX_PACKET_PAYLOAD_LENGTH + 1);
- uint8_ptr pkt_orig = incrementalBytes(Xbee::MAX_PACKET_PAYLOAD_LENGTH + 1);
-
- XbeeWrapper wrap(DEFAULT_TX_TIMEOUT);
-
- SECTION("Middle payload length")
- {
- REQUIRE(wrap.xbee->send(pkt.get(), 128));
- REQUIRE(wrap.bus->getParsedFrames().size() > 0);
-
- REQUIRE(wrap.bus->getParsedFrames().front().frame_type ==
- Xbee::FTYPE_TX_REQUEST);
-
- TXRequestFrame tx_req = *wrap.bus->getParsedFrames()
- .front()
- .toFrameType<Xbee::TXRequestFrame>();
-
- REQUIRE(tx_req.getRFDataLength() == 128);
- REQUIRE(memcmp(tx_req.getRFDataPointer(), pkt_orig.get(), 128) == 0);
- }
-
- SECTION("Max payload length")
- {
- REQUIRE(wrap.xbee->send(pkt.get(), Xbee::MAX_PACKET_PAYLOAD_LENGTH));
- REQUIRE(wrap.bus->getParsedFrames().size() > 0);
-
- REQUIRE(wrap.bus->getParsedFrames().front().frame_type ==
- Xbee::FTYPE_TX_REQUEST);
-
- TXRequestFrame tx_req = *wrap.bus->getParsedFrames()
- .front()
- .toFrameType<Xbee::TXRequestFrame>();
-
- REQUIRE(tx_req.getRFDataLength() == Xbee::MAX_PACKET_PAYLOAD_LENGTH);
- REQUIRE(memcmp(tx_req.getRFDataPointer(), pkt_orig.get(),
- Xbee::MAX_PACKET_PAYLOAD_LENGTH) == 0);
- }
-
- SECTION("Oversize payload")
- {
- REQUIRE_FALSE(
- wrap.xbee->send(pkt.get(), Xbee::MAX_PACKET_PAYLOAD_LENGTH + 1));
- REQUIRE(wrap.bus->getParsedFrames().size() == 0);
- }
-
- SECTION("No payload")
- {
- REQUIRE_FALSE(wrap.xbee->send(pkt.get(), 0));
- REQUIRE(wrap.bus->getParsedFrames().size() == 0);
- }
-
- SECTION("Send error")
- {
- wrap.bus->setRespondWithTxStatus(true, DELS_NO_SPECTRUM_AVAILABLE);
-
- REQUIRE_FALSE(
- wrap.xbee->send(pkt.get(), Xbee::MAX_PACKET_PAYLOAD_LENGTH));
- }
-
- SECTION("TX status timeout")
- {
- wrap.bus->setRespondWithTxStatus(false);
-
- long long start = miosix::getTick();
-
- REQUIRE_FALSE(
- wrap.xbee->send(pkt.get(), Xbee::MAX_PACKET_PAYLOAD_LENGTH));
-
- // Should not have returned until the timeout has expired
- REQUIRE(miosix::getTick() >= start + DEFAULT_TX_TIMEOUT);
- }
-}
-
-TEST_CASE("[Xbee] Test xbee.receive(...) by itself")
-{
- uint8_ptr rx_buf(new uint8_t[MAX_PACKET_PAYLOAD_LENGTH]);
-
- uint8_ptr pkt = incrementalBytes(Xbee::MAX_PACKET_PAYLOAD_LENGTH);
-
- XbeeWrapper wrap(DEFAULT_TX_TIMEOUT);
-
- RXPacketFrame rx;
- rx.setRXDataLength(MAX_PACKET_PAYLOAD_LENGTH);
- memcpy(rx.getRXDataPointer(), pkt.get(), MAX_PACKET_PAYLOAD_LENGTH);
- rx.setReceiveOptions(RO_POINT_MULTIPOINT);
- rx.setSourceAddress(0x1122334455667788);
-
- SECTION("RX buffer bigger than RX packet payload")
- {
- rx.setRXDataLength(50);
- rx.calcChecksum();
-
- wrap.bus->pushApiFrame(rx);
-
- REQUIRE(wrap.xbee->receive(rx_buf.get(), MAX_PACKET_PAYLOAD_LENGTH) ==
- 50);
-
- REQUIRE(memcmp(rx_buf.get(), pkt.get(), 50) == 0);
- }
-
- SECTION("RX buffer smaller than RX packet payload")
- {
- rx.setRXDataLength(130);
- rx.calcChecksum();
-
- wrap.bus->pushApiFrame(rx);
-
- REQUIRE(wrap.xbee->receive(rx_buf.get(), 50) == 50);
- REQUIRE(wrap.xbee->receive(rx_buf.get() + 50, 50) == 50);
- REQUIRE(wrap.xbee->receive(rx_buf.get() + 100, 50) == 30);
-
- REQUIRE(memcmp(rx_buf.get(), pkt.get(), 130) == 0);
- }
-
- SECTION("RX buffer == 1")
- {
- rx.setRXDataLength(30);
- rx.calcChecksum();
-
- wrap.bus->pushApiFrame(rx);
-
- for (int i = 0; i < 30; i++)
- {
- REQUIRE(wrap.xbee->receive(rx_buf.get() + i, 1) == 1);
- }
-
- REQUIRE(memcmp(rx_buf.get(), pkt.get(), 30) == 0);
- }
-
- SECTION("RX packet with wrong checksum")
- {
- rx.setRXDataLength(20);
- rx.calcChecksum();
- wrap.bus->pushApiFrame(rx);
-
- rx.setRXDataLength(21);
- rx.calcChecksum();
- rx.setRXDataLength(20); // Now the checksum is wrong
- wrap.bus->pushApiFrame(rx);
-
- // Only receive one of the two frames
- REQUIRE(wrap.xbee->receive(rx_buf.get(), 50) == 20);
-
- auto dont_care = async(std::launch::async,
- [&]()
- {
- miosix::Thread::sleep(1000);
- wrap.xbee->wakeReceiver(true);
- });
-
- // This should block until we force it to return
- REQUIRE(wrap.xbee->receive(rx_buf.get(), 50) == -1);
- }
-
- SECTION("receive() blocks until an interrupt is received")
- {
- rx.setRXDataLength(20);
- rx.calcChecksum();
-
- // Send an rx frame in one second
- auto dont_care = async(std::launch::async,
- [&]()
- {
- miosix::Thread::sleep(1000);
- wrap.bus->pushApiFrame(rx);
- wrap.xbee->wakeReceiver();
- });
-
- long long start = miosix::getTick();
- REQUIRE(wrap.xbee->receive(rx_buf.get(), 50) == 20);
-
- // Should not have returned before we sent the rx frame
- REQUIRE(miosix::getTick() >= start + 1000);
- }
-}
-
-TEST_CASE("[Xbee] Receive while sending")
-{
- uint8_ptr rx_buf(new uint8_t[MAX_PACKET_PAYLOAD_LENGTH]);
-
- uint8_ptr pkt_rx = incrementalBytes(Xbee::MAX_PACKET_PAYLOAD_LENGTH);
- uint8_ptr pkt_tx = incrementalBytes(Xbee::MAX_PACKET_PAYLOAD_LENGTH);
-
- XbeeWrapper wrap(1000);
- wrap.bus->setRespondWithTxStatus(true, 0);
-
- RXPacketFrame rx;
- rx.setRXDataLength(MAX_PACKET_PAYLOAD_LENGTH);
- memcpy(rx.getRXDataPointer(), pkt_rx.get(), MAX_PACKET_PAYLOAD_LENGTH);
- rx.setReceiveOptions(RO_POINT_MULTIPOINT);
- rx.setSourceAddress(0x1122334455667788);
-
- int num_rx_while_tx = 0;
-
- wrap.xbee->setOnFrameReceivedListener(
- [&](APIFrame& api)
- {
- if (api.frame_type == FTYPE_RX_PACKET_FRAME)
- {
- ++num_rx_while_tx;
- }
- });
-
- SECTION("2 RX packet smaller than one TX packet")
- {
- rx.setRXDataLength(50);
- rx.calcChecksum();
-
- wrap.bus->pushApiFrame(rx);
- wrap.bus->pushApiFrame(rx);
-
- REQUIRE(wrap.xbee->send(pkt_tx.get(), 150));
-
- REQUIRE(num_rx_while_tx == 2);
-
- size_t rx_len = 0;
- while (rx_len < 100)
- {
- rx_len += wrap.xbee->receive(rx_buf.get() + rx_len, 200);
- }
-
- REQUIRE(rx_len == 100);
- REQUIRE(memcmp(rx_buf.get(), pkt_rx.get(), 50) == 0);
- REQUIRE(memcmp(rx_buf.get() + 50, pkt_rx.get(), 50) == 0);
- }
-
- SECTION("More RX packets than buffer size: drop the oldest")
- {
- rx.setRXDataLength(10);
-
- // 1 packet too many
- unsigned int numpkts = RX_FRAMES_BUF_SIZE + 1;
- for (unsigned int i = 0; i < numpkts; i++)
- {
- memcpy(rx.getRXDataPointer(), pkt_rx.get() + i, 10);
- rx.calcChecksum();
- wrap.bus->pushApiFrame(rx);
- }
-
- // Should receive all the packets while sending
- REQUIRE(wrap.xbee->send(pkt_tx.get(), MAX_PACKET_PAYLOAD_LENGTH));
-
- REQUIRE(num_rx_while_tx == numpkts);
-
- // Only receive the last three packets
- size_t rx_len = 0;
- while (rx_len < (numpkts - 1) * 10)
- {
- rx_len += wrap.xbee->receive(rx_buf.get() + rx_len, 200);
- }
-
- REQUIRE(rx_len == (numpkts - 1) * 10);
-
- for (unsigned int i = 0; i < numpkts - 1; i++)
- {
- REQUIRE(memcmp(rx_buf.get() + i * 10, pkt_rx.get() + i + 1, 10) ==
- 0);
- }
- }
-
- SECTION("2 RX packet smaller than one TX packet, 1 byte receive")
- {
- rx.setRXDataLength(50);
- rx.calcChecksum();
-
- wrap.bus->pushApiFrame(rx);
- wrap.bus->pushApiFrame(rx);
-
- REQUIRE(wrap.xbee->send(pkt_tx.get(), 150));
-
- REQUIRE(num_rx_while_tx == 2);
-
- for (int i = 0; i < 50; i++)
- {
- REQUIRE(wrap.xbee->receive(rx_buf.get() + i, 1) == 1);
- }
- REQUIRE(memcmp(rx_buf.get(), pkt_rx.get(), 50) == 0);
-
- for (int i = 0; i < 50; i++)
- {
- REQUIRE(wrap.xbee->receive(rx_buf.get() + i, 1) == 1);
- }
- REQUIRE(memcmp(rx_buf.get(), pkt_rx.get(), 50) == 0);
- }
-}
-
-TEST_CASE("[Xbee] Test Xbee::sendAtCommand(...)")
-{
- XbeeWrapper wrap(DEFAULT_TX_TIMEOUT);
-
- SECTION("AT Command, no response required")
- {
- wrap.xbee->sendATCommand("AB");
-
- REQUIRE(wrap.bus->getParsedFrames().size() > 0);
- REQUIRE(wrap.bus->getParsedFrames()[0].frame_type == FTYPE_AT_COMMAND);
- }
-
- SECTION("AT Command, response required but not received")
- {
- ATCommandResponseFrame response;
- long long start = miosix::getTick();
- REQUIRE_FALSE(
- wrap.xbee->sendATCommand("AB", &response, nullptr, 0, 1000));
- REQUIRE(miosix::getTick() >= start + 1000);
-
- REQUIRE(wrap.bus->getParsedFrames().size() > 0);
- REQUIRE(wrap.bus->getParsedFrames()[0].frame_type == FTYPE_AT_COMMAND);
- }
-
- SECTION("AT Command, response required and received")
- {
- // Padding required in order to not receive the ATCommandResponse
- // frame too early in testing
- RXPacketFrame padding;
- padding.setRXDataLength(50);
- padding.calcChecksum();
-
- ATCommandResponseFrame resp;
- resp.setATCommand("AB");
- resp.setFrameID(1);
- resp.setCommandDataSize(1);
- resp.getCommandDataPointer()[0] = 0xAB;
- resp.calcChecksum();
-
- wrap.bus->pushApiFrame(padding);
- wrap.bus->pushApiFrame(resp);
-
- ATCommandResponseFrame received_response;
- long long start = miosix::getTick();
-
- REQUIRE(wrap.xbee->sendATCommand("AB", &received_response, nullptr, 0,
- 1000));
- REQUIRE(miosix::getTick() < start + 1000);
-
- REQUIRE(wrap.bus->getParsedFrames().size() > 0);
- REQUIRE(wrap.bus->getParsedFrames()[0].frame_type == FTYPE_AT_COMMAND);
-
- REQUIRE(received_response.getCommandDataLength() == 1);
- REQUIRE(received_response.getCommandDataPointer()[0] == 0xAB);
- }
-}
diff --git a/old_examples/tests/drivers/flashmemory/mockup/FlashDriver.h b/old_examples/tests/drivers/flashmemory/mockup/FlashDriver.h
deleted file mode 100644
index 0d6b1462087c25c60653527443d5266446690cec..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/flashmemory/mockup/FlashDriver.h
+++ /dev/null
@@ -1,598 +0,0 @@
-/* Copyright (c) 2020 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#pragma once
-
-#include <Singleton.h>
-#include <diagnostic/NewLogger.h>
-#include <miosix.h>
-
-using logging::logger;
-using miosix::Mode;
-using miosix::Thread;
-
-// Forward declaration
-namespace testing
-{
-namespace flashmemorytests
-{
-template <typename>
-class FlashTest;
-}
-} // namespace testing
-
-namespace flashmemory
-{
-
-static const uint32_t PAGES_PER_SUBSECTOR = 4U;
-static const uint32_t PAGES_PER_SECTOR = 16U;
-static const uint32_t SUBSECTORS_PER_SECTOR = 4U;
-
-static const uint32_t SUBSECTORS_NUM = 48U;
-static const uint32_t SECTORS_NUM = 12U;
-static const uint32_t PAGE_SIZE = 256U;
-
-static const uint32_t SUBSECTOR_SIZE = PAGE_SIZE * PAGES_PER_SUBSECTOR;
-static const uint32_t SECTOR_SIZE = PAGE_SIZE * PAGES_PER_SECTOR;
-
-static const uint32_t BANK_SIZE = SECTOR_SIZE * SECTORS_NUM / 2;
-static const uint32_t MEMORY_SIZE = SECTOR_SIZE * SECTORS_NUM;
-
-/**
- * @brief Definitions for results of various flash operations.
- *
- * Definitions for result flags of various flash operations.
- */
-
-enum OpResultFlags
-{
- RESULT_OK = 0x00,
-
- RESULT_F_OUT_OF_MEMORY = 0x01,
- RESULT_F_CHECK_FAIL = 0x04,
-
- // Bits reserved for future use
- RESULT_F_UNUSED_1 = 0x08,
- RESULT_F_UNUSED_2 = 0x40,
- RESULT_F_UNUSED_3 = 0x80,
-
- /**
- * These bits are in the same positions of the corresponding bits in the
- * FLAG STATUS REGISTER
- */
- RESULT_F_PROTECTION_ERROR = 0x02,
- RESULT_F_PROGRAM_ERROR = 0x10,
- RESULT_F_ERASE_ERROR = 0x20
-};
-
-template <typename Bus>
-class FlashDriver : Singleton<FlashDriver<Bus>>
-{
- typedef Singleton<FlashDriver<Bus>> SingletonType;
-
- friend class Singleton<FlashDriver<Bus>>;
-
- template <typename>
- friend class FlashDriverTest;
-
- template <typename>
- friend class testing::flashmemorytests::FlashTest;
-
-public:
- ~FlashDriver() { delete fake_memory_; }
-
- /**
- * @brief Read n bytes into a buffer, starting from the specified address
- *
- * @param result
- * @param address Starting address
- * @param buf Buffer to read data into
- * @param size Number of bytes to read
- */
- void read(uint8_t* result, uint32_t address, uint8_t* buf, uint32_t size)
- {
- if (address + size > MEMORY_SIZE)
- {
- logger.error(logtag(),
- "Read outside of memory bounds addr + size: ",
- address + size, " MEMSIZE: ", MEMORY_SIZE);
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- uint32_t rsize;
- if (address < BANK_SIZE)
- rsize = std::min(size, BANK_SIZE - address);
- else
- rsize = size;
-
- // uint8_t addr_buf[4];
- // addr_to_buf(addr_buf, address);
-
- fakeRead(address, buf, rsize);
- // Bus::read(READ, addr_buf, buf, 4, rsize);
-
- size -= rsize;
-
- // This means that we reached the end of the first die but we still need
- // to read some data.
- if (size > 0)
- {
- address += rsize;
- buf += rsize;
-
- // addr_to_buf(addr_buf, address);
-
- // Read the remaining bytes
- fakeRead(address, buf, size);
- // Bus::read(READ, addr_buf, buf, 4, size);
- }
-
- *result = RESULT_OK;
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address.
- *
- * @param address
- * @param data
- * @param size
- */
- void write(uint8_t* result, uint32_t address, uint8_t* data, uint32_t size)
- {
- // Do not write outside of the memory
- if (address + size > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- *result = RESULT_OK;
-
- // uint8_t addr_buf[4], status;
-
- uint32_t next_page, wsize;
-
- do
- {
- next_page = (address / 256) * 256 + 256;
-
- wsize = std::min(next_page - address, size);
-
- // addr_to_buf(addr_buf, address);
- //_write_enable();
-
- fakeWrite(address, data, wsize);
- /*Bus::write(PROGRAM_PAGE, addr_buf, data, 4, wsize);
-
- do {
- status = _read_flag_status_reg();
- }while((status & FSR_PRG_ERS_CTRL) == 0);*/
-
- data += wsize;
- size -= wsize;
- address = next_page;
-
- } while (size > 0 && *result == RESULT_OK);
-
- /*//Clear flag status register if an error occurred
- if(*result != RESULT_OK)
- {
- _clear_flag_status_reg();
-
- //Manually reset write_enable latch
- if((*result & RESULT_PROTECTION_ERROR) > 0)
- {
- _write_disable();
- }
- }*/
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address, then
- * checks if everything was written correctly.
- *
- * @param address
- * @param data
- * @param size
- */
- void writeAndCheck(uint8_t* result, uint32_t address, uint8_t* data,
- uint32_t size)
- { // TODO: size_t
- write(result, address, data, size);
- if (*result == RESULT_OK)
- {
- uint8_t* check = new uint8_t[size];
- read(result, address, check, size);
- for (uint32_t i = 0; i < size; i++)
- {
- if (*check++ != *data++)
- {
- // Something was not written/read correctly.
- *result = RESULT_F_CHECK_FAIL;
- break;
- }
- }
- }
- }
-
- /**
- * @brief Writes data on the flash starting from the specified address, only
- * if the provided data fits in a single page.
- *
- * Writes data on the flash starting from the specified address, only
- * if the provided data fits in a single page. If too much data is provided
- * nothing will be written and result will be set to FLASH_OUT_OF_RANGE.
- *
- * @param result
- * @param address
- * @param data
- * @param size
- */
- void programPage(uint8_t* result, uint32_t address, uint8_t* data,
- uint32_t size)
- {
- /*//Do now wrap around a page and do not try to write outside of the
- memory uint32_t next_page = (address / 256)*256 + 256; if(address +
- size > next_page || address > MEMORY_SIZE)
- {
- *result = RESULT_OUT_OF_RNG;
- return;
- }
-
- uint8_t addr_buf[4], status;
- addr_to_buf(addr_buf, address);
-
- _write_enable();
- Bus::write(PROGRAM_PAGE, addr_buf, data, 4, size);
-
- do {
- status = _read_flag_status_reg();
- }while((status & FSR_PRG_ERS_CTRL) == 0);
-
- *result = status & (FSR_PROGRAM | FSR_PROTECTION);
-
- //Clear flag status register if an error has been encountered
- if(*result != RESULT_OK)
- {
- _clear_flag_status_reg();
-
- //Manually reset write_enable latch
- if((*result & RESULT_PROTECTION_ERROR) > 0)
- {
- _write_disable();
- }
- }*/
- }
-
- /**
- * @brief Enables or disables read only mode
- */
- void setReadOnly(bool readonly = true) { read_only_ = readonly; }
-
- bool isReadOnly() const { return read_only_; }
-
- /**
- * @brief Enable the next erase operation. Call this before every erase op.
- */
- void enableErase() { m_erase_enable_ = true; }
-
- /**
- * @brief Erases the subsector containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- *
- * @warning Estimated execution time is slightly less than 1 second.
- *
- * @param result
- * @param address
- */
- void eraseSubsector(uint8_t* result, uint32_t address)
- {
- erase(result, SUBSECTOR_ERASE, address);
- }
-
- /**
- * @brief Erases the sector containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- * @warning Estimated execution time is about 2 seconds.
- *
- * @param result
- * @param address
- */
- void eraseSector(uint8_t* result, uint32_t address)
- {
- erase(result, SECTOR_ERASE, address);
- }
-
- /**
- * @brief Erases the entire die containing the specified address. For the
- * operation to be successful, enable_erase_op must be called before this.
- * @warning Estimated execution time is more than 4 minutes.
- *
- * @param result
- * @param die: 0 to erase the first die, 1 to erase the second.
- */
- void eraseDie(uint8_t* result, uint8_t die)
- {
- if (die == 0)
- {
- erase(result, DIE_ERASE, 0);
- }
- else if (die == 1)
- {
- erase(result, DIE_ERASE, BANK_SIZE);
- }
- }
-
- /**
- * Reads id information for this flash memory.
- * @param buf Buffer with at least 20 bytes
- */
- void readId(uint8_t* buf)
- {
- // Bus::read(READ_ID, buf, 20);
- }
-
- /**
- * @brief Software reset for the memory. All volatile bits are set to their
- * default value.
- */
- void softReset()
- {
- /*Bus::write(RESET_ENABLE);
- usleep(5);
- Bus::write(RESET_MEMORY);
- _wait_until_ready();*/
- }
-
-private:
- FlashDriver()
- {
- printf("Mock memory size: %d\n", (int)MEMORY_SIZE);
- memset((void*)(fake_memory_), 0xFF, MEMORY_SIZE);
- }
-
- void erase(uint8_t* result, uint8_t erase_cmd, uint32_t address)
- {
- if (address > MEMORY_SIZE)
- {
- *result = RESULT_F_OUT_OF_MEMORY;
- return;
- }
-
- if (!m_erase_enable_)
- {
- *result = RESULT_F_ERASE_ERROR;
- return;
- }
-
- // uint8_t addr_buf[4], status;
- // addr_to_buf(addr_buf, address);
- *result = RESULT_OK;
- switch (erase_cmd)
- {
- case SUBSECTOR_ERASE:
- address = address / SUBSECTOR_SIZE * SUBSECTOR_SIZE;
- fakeErase(address, SUBSECTOR_SIZE);
- break;
- case SECTOR_ERASE:
- address = address / SECTOR_SIZE * SECTOR_SIZE;
- fakeErase(address, SECTOR_SIZE);
- break;
- case DIE_ERASE:
- address = address / BANK_SIZE * BANK_SIZE;
- fakeErase(address, BANK_SIZE);
- break;
- default:
- *result = RESULT_F_ERASE_ERROR;
- }
-
- m_erase_enable_ = false;
- }
-
- /**
- * @brief Checks if a program operation is still in progress.
- * @param result
- */
- bool isBusy()
- {
- return false; //_read_flag_status_reg() & FSR_PRG_ERS_CTRL;
- }
-
- /**
- * @brief Waits until the memory is ready to perform a new write/erase op.
- * @param result
- */
- void waitUntilReady()
- {
- /*while((_read_flag_status_reg() & FSR_PRG_ERS_CTRL) == 0)
- {
-
- }*/
- }
-
- uint8_t readStatusReg()
- {
- return 0;
- /*uint8_t ret = Bus::read(READ_STATUS_REG);
- return ret;*/
- }
-
- void writeStatusReg(uint8_t val)
- {
- /*_write_enable();
- Bus::write(WRITE_STATUS_REG, val);
- _write_disable();
- _wait_until_ready();*/
- }
-
- uint8_t readFlagStatusReg()
- {
- /*uint8_t ret = Bus::read(READ_FLAG_STATUS_REG);
- return ret;*/
- return 0;
- }
-
- void clearFlagStatusReg()
- {
- // Bus::write(CLEAR_FLAG_STATUS_REG);
- }
-
- uint16_t readConfigReg()
- {
- /*uint8_t buf[2];
- Bus::read(READ_NV_CONFIG_REG, buf, 2);
-
- uint16_t res = buf[0] | (buf[1] << 8);*/
-
- return 0;
- }
-
- void writeConfigReg(uint16_t val)
- {
- /*
- * Mask some of the bits of the config register because
- * we don't want to change them by accident.
- */
- /*val = val | 0x0FEC;
-
- uint8_t buf[2];
- buf[0] = val & 0xFF;
- buf[1] = (val >> 8) & 0xFF;
-
- _write_enable();
- Bus::write(WRITE_NV_CONFIG_REG, buf, 2);
- _write_disable();
- _wait_until_ready();*/
- }
-
- void writeEnable()
- {
- /*if(!m_read_only) {
- Bus::write(WRITE_ENABLE);
- }*/
- }
-
- void writeDisable()
- {
- // Bus::write(WRITE_DISABLE);
- }
-
- static void addrToBuf(uint8_t* buf, uint32_t addr)
- {
- for (int i = 0; i < 4; i++)
- {
- buf[3 - i] = (addr >> 8 * i) & 0xFF;
- }
- }
-
- void fakeRead(uint32_t address, uint8_t* data, uint32_t size)
- {
- // printf("Reading %d bytes from %d \n", (int)size, (int)address);
- if (address + size > MEMORY_SIZE)
- {
- return;
- }
-
- memcpy((void*)(data), (void*)(fake_memory_ + address), size);
- }
-
- void fakeWrite(uint32_t address, uint8_t* data, uint32_t size)
- {
- if (address + size > MEMORY_SIZE)
- {
- return;
- }
-
- for (uint32_t i = 0; i < size; i++)
- {
- fake_memory_[address + i] &= data[i];
- }
-
- // memcpy((void*)(fake_memory_ + address), (void*)(data), size);
- }
-
- void fakeErase(uint32_t address, uint32_t size)
- {
- if (address + size > MEMORY_SIZE)
- {
- return;
- }
-
- memset((void*)(fake_memory_ + address), 0xFF, size);
- }
-
- static std::string logtag() { return "FlashDriver"; }
-
- enum Commands
- {
- READ_ID = 0x9F,
-
- WRITE_ENABLE = 0x06,
- WRITE_DISABLE = 0x04,
-
- READ_STATUS_REG = 0x05,
- WRITE_STATUS_REG = 0x01,
-
- READ_FLAG_STATUS_REG = 0x70,
- CLEAR_FLAG_STATUS_REG = 0x50,
-
- // non-volatile configuration register
- READ_NV_CONFIG_REG = 0xB5,
- WRITE_NV_CONFIG_REG = 0xB1,
-
- // volatile configuration register
- WRITE_VOL_CONFIG_REG = 0x85,
- READ_VOL_CONFIG_REG = 0x81,
-
- READ_EXT_ADDRESS_REG = 0xC8,
- WRITE_EXT_ADDRESS_REG = 0xC5,
-
- RESET_ENABLE = 0x66,
- RESET_MEMORY = 0x99,
-
- READ = 0x03,
- PROGRAM_PAGE = 0x02,
-
- SUBSECTOR_ERASE = 0x20,
- SECTOR_ERASE = 0xD8,
- DIE_ERASE = 0xC4
- };
-
- uint8_t* fake_memory_ = new uint8_t[MEMORY_SIZE];
- bool read_only_ = false;
- bool m_erase_enable_ = false;
-
- /**
- * Flag status register bit definitions
- */
- static const uint8_t FSR_ADDRESSING_MODE = 0x01;
- static const uint8_t FSR_PROTECTION = 0x02;
- static const uint8_t FSR_PROGRAM_SUSPEND = 0x04;
- static const uint8_t FSR_VPP = 0x08;
- static const uint8_t FSR_PROGRAM = 0x10;
- static const uint8_t FSR_ERASE = 0x20;
- static const uint8_t FSR_ERASE_SUSPEND = 0x40;
- static const uint8_t FSR_PRG_ERS_CTRL = 0x80;
-};
-
-} // namespace flashmemory
diff --git a/old_examples/tests/drivers/test-ad7994-bare.cpp b/old_examples/tests/drivers/test-ad7994-bare.cpp
deleted file mode 100644
index fddbddef2d6e50f91dbd1f4098c047cfa249e7be..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-ad7994-bare.cpp
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/BusTemplate.h>
-#include <miosix.h>
-
-#include <cstdint>
-#include <cstdio>
-
-using namespace miosix;
-
-const uint8_t ADDRESS = 0x22 << 1;
-const uint8_t REG_CONFIG = 0x02;
-const uint8_t DEFAULT_CONFIG = 0x08;
-
-typedef ProtocolI2C<I2C1Driver> my_i2c1;
-
-int main()
-{
- // soft_i2c::init();
- my_i2c1::init();
-
- uint8_t reg_config = REG_CONFIG;
- uint8_t config_val = 0x0A;
- uint8_t config_read_val;
- for (;;)
- {
- // Read default value
- my_i2c1::directWrite(ADDRESS, ®_config, 1);
- my_i2c1::directRead(ADDRESS, &config_read_val, 1);
-
- if (config_read_val == DEFAULT_CONFIG)
- {
- printf("1. Read ok.\n");
- }
- else
- {
- printf("1. ERROR. read: %d\n", config_read_val);
- }
- Thread::sleep(200);
- // Write custom value and read back.
- my_i2c1::write(ADDRESS, REG_CONFIG, &config_val, 1);
- my_i2c1::directRead(ADDRESS, &config_read_val, 1);
-
- if (config_read_val == config_val)
- {
- printf("2. Read ok.\n");
- }
- else
- {
- printf("2. ERROR. read: %d\n", config_read_val);
- }
-
- Thread::sleep(200);
- // Read back the wrong way
- config_read_val = 0;
- my_i2c1::read(ADDRESS, REG_CONFIG, &config_read_val, 1);
-
- if (config_read_val != config_val)
- {
- printf("3. OK. Reading the wrong way doesn't work as expected\n");
- }
- else
- {
- printf("3. ERROR. Succesfully read when it should't\n");
- }
- printf("\n\n");
- Thread::sleep(1500);
- }
-}
diff --git a/old_examples/tests/drivers/test-ad7994.cpp b/old_examples/tests/drivers/test-ad7994.cpp
deleted file mode 100644
index 4875e22d6a38c05e7cb69f93defff678243086e1..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-ad7994.cpp
+++ /dev/null
@@ -1,76 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Authors: Luca Erbetta, Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/BusTemplate.h>
-#include <drivers/adc/AD7994.h>
-#include <miosix.h>
-
-using namespace miosix;
-
-// Homeone and deathstack already define pins
-#include <interfaces-impl/hwmapping.h>
-using I2CProtocol = ProtocolI2C<miosix::I2C1Driver>;
-
-using convst = miosix::sensors::ad7994::nconvst;
-using busy = miosix::sensors::ad7994::ab;
-static constexpr uint8_t addr = miosix::sensors::ad7994::addr;
-
-typedef AD7994<I2CProtocol, busy, convst> AD7994_t;
-
-int main()
-{
- convst::mode(Mode::OUTPUT);
-
- AD7994_t ad{addr};
- if (ad.init())
- printf("Init succeeded\n");
- else
- printf("Init failed\n");
-
- ad.enableChannel(AD7994_t::Channel::CH1);
- ad.enableChannel(AD7994_t::Channel::CH2);
- ad.enableChannel(AD7994_t::Channel::CH3);
- ad.enableChannel(AD7994_t::Channel::CH4);
-
- AD7994Sample sample1, sample2, sample3, sample4;
-
- for (;;)
- {
- if (ad.onSimpleUpdate())
- {
- sample1 = ad.getLastSample(AD7994_t::Channel::CH1);
- sample2 = ad.getLastSample(AD7994_t::Channel::CH2);
- sample3 = ad.getLastSample(AD7994_t::Channel::CH3);
- sample4 = ad.getLastSample(AD7994_t::Channel::CH4);
- printf("timestamp: %d value: %d\n", (int)sample1.timestamp,
- (int)sample1.value);
- printf("timestamp: %d value: %d\n", (int)sample2.timestamp,
- (int)sample2.value);
- printf("timestamp: %d value: %d\n", (int)sample3.timestamp,
- (int)sample3.value);
- printf("timestamp: %d value: %d\n\n", (int)sample4.timestamp,
- (int)sample4.value);
- }
-
- Thread::sleep(1000);
- }
-}
diff --git a/old_examples/tests/drivers/test-i2c-mpu9255.cpp b/old_examples/tests/drivers/test-i2c-mpu9255.cpp
deleted file mode 100644
index fdb4778f69f71b563748d914971a94c65a96a51f..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-i2c-mpu9255.cpp
+++ /dev/null
@@ -1,84 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/BusTemplate.h>
-#include <miosix.h>
-#include <util/software_i2c.h>
-
-#include <cstdint>
-#include <cstdio>
-
-using namespace miosix;
-
-const uint8_t ADDRESS = 0x68 << 1;
-const uint8_t WHO_AM_I = 0x73;
-const uint8_t REG_WHO_AM_I = 117; // Register 117
-
-typedef ProtocolI2C<I2C1Driver> my_i2c1;
-
-typedef Gpio<GPIOB_BASE, 8> scl;
-typedef Gpio<GPIOB_BASE, 9> sda;
-
-using soft_i2c = SoftwareI2C<sda, scl>;
-
-void masterRead(uint8_t bit7_address, uint8_t reg_address, uint8_t *data,
- int len)
-{
- int i = 0;
- soft_i2c::sendStart();
- soft_i2c::send((bit7_address));
- soft_i2c::send(reg_address);
- soft_i2c::sendRepeatedStart();
- soft_i2c::send((bit7_address) + 1);
-
- for (i = 0; i < (len - 1); i++)
- data[i] = soft_i2c::recvWithAck();
-
- data[len - 1] = soft_i2c::recvWithNack();
-
- soft_i2c::sendStop();
-}
-
-int main()
-{
- // soft_i2c::init();
-
- my_i2c1::init();
-
- uint8_t who_am_i;
- for (;;)
- {
- long long s = miosix::getTick();
- my_i2c1::read(ADDRESS, REG_WHO_AM_I, &who_am_i, 1);
- long long d = miosix::getTick() - s;
-
- if (who_am_i == WHO_AM_I)
- {
- printf("Read ok. (%d)\n", (int)d);
- }
- else
- {
- printf("ERROR. read: %d\n", who_am_i);
- }
- Thread::sleep(1500);
- }
-}
diff --git a/old_examples/tests/drivers/test-imu-adis.cpp b/old_examples/tests/drivers/test-imu-adis.cpp
deleted file mode 100644
index 777c33d8f60da0d7f638fdaaf3ec229f54af6a4e..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-imu-adis.cpp
+++ /dev/null
@@ -1,89 +0,0 @@
-/* Copyright (c) 2018 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <diagnostic/CpuMeter.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/spi/SensorSpi.h>
-#include <interfaces-impl/hwmapping.h>
-#include <sensors/ADIS16405/ADIS16405.h>
-#include <sensors/SensorSampler.h>
-#include <utils/Stats/Stats.h>
-
-using namespace miosix;
-using namespace miosix::interfaces;
-
-// Reset pin
-typedef Gpio<GPIOD_BASE, 5> rstPin; // PD5 for the HomeoneBoard
-
-// SPI1 binding to the sensor
-typedef BusSPI<1, spi1::mosi, spi1::miso, spi1::sck> busSPI1; // Create SPI1
-typedef ProtocolSPI<busSPI1, miosix::sensors::adis16405::cs>
- spiADIS16405; // La lego al Chip Select 1 per la IMU 1
-
-int main()
-{
- spiADIS16405::init();
-
- Thread::sleep(1000);
- ADIS16405<spiADIS16405, rstPin>* adis =
- new ADIS16405<spiADIS16405, rstPin>(adis->GYRO_FS_300);
-
- if (adis->init())
- printf("[ADIS16405] Init succeeded\n");
- else
- printf("[ADIS16405] Init failed\n");
-
- if (adis->selfTest())
- printf("[ADIS16405] Self test succeeded\n");
- else
- printf("[ADIS16405] Self test failed\n");
-
- SimpleSensorSampler sampler(250, 1);
- sampler.addSensor(adis, std::bind([&]() {}));
-
- StatsResult statResult;
- Stats stats;
-
- int counter = 0;
-
- while (true)
- {
- sampler.sampleAndCallback();
-
- stats.add(averageCpuUtilization());
-
- if (counter == 2500)
- {
- statResult = stats.getStats();
- printf("CPU usage: %f\n", statResult.mean);
- counter = 0;
-
- const Vec3* last_data = adis->accelDataPtr();
- printf("%f %f %f\n", last_data->getX(), last_data->getY(),
- last_data->getZ());
- }
- counter++;
-
- Thread::sleep(100);
- }
-}
diff --git a/old_examples/tests/drivers/test-lsm.cpp b/old_examples/tests/drivers/test-lsm.cpp
deleted file mode 100644
index 6f0dbc430be8d67b25d945007e6c9519df8647b5..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-lsm.cpp
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Nuno Barcellos
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <Common.h>
-#include <diagnostic/CpuMeter.h>
-#include <drivers/BusTemplate.h>
-#include <drivers/spi/SensorSpi.h>
-#include <interfaces-impl/hwmapping.h>
-#include <sensors/LSM6DS3H/LSM6DS3H.h>
-#include <sensors/SensorSampler.h>
-#include <utils/Stats/Stats.h>
-
-using namespace miosix;
-using namespace miosix::interfaces;
-
-/* SPI1 binding to the sensor */
-typedef BusSPI<1, spi1::mosi, spi1::miso, spi1::sck> busSPI1;
-typedef ProtocolSPI<busSPI1, sensors::lsm6ds3h::cs> spiLSM6DS3H0_a;
-
-int main()
-{
- SimpleSensorSampler sampler(250, 1);
- spiLSM6DS3H0_a::init();
-
- LSM6DS3H<spiLSM6DS3H0_a>* lsm6ds3h = new LSM6DS3H<spiLSM6DS3H0_a>(3, 3);
-
- if (lsm6ds3h->init())
- {
- printf("[LSM6DS3H] Init succeeded\n");
- sampler.addSensor(lsm6ds3h, std::bind([&]() {}));
- }
- else
- {
- printf("[LSM6DS3H] Init failed\n");
-
- while (!lsm6ds3h->init())
- {
- printf("[LSM6DS3H] Init failed\n");
- Thread::sleep(1000);
- }
- }
-
- while (true)
- {
- sampler.sampleAndCallback();
-
- // const Vec3* last_data = lsm6ds3h->gyroDataPtr();
- // printf("%f %f %f\n", last_data->getX(), last_data->getY(),
- // last_data->getZ());
-
- const Vec3* last_data = lsm6ds3h->accelDataPtr();
- printf("%f %f %f\n", last_data->getX(), last_data->getY(),
- last_data->getZ());
-
- // const float* last_temp = lsm6ds3h->tempDataPtr();
- // printf("temp: %f\n", *last_temp);
-
- Thread::sleep(100);
- }
-}
diff --git a/old_examples/tests/drivers/test-piksi.cpp b/old_examples/tests/drivers/test-piksi.cpp
deleted file mode 100644
index a850afdf7e4ffaad156d80beece2cc11c4334775..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-piksi.cpp
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright (c) 2017 Skyward Experimental Rocketry
- * Author: Federico Terraneo
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/old_examples/piksi/piksi.h>
-#include <time.h>
-
-#include <iostream>
-using namespace std;
-
-#ifdef _MIOSIX
-
-#include <miosix.h>
-using namespace miosix;
-
-#endif //_MIOSIX
-
-// Polling test, usng getGpsData()
-
-int main()
-{
-#ifdef _MIOSIX
-
- Piksi piksi("/dev/gps");
-#else //_MIOSIX
- Piksi piksi("/dev/ttyUSB0");
-#endif //_MIOSIX
- for (;;)
- {
- Thread::sleep(200);
- try
- {
- auto gps = piksi.getGpsData();
-#ifdef _MIOSIX
- long long now = getTick();
-#else //_MIOSIX
- long long now = clock() / (CLOCKS_PER_SEC / 1000);
-#endif //_MIOSIX
- cout << " t: " << gps.timestamp << " lat: " << gps.latitude
- << " lon: " << gps.longitude << " h: " << gps.height
- << " vn: " << gps.velocityNorth << " ve: " << gps.velocityEast
- << " vd: " << gps.velocityDown << " ns: " << gps.numSatellites
- << " now: " << now;
- }
- catch (...)
- {
- cout << "---" << endl;
- }
- }
-}
-
-// Blocking wait test, using waitForGpsData()
-
-// int main()
-// {
-// #ifdef _MIOSIX
-// Piksi piksi("/dev/gps");
-// #else //_MIOSIX
-// Piksi piksi("/dev/ttyUSB0");
-// #endif //_MIOSIX
-//
-// for(;;)
-// {
-// auto gps=piksi.waitForGpsData();
-// #ifdef _MIOSIX
-// long long now=getTick();
-// #else //_MIOSIX
-// long long now=clock()/(CLOCKS_PER_SEC/1000);
-// #endif //_MIOSIX
-// cout<<" t: "<<now-gps.timestamp
-// <<" lat: "<<gps.latitude
-// <<" lon: "<<gps.longitude
-// <<" h: "<<gps.height
-// <<" vn: "<<gps.velocityNorth
-// <<" ve: "<<gps.velocityEast
-// <<" vd: "<<gps.velocityDown
-// <<" ns: "<<gps.numSatellites<<endl;
-// }
-// }
diff --git a/old_examples/tests/drivers/test-spi2.cpp b/old_examples/tests/drivers/test-spi2.cpp
deleted file mode 100644
index 95a32075ac9c0d3848f3a97d7a9f5bd3695c68c3..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-spi2.cpp
+++ /dev/null
@@ -1,44 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#include <drivers/BusTemplate.h>
-#include <interfaces-impl/hwmapping.h>
-
-using namespace miosix;
-using namespace interfaces;
-
-typedef BusSPI<2, spi2::mosi, spi2::miso, spi2::sck> busSPI2; // Creo la SPI2
-typedef ProtocolSPI<busSPI2, xbee::cs> pspi2;
-
-int main()
-{
- pspi2::init();
- Thread::sleep(200);
- for (;;)
- {
- pspi2::write(0x45);
- uint8_t r = pspi2::read(0xF6);
- printf("%d\n", r);
-
- Thread::sleep(500);
- }
-}
diff --git a/old_examples/tests/drivers/test-tempSensor.cpp b/old_examples/tests/drivers/test-tempSensor.cpp
deleted file mode 100644
index dda827a51484229a9a420b2b97a6478e0e63f81e..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-tempSensor.cpp
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Alessio Galluccio
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-#include <Common.h>
-#include <drivers/BusTemplate.h>
-#include <sensors/LM75B.h>
-
-using namespace miosix;
-
-#include <interfaces-impl/hwmapping.h>
-using I2CProtocol = ProtocolI2C<miosix::I2C1Driver>;
-
-uint8_t addr1 = 0x48 << 1;
-uint8_t addr2 = 0x49 << 1;
-
-typedef LM75B<I2CProtocol> LM75BType;
-int main()
-{
- LM75BType temp1{addr1};
- LM75BType temp2{addr2};
- Thread::sleep(500);
-
- while (true)
- {
- bool result1 = temp1.selfTest();
- bool result2 = temp2.selfTest();
-
- miosix::ledOn();
- TRACE("LM75B self test result: temp1=%d temp2=%d\n", result1, result2);
- Thread::sleep(500);
- miosix::ledOff();
- Thread::sleep(500);
- TRACE("LM75B (1) temperature: %f\n", temp1.getTemp());
- TRACE("LM75B (2) temperature: %f\n", temp2.getTemp());
- }
-}
diff --git a/old_examples/tests/drivers/test-unit-LM75B.cpp b/old_examples/tests/drivers/test-unit-LM75B.cpp
deleted file mode 100644
index 01b7efb14f93ef220d202fdf4afa9eaba825ab6a..0000000000000000000000000000000000000000
--- a/old_examples/tests/drivers/test-unit-LM75B.cpp
+++ /dev/null
@@ -1,79 +0,0 @@
-/* Copyright (c) 2019 Skyward Experimental Rocketry
- * Author: Luca Erbetta
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- */
-
-#define private public
-
-#ifdef STANDALONE_CATCH1_TEST
-#include "catch-tests-entry.cpp"
-#endif
-
-#include <Common.h>
-#include <sensors/LM75B.h>
-
-#include <catch2/catch.hpp>
-
-using namespace miosix;
-
-#include <interfaces-impl/hwmapping.h>
-using I2CProtocol = ProtocolI2C<miosix::I2C1Driver>;
-typedef LM75B<I2CProtocol> LM75BType;
-
-// TODO sistemare la codifica di {0x80, 0x00}, che
-// per qualche ragione, diventa positiva
-TEST_CASE("[LM75B] temperature")
-{
- uint8_t addr1 = 0x48 << 1;
- LM75BType temp1{addr1};
-
- SECTION("[LM75B] positive temperature")
- {
- uint8_t temp_array[2] = {0x10, 0x10};
- REQUIRE(temp1.computeTemp(temp_array) == Approx(16.0).epsilon(0.001));
- }
-
- SECTION("[LM75B] negative temperature")
- {
- uint8_t temp_array[2] = {0x80, 0x10};
- REQUIRE(temp1.computeTemp(temp_array) ==
- Approx(-127.875).epsilon(0.001));
- }
-
- SECTION("[LM75B] zero temperature")
- {
- uint8_t temp_array[2] = {0x00, 0x00};
- REQUIRE(temp1.computeTemp(temp_array) == Approx(0).epsilon(0.001));
- }
-
- SECTION("[LM75B] max temperature")
- {
- uint8_t temp_array[2] = {0x7F, 0xFF};
- REQUIRE(temp1.computeTemp(temp_array) ==
- Approx(127.875).epsilon(0.001));
- }
-
- SECTION("[LM75B] min temperature")
- {
- uint8_t temp_array[2] = {0x80, 0x01};
- REQUIRE(temp1.computeTemp(temp_array) ==
- Approx(-127.875).epsilon(0.001));
- }
-}