diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
index 29c0603ee17c9ec5eb03119e3f123d83cc047e5d..1d0c2567aa833033afbf6c76545acce9bd472060 100644
--- a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
+++ b/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
@@ -98,21 +98,35 @@
This value must be a multiple of 0x200. */
/******************************************************************************/
-// By Alberto Nidasio -- begin
+// By Alberto Nidasio and TFT -- begin
+#if (HSE_VALUE % 2000000) == 0
-// Divide the input clock
-#define PLL_M (HSE_VALUE/1000000)
+//PLL input frequency set to 2MHz to reduce jitter as suggested by the datasheet.
+const unsigned int PLL_M=HSE_VALUE/2000000;
+#ifdef SYSCLK_FREQ_216MHz
+const unsigned int PLL_Q=9;
+const unsigned int PLL_R=7;
+const unsigned int PLL_N=216;
+const unsigned int PLL_P=2;
+#else
+#error Clock not selected
+#endif
+
+#else // HSE_VALUE not divisible by 2MHz
+//PLL Input frequency set to 1MHz
+const unsigned int PLL_M=HSE_VALUE/1000000;
#ifdef SYSCLK_FREQ_216MHz
-#define PLL_Q 9
-#define PLL_R 7
-#define PLL_N 432
-#define PLL_P 2
+const unsigned int PLL_Q=9;
+const unsigned int PLL_R=7;
+const unsigned int PLL_N=432;
+const unsigned int PLL_P=2;
#else
#error Clock not selected
#endif
-// By Alberto Nidasio -- end
+#endif // HSE_VALUE divisibility check
+// By Alberto Nidasio and TFT -- end
/**
* @}
@@ -253,7 +267,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllSource = 0, pllm = 2;
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
@@ -271,10 +285,10 @@ void SystemCoreClockUpdate(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
- pllSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- if (pllSource != 0)
+ if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
@@ -302,7 +316,7 @@ void SystemCoreClockUpdate(void)
//By TFT: added PLL initialization that was not present in the CMSIS code
void SetSysClk(void)
{
- register uint32_t tmpReg = 0, timeout = 0xFFFF;
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
@@ -320,8 +334,8 @@ void SetSysClk(void)
/* Wait till HSE is ready and if Time out is reached exit */
do
{
- tmpReg = RCC->CR & RCC_CR_HSERDY;
- } while((tmpReg != RCC_CR_HSERDY) && (timeout-- > 0));
+ tmpreg = RCC->CR & RCC_CR_HSERDY;
+ } while((tmpreg != RCC_CR_HSERDY) && (timeout-- > 0));
if(timeout != 0)
{
@@ -337,8 +351,8 @@ void SetSysClk(void)
/* Wait till ODR is ready and if Time out is reached exit */
do
{
- tmpReg = PWR->CSR1 & PWR_CSR1_ODRDY;
- } while((tmpReg != PWR_CSR1_ODRDY) && (timeout-- > 0));
+ tmpreg = PWR->CSR1 & PWR_CSR1_ODRDY;
+ } while((tmpreg != PWR_CSR1_ODRDY) && (timeout-- > 0));
/* Enable ODSW */
PWR->CR1 |= 0x00020000;
@@ -346,8 +360,8 @@ void SetSysClk(void)
/* Wait till ODR is ready and if Time out is reached exit */
do
{
- tmpReg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
- } while((tmpReg != PWR_CSR1_ODSWRDY) && (timeout-- > 0));
+ tmpreg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
+ } while((tmpreg != PWR_CSR1_ODSWRDY) && (timeout-- > 0));
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
@@ -369,8 +383,8 @@ void SetSysClk(void)
timeout = 0xFFFF;
do
{
- tmpReg = (RCC->CR & RCC_CR_PLLRDY);
- } while((tmpReg != RCC_CR_PLLRDY) && (timeout-- > 0));
+ tmpreg = (RCC->CR & RCC_CR_PLLRDY);
+ } while((tmpreg != RCC_CR_PLLRDY) && (timeout-- > 0));
if(timeout != 0)
{
@@ -384,8 +398,8 @@ void SetSysClk(void)
timeout = 0xFFFF;
do
{
- tmpReg = (RCC->CFGR & RCC_CFGR_SWS);
- } while((tmpReg != RCC_CFGR_SWS) && (timeout-- > 0));
+ tmpreg = (RCC->CFGR & RCC_CFGR_SWS);
+ } while((tmpreg != RCC_CFGR_SWS) && (timeout-- > 0));
}
}
diff --git a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
index 68ed3b127501e875a1ed54fb6a22561f54e50092..84de925323215b7f22475174c0f16e38a0a14695 100644
--- a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
+++ b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
@@ -40,10 +40,10 @@
//Note: enabling debugging might cause deadlock when using sleep() or reboot()
//The bug won't be fixed because debugging is only useful for driver development
///\internal Debug macro, for normal conditions
-// #define DBG iprintf
+//#define DBG iprintf
#define DBG(x,...) do {} while(0)
///\internal Debug macro, for errors only
-// #define DBGERR iprintf
+//#define DBGERR iprintf
#define DBGERR(x,...) do {} while(0)
/*
@@ -52,16 +52,16 @@
*/
#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
-#if defined(__SDMMC1)
+#if SD_SDMMC==1
#define SDIO SDMMC1
#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC1EN
#define SDIO_IRQn SDMMC1_IRQn
-#elif defined(__SDMMC2)
-#define SDIO SDMMC2
+#elif SD_SDMMC==2
+#define SDIO SDMMC2
#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC2EN
#define SDIO_IRQn SDMMC2_IRQn
#else
-#warning This error is a reminder that you have not selected between SDMMC1 and SDMMC2 in Makefile.int
+#error SD_SDMMC undefined or not in range
#endif
#define SDIO_STA_STBITERR 0 //This bit has been removed
@@ -100,9 +100,15 @@
#define SDIO_POWER_PWRCTRL_1 SDMMC_POWER_PWRCTRL_1
#define SDIO_POWER_PWRCTRL_0 SDMMC_POWER_PWRCTRL_0
+constexpr int ICR_FLAGS_CLR=0x5ff;
+
+#else //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+
+constexpr int ICR_FLAGS_CLR=0x7ff;
+
#endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
#define DMA_Stream DMA2_Stream0
#else
#define DMA_Stream DMA2_Stream3
@@ -112,7 +118,7 @@
* \internal
* DMA2 Stream interrupt handler
*/
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
void __attribute__((naked)) DMA2_Stream0_IRQHandler()
#else
void __attribute__((naked)) DMA2_Stream3_IRQHandler()
@@ -127,9 +133,9 @@ void __attribute__((naked)) DMA2_Stream3_IRQHandler()
* \internal
* SDIO interrupt handler
*/
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC1)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==1
void __attribute__((naked)) SDMMC1_IRQHandler()
-#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
void __attribute__((naked)) SDMMC2_IRQHandler()
#else //stm32f2 and stm32f4
void __attribute__((naked)) SDIO_IRQHandler()
@@ -154,28 +160,28 @@ static unsigned int sdioFlags; ///< \internal SDIO status flags
void __attribute__((used)) SDDMAirqImpl()
{
dmaFlags=DMA2->LISR;
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
- if (dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
- transferError = true;
-
- DMA2->LIFCR = DMA_LIFCR_CTCIF0 |
- DMA_LIFCR_CTEIF0 |
- DMA_LIFCR_CDMEIF0 |
- DMA_LIFCR_CFEIF0;
-#else
- if (dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
- transferError = true;
+ #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+ if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
+ transferError=true;
- DMA2->LIFCR = DMA_LIFCR_CTCIF3 |
- DMA_LIFCR_CTEIF3 |
- DMA_LIFCR_CDMEIF3 |
- DMA_LIFCR_CFEIF3;
-#endif
+ DMA2->LIFCR = DMA_LIFCR_CTCIF0
+ | DMA_LIFCR_CTEIF0
+ | DMA_LIFCR_CDMEIF0
+ | DMA_LIFCR_CFEIF0;
+ #else
+ if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
+ transferError=true;
+
+ DMA2->LIFCR = DMA_LIFCR_CTCIF3
+ | DMA_LIFCR_CTEIF3
+ | DMA_LIFCR_CDMEIF3
+ | DMA_LIFCR_CFEIF3;
+ #endif
if(!waiting) return;
waiting->IRQwakeup();
- if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority())
- Scheduler::IRQfindNextThread();
+ if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority())
+ Scheduler::IRQfindNextThread();
waiting=0;
}
@@ -190,12 +196,12 @@ void __attribute__((used)) SDirqImpl()
SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL))
transferError=true;
- SDIO->ICR=0x7ff;//Clear flags
+ SDIO->ICR=ICR_FLAGS_CLR; //Clear flags
if(!waiting) return;
waiting->IRQwakeup();
- if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority())
- Scheduler::IRQfindNextThread();
+ if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority())
+ Scheduler::IRQfindNextThread();
waiting=0;
}
@@ -224,20 +230,20 @@ enum CardType
static CardType cardType=Invalid;
//SD card GPIOs
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
-typedef Gpio<GPIOG_BASE, 9> sdD0;
-typedef Gpio<GPIOG_BASE, 10> sdD1;
-typedef Gpio<GPIOB_BASE, 3> sdD2;
-typedef Gpio<GPIOB_BASE, 4> sdD3;
-typedef Gpio<GPIOD_BASE, 6> sdCLK;
-typedef Gpio<GPIOD_BASE, 7> sdCMD;
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+typedef Gpio<GPIOG_BASE,9> sdD0;
+typedef Gpio<GPIOG_BASE,10> sdD1;
+typedef Gpio<GPIOB_BASE,3> sdD2;
+typedef Gpio<GPIOB_BASE,4> sdD3;
+typedef Gpio<GPIOD_BASE,6> sdCLK;
+typedef Gpio<GPIOD_BASE,7> sdCMD;
#else
-typedef Gpio<GPIOC_BASE, 8> sdD0;
-typedef Gpio<GPIOC_BASE, 9> sdD1;
-typedef Gpio<GPIOC_BASE, 10> sdD2;
-typedef Gpio<GPIOC_BASE, 11> sdD3;
-typedef Gpio<GPIOC_BASE, 12> sdCLK;
-typedef Gpio<GPIOD_BASE, 2> sdCMD;
+typedef Gpio<GPIOC_BASE,8> sdD0;
+typedef Gpio<GPIOC_BASE,9> sdD1;
+typedef Gpio<GPIOC_BASE,10> sdD2;
+typedef Gpio<GPIOC_BASE,11> sdD3;
+typedef Gpio<GPIOC_BASE,12> sdCLK;
+typedef Gpio<GPIOD_BASE,2> sdCMD;
#endif
@@ -672,12 +678,12 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
{
if(SDIO->STA & SDIO_STA_CMDSENT)
{
- SDIO->ICR=0x7ff;//Clear flags
+ SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
return CmdResult(cc,CmdResult::Ok);
}
delayUs(1);
}
- SDIO->ICR=0x7ff;//Clear flags
+ SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
return CmdResult(cc,CmdResult::Timeout);
}
@@ -687,7 +693,7 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
unsigned int status=SDIO->STA;
if(status & SDIO_STA_CMDREND)
{
- SDIO->ICR=0x7ff;//Clear flags
+ SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok);
else return CmdResult(cc,CmdResult::RespNotMatch);
}
@@ -925,12 +931,21 @@ static void displayBlockTransferError()
static unsigned int dmaTransferCommonSetup(const unsigned char *buffer)
{
//Clear both SDIO and DMA interrupt flags
- SDIO->ICR=0x4005ff;
- DMA2->LIFCR=0xffffffff;
+ SDIO->ICR=ICR_FLAGS_CLR;
+ #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+ DMA2->LIFCR = DMA_LIFCR_CTCIF0
+ | DMA_LIFCR_CTEIF0
+ | DMA_LIFCR_CDMEIF0
+ | DMA_LIFCR_CFEIF0;
+ #else
+ DMA2->LIFCR = DMA_LIFCR_CTCIF3
+ | DMA_LIFCR_CTEIF3
+ | DMA_LIFCR_CDMEIF3
+ | DMA_LIFCR_CFEIF3;
+ #endif
transferError=false;
- dmaFlags=0;
- sdioFlags=0;
+ dmaFlags=sdioFlags=0;
waiting=Thread::getCurrentThread();
//Select DMA transfer size based on buffer alignment. Best performance
@@ -976,28 +991,28 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout
- DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
- DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
- //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
- DMA_Stream->FCR=DMA_SxFCR_FEIE | //Interrupt on fifo error
- DMA_SxFCR_DMDIS | //Fifo enabled
- DMA_SxFCR_FTH_0; //Take action if fifo half full
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
- DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
-#else
- DMA_Stream->CR = DMA_SxCR_CHSEL_2 | // Channel 4 (SDIO)
-#endif
- DMA_SxCR_PBURST_0 | //4-beat bursts read from SDIO
- DMA_SxCR_PL_0 | //Medium priority DMA stream
- memoryTransferSize | //RAM data size depends on alignment
- DMA_SxCR_PSIZE_1 | //Read 32bit at a time from SDIO
- DMA_SxCR_MINC | //Increment RAM pointer
- 0 | //Peripheral to memory direction
- DMA_SxCR_PFCTRL | //Peripheral is flow controller
- DMA_SxCR_TCIE | //Interrupt on transfer complete
- DMA_SxCR_TEIE | //Interrupt on transfer error
- DMA_SxCR_DMEIE | //Interrupt on direct mode error
- DMA_SxCR_EN; //Start the DMA
+ DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+ DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+ //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
+ DMA_Stream->FCR = DMA_SxFCR_FEIE //Interrupt on fifo error
+ | DMA_SxFCR_DMDIS //Fifo enabled
+ | DMA_SxFCR_FTH_0; //Take action if fifo half full
+ #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+ DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO)
+ #else
+ DMA_Stream->CR = DMA_SxCR_CHSEL_2 //Channel 4 (SDIO)
+ #endif
+ | DMA_SxCR_PBURST_0 //4-beat bursts read from SDIO
+ | DMA_SxCR_PL_0 //Medium priority DMA stream
+ | memoryTransferSize //RAM data size depends on alignment
+ | DMA_SxCR_PSIZE_1 //Read 32bit at a time from SDIO
+ | DMA_SxCR_MINC //Increment RAM pointer
+ | 0 //Peripheral to memory direction
+ | DMA_SxCR_PFCTRL //Peripheral is flow controller
+ | DMA_SxCR_TCIE //Interrupt on transfer complete
+ | DMA_SxCR_TEIE //Interrupt on transfer error
+ | DMA_SxCR_DMEIE //Interrupt on direct mode error
+ | DMA_SxCR_EN; //Start the DMA
SDIO->DLEN=nblk*512;
if(waiting==0)
@@ -1083,30 +1098,30 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout
- DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
- DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
- //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
+ DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+ DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+ //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
//Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate
//a spurious fifo error. The code was tested and the transfer completes
//successfully even in the presence of this fifo error
- DMA_Stream->FCR=DMA_SxFCR_DMDIS | //Fifo enabled
- DMA_SxFCR_FTH_1 | //Take action if fifo full
- DMA_SxFCR_FTH_0;
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
- DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
+ DMA_Stream->FCR = DMA_SxFCR_DMDIS //Fifo enabled
+ | DMA_SxFCR_FTH_1 //Take action if fifo full
+ | DMA_SxFCR_FTH_0;
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
+ DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO)
#else
- DMA_Stream->CR = DMA_SxCR_CHSEL_2 | // Channel 4 (SDIO)
+ DMA_Stream->CR = DMA_SxCR_CHSEL_2 // Channel 4 (SDIO)
#endif
- DMA_SxCR_PBURST_0 | //4-beat bursts write to SDIO
- DMA_SxCR_PL_0 | //Medium priority DMA stream
- memoryTransferSize | //RAM data size depends on alignment
- DMA_SxCR_PSIZE_1 | //Write 32bit at a time to SDIO
- DMA_SxCR_MINC | //Increment RAM pointer
- DMA_SxCR_DIR_0 | //Memory to peripheral direction
- DMA_SxCR_PFCTRL | //Peripheral is flow controller
- DMA_SxCR_TEIE | //Interrupt on transfer error
- DMA_SxCR_DMEIE | //Interrupt on direct mode error
- DMA_SxCR_EN; //Start the DMA
+ | DMA_SxCR_PBURST_0 //4-beat bursts write to SDIO
+ | DMA_SxCR_PL_0 //Medium priority DMA stream
+ | memoryTransferSize //RAM data size depends on alignment
+ | DMA_SxCR_PSIZE_1 //Write 32bit at a time to SDIO
+ | DMA_SxCR_MINC //Increment RAM pointer
+ | DMA_SxCR_DIR_0 //Memory to peripheral direction
+ | DMA_SxCR_PFCTRL //Peripheral is flow controller
+ | DMA_SxCR_TEIE //Interrupt on transfer error
+ | DMA_SxCR_DMEIE //Interrupt on direct mode error
+ | DMA_SxCR_EN; //Start the DMA
SDIO->DLEN=nblk*512;
if(waiting==0)
@@ -1208,46 +1223,46 @@ static void initSDIOPeripheral()
RCC_SYNC();
RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
RCC_SYNC();
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+ #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
sdD0::mode(Mode::ALTERNATE);
sdD0::alternateFunction(11);
-#ifndef SD_ONE_BIT_DATABUS
+ #ifndef SD_ONE_BIT_DATABUS
sdD1::mode(Mode::ALTERNATE);
sdD1::alternateFunction(11);
sdD2::mode(Mode::ALTERNATE);
sdD2::alternateFunction(10);
sdD3::mode(Mode::ALTERNATE);
sdD3::alternateFunction(10);
-#endif // SD_ONE_BIT_DATABUS
+ #endif // SD_ONE_BIT_DATABUS
sdCLK::mode(Mode::ALTERNATE);
sdCLK::alternateFunction(11);
sdCMD::mode(Mode::ALTERNATE);
sdCMD::alternateFunction(11);
-#else
+ #else
sdD0::mode(Mode::ALTERNATE);
sdD0::alternateFunction(12);
-#ifndef SD_ONE_BIT_DATABUS
+ #ifndef SD_ONE_BIT_DATABUS
sdD1::mode(Mode::ALTERNATE);
sdD1::alternateFunction(12);
sdD2::mode(Mode::ALTERNATE);
sdD2::alternateFunction(12);
sdD3::mode(Mode::ALTERNATE);
sdD3::alternateFunction(12);
-#endif // SD_ONE_BIT_DATABUS
+ #endif // SD_ONE_BIT_DATABUS
sdCLK::mode(Mode::ALTERNATE);
sdCLK::alternateFunction(12);
sdCMD::mode(Mode::ALTERNATE);
sdCMD::alternateFunction(12);
-#endif
+ #endif
}
-#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+ #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
-#else
+ #else
NVIC_SetPriority(DMA2_Stream3_IRQn,15);//Low priority for DMA
NVIC_EnableIRQ(DMA2_Stream3_IRQn);
-#endif
+ #endif
NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO
NVIC_EnableIRQ(SDIO_IRQn);
@@ -1256,7 +1271,11 @@ static void initSDIOPeripheral()
SDIO->CLKCR=0;
SDIO->CMD=0;
SDIO->DCTRL=0;
+ #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+ SDIO->ICR=0x4005ff;
+ #else
SDIO->ICR=0xc007ff;
+ #endif
SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state
//This delay is particularly important: when setting the POWER register a
//glitch on the CMD pin happens. This glitch has a fast fall time and a slow
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp
index 562d41a9d21282b392d36005e17a95f36360fa50..21064c4c6e8a91d4d05dc8c3e9c7f28299f6dc0b 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp
@@ -21,11 +21,26 @@
* Never returns.
*/
void program_startup() __attribute__((noreturn));
-void program_startup() {
- // Cortex M7 core appears to get out of reset with interrupts already
- // enabled
+void program_startup()
+{
+ //Cortex M7 core appears to get out of reset with interrupts already enabled
__disable_irq();
+ /**
+ * SystemInit() is called *before* initializing .data and zeroing .bss
+ * Despite all startup files provided by ST do the opposite, there are three
+ * good reasons to do so:
+ * 1. First, the CMSIS specifications say that SystemInit() must not access
+ * global variables, so it is actually possible to call it before
+ * 2. Second, when running Miosix with the xram linker scripts .data and
+ * .bss are placed in the external RAM, so we *must* call SystemInit(),
+ * which enables xram, before touching .data and .bss
+ * 3. Third, this is a performance improvement since the loops that
+ * initialize .data and zeros .bss now run with the CPU at full speed
+ * instead of 8MHz
+ */
+ SystemInit();
+
miosix::IRQconfigureCache();
// These are defined in the linker script
@@ -36,43 +51,28 @@ void program_startup() {
extern unsigned char _bss_end asm("_bss_end");
// Initialize .data section, clear .bss section
- unsigned char *etext = &_etext;
- unsigned char *data = &_data;
- unsigned char *edata = &_edata;
- unsigned char *bss_start = &_bss_start;
- unsigned char *bss_end = &_bss_end;
- memcpy(data, etext, edata - data);
- memset(bss_start, 0, bss_end - bss_start);
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ memcpy(data, etext, edata-data);
+ memset(bss_start, 0, bss_end-bss_start);
// Move on to stage 2
_init();
// If main returns, reboot
NVIC_SystemReset();
- for (;;)
- ;
+ for(;;) ;
}
/**
* Reset handler, called by hardware immediately after reset
*/
void Reset_Handler() __attribute__((__interrupt__, noreturn));
-void Reset_Handler() {
- /**
- * SystemInit() is called *before* initializing .data and zeroing .bss
- * Despite all startup files provided by ST do the opposite, there are three
- * good reasons to do so:
- * 1. First, the CMSIS specifications say that SystemInit() must not access
- * global variables, so it is actually possible to call it before
- * 2. Second, when running Miosix with the xram linker scripts .data and
- * .bss are placed in the external RAM, so we *must* call SystemInit(),
- * which enables xram, before touching .data and .bss
- * 3. Third, this is a performance improvement since the loops that
- * initialize .data and zeros .bss now run with the CPU at full speed
- * instead of 8MHz
- */
- SystemInit();
-
+void Reset_Handler()
+{
/*
* Load into the program stack pointer the heap end address and switch from
* the msp to sps.
@@ -86,8 +86,7 @@ void Reset_Handler() {
"msr psp, r0 \n\t"
"movw r0, #2 \n\n" // Set the control register to use
"msr control, r0 \n\t" // the process stack
- "isb \n\t" ::
- : "r0");
+ "isb \n\t":::"r0");
program_startup();
}
@@ -227,7 +226,8 @@ extern char _main_stack_top asm("_main_stack_top");
// Interrupt vectors, must be placed @ address 0x00000000
// The extern declaration is required otherwise g++ optimizes it out
extern void (*const __Vectors[])();
-void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = {
+void (*const __Vectors[])() __attribute__((section(".isr_vector"))) =
+{
reinterpret_cast<void (*)()>(&_main_stack_top), /* Stack pointer*/
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
index 288dab6f34f69a56be30fbdee6c8a7b0a0da88e1..af0ba546e2535096cb2e382afdebf0e78985b9b9 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
@@ -57,7 +57,8 @@ namespace miosix {
// Initialization
//
-void IRQbspInit() {
+void IRQbspInit()
+{
// Enable all gpios
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
@@ -82,42 +83,42 @@ void IRQbspInit() {
ledOn();
delayMs(100);
ledOff();
- auto tx = Gpio<GPIOD_BASE, 8>::getPin();
- tx.alternateFunction(7);
- auto rx = Gpio<GPIOD_BASE, 9>::getPin();
- rx.alternateFunction(7);
+ auto tx=Gpio<GPIOD_BASE,8>::getPin(); tx.alternateFunction(7);
+ auto rx=Gpio<GPIOD_BASE,9>::getPin(); rx.alternateFunction(7);
DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>(
new STM32Serial(3, defaultSerialSpeed, tx, rx)));
}
-void bspInit2() {
-#ifdef WITH_FILESYSTEM
+void bspInit2()
+{
+ #ifdef WITH_FILESYSTEM
basicFilesystemSetup(SDIODriver::instance());
-#endif // WITH_FILESYSTEM
+ #endif //WITH_FILESYSTEM
}
//
// Shutdown and reboot
//
-void shutdown() {
- ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
+void shutdown()
+{
+ ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
-#ifdef WITH_FILESYSTEM
+ #ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
-#endif // WITH_FILESYSTEM
+ #endif //WITH_FILESYSTEM
disableInterrupts();
- for (;;)
- ;
+ for(;;) ;
}
-void reboot() {
- ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
+void reboot()
+{
+ ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
-#ifdef WITH_FILESYSTEM
+ #ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
-#endif // WITH_FILESYSTEM
+ #endif //WITH_FILESYSTEM
disableInterrupts();
miosix_private::IRQsystemReboot();
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h
index 41b83218a1a26e4ab8a4aee9f4f43a6a576bf3fd..2a063b99a2d5fee1438f5c925eaae46348e121e1 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h
@@ -47,18 +47,20 @@ namespace miosix {
* \internal
* Board pin definition
*/
-typedef Gpio<GPIOB_BASE, 0> userLed1;
-typedef Gpio<GPIOB_BASE, 7> userLed2;
-typedef Gpio<GPIOB_BASE, 14> userLed3;
-typedef Gpio<GPIOC_BASE, 13> userBtn;
+typedef Gpio<GPIOB_BASE,0> userLed1;
+typedef Gpio<GPIOB_BASE,7> userLed2;
+typedef Gpio<GPIOB_BASE,14> userLed3;
+typedef Gpio<GPIOC_BASE,13> userBtn;
-inline void ledOn() {
+inline void ledOn()
+{
userLed1::high();
userLed2::high();
userLed3::high();
}
-inline void ledOff() {
+inline void ledOff()
+{
userLed1::low();
userLed2::low();
userLed3::low();
@@ -94,4 +96,4 @@ inline bool sdCardSense() { return true; }
} // namespace miosix
-#endif // BSP_IMPL_H
+#endif //BSP_IMPL_H
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
index 2477e0e9904b875d479a8ae3dba65a520c0ada72..2f196bf6bd119712fe9da7fb081b557d25dda76f 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
@@ -21,7 +21,8 @@
* Never returns.
*/
void program_startup() __attribute__((noreturn));
-void program_startup() {
+void program_startup()
+{
// Cortex M7 core appears to get out of reset with interrupts already
// enabled
__disable_irq();
@@ -36,28 +37,28 @@ void program_startup() {
extern unsigned char _bss_end asm("_bss_end");
// Initialize .data section, clear .bss section
- unsigned char *etext = &_etext;
- unsigned char *data = &_data;
- unsigned char *edata = &_edata;
- unsigned char *bss_start = &_bss_start;
- unsigned char *bss_end = &_bss_end;
- memcpy(data, etext, edata - data);
- memset(bss_start, 0, bss_end - bss_start);
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ memcpy(data, etext, edata-data);
+ memset(bss_start, 0, bss_end-bss_start);
// Move on to stage 2
_init();
// If main returns, reboot
NVIC_SystemReset();
- for (;;)
- ;
+ for(;;) ;
}
/**
* Reset handler, called by hardware immediately after reset
*/
void Reset_Handler() __attribute__((__interrupt__, noreturn));
-void Reset_Handler() {
+void Reset_Handler()
+{
/**
* SystemInit() is called *before* initializing .data and zeroing .bss
* Despite all startup files provided by ST do the opposite, there are three
@@ -78,9 +79,9 @@ void Reset_Handler() {
* Put after SystemInit() as SDRAM is timing-sensitive and needs the full
* clock speed.
*/
-#ifdef __ENABLE_XRAM
+ #ifdef __ENABLE_XRAM
miosix::configureSdram();
-#endif //__ENABLE_XRAM
+ #endif //__ENABLE_XRAM
/*
* Load into the program stack pointer the heap end address and switch from
@@ -95,8 +96,7 @@ void Reset_Handler() {
"msr psp, r0 \n\t"
"movw r0, #2 \n\n" // Set the control register to use
"msr control, r0 \n\t" // the process stack
- "isb \n\t" ::
- : "r0");
+ "isb \n\t":::"r0");
program_startup();
}
@@ -236,7 +236,8 @@ extern char _main_stack_top asm("_main_stack_top");
// Interrupt vectors, must be placed @ address 0x00000000
// The extern declaration is required otherwise g++ optimizes it out
extern void (*const __Vectors[])();
-void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = {
+void (*const __Vectors[])() __attribute__((section(".isr_vector"))) =
+{
reinterpret_cast<void (*)()>(&_main_stack_top), /* Stack pointer*/
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
index 77e58cdf73643dbf401399044f43060d972e32a3..51fe420bade283f539eb6ced7031b0226ff1e282 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
@@ -57,13 +57,15 @@ namespace miosix {
// Initialization
//
-static void sdramCommandWait() {
- for (int i = 0; i < 0xffff; i++)
- if ((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) == 0)
+static void sdramCommandWait()
+{
+ for(int i=0;i<0xffff;i++)
+ if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0)
return;
}
-void configureSdram() {
+void configureSdram()
+{
// Enable all gpios, passing clock
RCC->AHB1ENR |=
RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN |
@@ -177,34 +179,34 @@ void configureSdram() {
// HCLK = 216MHz -> SDRAM clock = HCLK/2 = 133MHz
// 1. Memory device features
- FMC_Bank5_6->SDCR[0] = 0 // 0 delay after CAS latency
- | FMC_SDCR1_RBURST // Enable read bursts
- | FMC_SDCR1_SDCLK_1 // SDCLK = HCLK / 2
- | 0 // Write accesses allowed
- | FMC_SDCR1_CAS_1 // 2 cycles CAS latency
- | FMC_SDCR1_NB // 4 internal banks
- | FMC_SDCR1_MWID_1 // 32 bit data bus
- | FMC_SDCR1_NR_0 // 12 bit row address
- | 0; // 8 bit column address
+ FMC_Bank5_6->SDCR[0] = 0 // 0 delay after CAS latency
+ | FMC_SDCR1_RBURST // Enable read bursts
+ | FMC_SDCR1_SDCLK_1 // SDCLK = HCLK / 2
+ | 0 // Write accesses allowed
+ | FMC_SDCR1_CAS_1 // 2 cycles CAS latency
+ | FMC_SDCR1_NB // 4 internal banks
+ | FMC_SDCR1_MWID_1 // 32 bit data bus
+ | FMC_SDCR1_NR_0 // 12 bit row address
+ | 0; // 8 bit column address
// 2. Memory device timings
-#ifdef SYSCLK_FREQ_216MHz
+ #ifdef SYSCLK_FREQ_216MHz
// SDRAM timings. One clock cycle is 9.26ns
FMC_Bank5_6->SDTR[0] =
- (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns)
+ (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns)
| (2 - 1) << FMC_SDTR1_TRP_Pos // 2 cycles TRP (18.52ns > 18ns)
| (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (18.52ns > 12ns)
| (7 - 1) << FMC_SDTR1_TRC_Pos // 7 cycles TRC (64.82ns > 60ns)
| (5 - 1) << FMC_SDTR1_TRAS_Pos // 5 cycles TRAS (46.3ns > 42ns)
| (8 - 1) << FMC_SDTR1_TXSR_Pos // 8 cycles TXSR (74.08ns > 70ns)
| (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (18.52ns > 12ns)
-#else
-#error No SDRAM timings for this clock
-#endif
+ #else
+ #error No SDRAM timings for this clock
+ #endif
// 3. Enable the bank 1 clock
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_0 // Clock Configuration Enable
- | FMC_SDCMR_CTB1; // Bank 1
+ | FMC_SDCMR_CTB1; // Bank 1
sdramCommandWait();
// 4. Wait during command execution
@@ -212,41 +214,42 @@ void configureSdram() {
// 5. Issue a "Precharge All" command
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 // Precharge all
- | FMC_SDCMR_CTB1; // Bank 1
+ | FMC_SDCMR_CTB1; // Bank 1
sdramCommandWait();
// 6. Issue Auto-Refresh commands
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 | FMC_SDCMR_MODE_0 // Auto-Refresh
- | FMC_SDCMR_CTB1 // Bank 1
- | (8 - 1) << FMC_SDCMR_NRFS_Pos; // 2 Auto-Refresh
+ | FMC_SDCMR_CTB1 // Bank 1
+ | (8 - 1) << FMC_SDCMR_NRFS_Pos; // 2 Auto-Refresh
sdramCommandWait();
// 7. Issue a Load Mode Register command
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_2 /// Load mode register
- | FMC_SDCMR_CTB1 // Bank 1
- | 0x220 << FMC_SDCMR_MRD_Pos; // CAS = 2, burst = 1
+ | FMC_SDCMR_CTB1 // Bank 1
+ | 0x220 << FMC_SDCMR_MRD_Pos; // CAS = 2, burst = 1
sdramCommandWait();
// 8. Program the refresh rate (4K / 64ms)
// 64ms / 4096 = 15.625us
-#ifdef SYSCLK_FREQ_216MHz
+ #ifdef SYSCLK_FREQ_216MHz
// 15.625us * 108MHz = 1687 - 20 = 1667
FMC_Bank5_6->SDRTR = 1667 << FMC_SDRTR_COUNT_Pos;
-#else
-#error No SDRAM refresh timings for this clock
-#endif
+ #else
+ #error No SDRAM refresh timings for this clock
+ #endif
}
-void IRQbspInit() {
-// If using SDRAM GPIOs are enabled by configureSdram(), else enable them here
-#ifndef __ENABLE_XRAM
+void IRQbspInit()
+{
+ //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here
+ #ifndef __ENABLE_XRAM
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN |
RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN;
RCC_SYNC();
-#endif //__ENABLE_XRAM
+ #endif //__ENABLE_XRAM
userLed1::mode(Mode::OUTPUT);
userLed2::mode(Mode::OUTPUT);
@@ -262,34 +265,36 @@ void IRQbspInit() {
defaultSerial, defaultSerialSpeed, STM32Serial::NOFLOWCTRL)));
}
-void bspInit2() {
-#ifdef WITH_FILESYSTEM
+void bspInit2()
+{
+ #ifdef WITH_FILESYSTEM
basicFilesystemSetup(SDIODriver::instance());
-#endif // WITH_FILESYSTEM
+ #endif // WITH_FILESYSTEM
}
//
// Shutdown and reboot
//
-void shutdown() {
+void shutdown()
+{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
-#ifdef WITH_FILESYSTEM
+ #ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
-#endif // WITH_FILESYSTEM
+ #endif // WITH_FILESYSTEM
disableInterrupts();
- for (;;)
- ;
+ for(;;) ;
}
-void reboot() {
+void reboot()
+{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
-#ifdef WITH_FILESYSTEM
+ #ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
-#endif // WITH_FILESYSTEM
+ #endif // WITH_FILESYSTEM
disableInterrupts();
miosix_private::IRQsystemReboot();
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h
index 6b276803f54778927355ecd47e50083efe647b96..e7ece74a73e7336ad18927bf0c8c95b8dd97a419 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h
+++ b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h
@@ -54,19 +54,21 @@ void configureSdram();
* \internal
* Board pin definition
*/
-typedef Gpio<GPIOJ_BASE, 13> userLed1;
-typedef Gpio<GPIOJ_BASE, 5> userLed2;
-typedef Gpio<GPIOA_BASE, 12> userLed3;
-typedef Gpio<GPIOA_BASE, 0> userBtn;
-typedef Gpio<GPIOI_BASE, 15> sdCardDetect;
-
-inline void ledOn() {
+typedef Gpio<GPIOJ_BASE,13> userLed1;
+typedef Gpio<GPIOJ_BASE,5> userLed2;
+typedef Gpio<GPIOA_BASE,12> userLed3;
+typedef Gpio<GPIOA_BASE,0> userBtn;
+typedef Gpio<GPIOI_BASE,15> sdCardDetect;
+
+inline void ledOn()
+{
userLed1::high();
userLed2::high();
userLed3::high();
}
-inline void ledOff() {
+inline void ledOff()
+{
userLed1::low();
userLed2::low();
userLed3::low();
diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc
index 50937456938a56fea367c592f9c9a24dfc0b35c5..bc6b2dc469ed35613a18b00ecc2aadb3469d712f 100644
--- a/miosix/config/Makefile.inc
+++ b/miosix/config/Makefile.inc
@@ -2954,10 +2954,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
CFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO
CXXFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO
- ## Select the SDMMC peripheral to use for the filesystem
- SD := -D__SDMMC1
- # SD := -D__SDMMC2
-
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
@@ -2993,10 +2989,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
CFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO
CXXFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO
- ## Select the SDMMC peripheral to use for the filesystem
- SD := -D__SDMMC1
- # SD := -D__SDMMC2
-
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
@@ -3036,10 +3028,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
## Enables the initialization of the external 16MB SDRAM memory
XRAM := -D__ENABLE_XRAM
- ## Select the SDMMC peripheral to use for the filesystem
- # SD := -D__SDMMC1
- SD := -D__SDMMC2
-
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_216MHz=216000000
@@ -3071,9 +3059,9 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
AFLAGS_BASE := $(ARCHOPTS)
CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- $(SD) $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
+ $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
- $(SD) $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
+ $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
LFLAGS_BASE := $(ARCHOPTS) -Wl,--gc-sections,-Map,main.map \
-Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
$(OPT_OPTIMIZATION) -nostdlib
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
index db80454f1d2f0f578e3eba6b0a0bbb8f4c0f09ef..5111754d78272523c5641ff9f3d2c9412680a5a9 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h
@@ -1,5 +1,5 @@
/***************************************************************************
- * Copyright (C) 2018 by Terraneo Federico *
+ * Copyright (C) 2018-2021 by Terraneo Federico *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
@@ -25,10 +25,7 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
-#ifndef BOARD_SETTINGS_H
-#define BOARD_SETTINGS_H
-
-#include "util/version.h"
+#pragma once
/**
* \internal
@@ -45,32 +42,33 @@ namespace miosix {
/// Size of stack for main().
/// The C standard library is stack-heavy (iprintf requires 1KB)
-const unsigned int MAIN_STACK_SIZE = 4 * 1024;
+const unsigned int MAIN_STACK_SIZE=4*1024;
/// Frequency of tick (in Hz). For the priority scheduler this is also the
/// context switch frequency
-const unsigned int TICK_FREQ = 1000;
+const unsigned int TICK_FREQ=1000;
///\internal Aux timer run @ 100KHz
/// Note that since the timer is only 16 bits this imposes a limit on the
/// burst measurement of 655ms. If due to a pause_kernel() or
/// disable_interrupts() section a thread runs for more than that time, a wrong
/// burst value will be measured
-const unsigned int AUX_TIMER_CLOCK = 100000;
-const unsigned int AUX_TIMER_MAX = 0xffff; ///<\internal Aux timer is 16 bits
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
/// Serial port
-const unsigned int defaultSerialSpeed = 115200;
+const unsigned int defaultSerialSpeed=115200;
+// #define SERIAL_1_DMA
+// #define SERIAL_2_DMA
#define SERIAL_3_DMA
-// SD card driver
-static const unsigned char sdVoltage = 33; // Board powered @ 3.3V
-// #define SD_ONE_BIT_DATABUS
+//SD card driver
+static const unsigned char sdVoltage=33; //Board powered @ 3.3V
+#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus
+#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2
/**
* \}
*/
} //namespace miosix
-
-#endif /* BOARD_SETTINGS_H */
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
index cc61b139592ffb9a3e5c68122326a3ed908eda94..edd7f380548a04ffb50e887ea3917c2cc510a70c 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h
@@ -27,8 +27,6 @@
#pragma once
-#include "util/version.h"
-
/**
* \internal
* Versioning for board_settings.h for out of git tree projects
@@ -44,27 +42,30 @@ namespace miosix {
/// Size of stack for main().
/// The C standard library is stack-heavy (iprintf requires 1KB)
-const unsigned int MAIN_STACK_SIZE = 4 * 1024;
+const unsigned int MAIN_STACK_SIZE=4*1024;
/// Frequency of tick (in Hz). For the priority scheduler this is also the
/// context switch frequency
-const unsigned int TICK_FREQ = 1000;
+const unsigned int TICK_FREQ=1000;
///\internal Aux timer run @ 100KHz
/// Note that since the timer is only 16 bits this imposes a limit on the
/// burst measurement of 655ms. If due to a pause_kernel() or
/// disable_interrupts() section a thread runs for more than that time, a wrong
/// burst value will be measured
-const unsigned int AUX_TIMER_CLOCK = 100000;
-const unsigned int AUX_TIMER_MAX = 0xffff; ///<\internal Aux timer is 16 bits
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
/// Serial port
-const unsigned int defaultSerialSpeed = 115200;
+const unsigned int defaultSerialSpeed=115200;
+// #define SERIAL_1_DMA
+// #define SERIAL_2_DMA
#define SERIAL_3_DMA
-// SD card driver
-static const unsigned char sdVoltage = 33; // Board powered @ 3.3V
+//SD card driver
+static const unsigned char sdVoltage=33; //Board powered @ 3.3V
// #define SD_ONE_BIT_DATABUS
+#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2
/**
* \}
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
index 14ebb5318909d5e2c11ad12693b56abfdf0bf6e3..bf231eaf57fc93a96159b39ae17a5869a909e41e 100644
--- a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h
@@ -27,8 +27,6 @@
#pragma once
-#include "util/version.h"
-
/**
* \internal
* Versioning for board_settings.h for out of git tree projects
@@ -44,28 +42,31 @@ namespace miosix {
/// Size of stack for main().
/// The C standard library is stack-heavy (iprintf requires 1KB)
-const unsigned int MAIN_STACK_SIZE = 4 * 1024;
+const unsigned int MAIN_STACK_SIZE=4*1024;
/// Frequency of tick (in Hz). For the priority scheduler this is also the
/// context switch frequency
-const unsigned int TICK_FREQ = 1000;
+const unsigned int TICK_FREQ=1000;
///\internal Aux timer run @ 100KHz
/// Note that since the timer is only 16 bits this imposes a limit on the
/// burst measurement of 655ms. If due to a pause_kernel() or
/// disable_interrupts() section a thread runs for more than that time, a wrong
/// burst value will be measured
-const unsigned int AUX_TIMER_CLOCK = 100000;
-const unsigned int AUX_TIMER_MAX = 0xffff; ///<\internal Aux timer is 16 bits
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
/// Serial port
-const unsigned int defaultSerial = 1;
-const unsigned int defaultSerialSpeed = 115200;
+const unsigned int defaultSerial=1;
+const unsigned int defaultSerialSpeed=115200;
#define SERIAL_1_DMA
+// #define SERIAL_2_DMA
+// #define SERIAL_3_DMA
// SD card driver
-static const unsigned char sdVoltage = 33; // Board powered @ 3.3V
+static const unsigned char sdVoltage=33; //Board powered @ 3.3V
// #define SD_ONE_BIT_DATABUS
+#define SD_SDMMC 2 //Select either SDMMC1 or SDMMC2
/**
* \}
diff --git a/miosix/config/options.cmake b/miosix/config/options.cmake
index bd5efa3b3e7b7e9af28411ff8f5765338c24349e..e495c9e6e42c483e6a17e0ece9f11ed0294f1f46 100644
--- a/miosix/config/options.cmake
+++ b/miosix/config/options.cmake
@@ -3105,10 +3105,6 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
list(APPEND CFLAGS_BASE -D_BOARD_STM32F746ZG_NUCLEO)
list(APPEND CXXFLAGS_BASE -D_BOARD_STM32F746ZG_NUCLEO)
- ## Select the SDMMC peripheral to use for the filesystem
- set(SD -D__SDMMC1)
- # set(SD -D__SDMMC2)
-
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
set(CLOCK_FREQ -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000)
@@ -3145,10 +3141,6 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
list(APPEND CFLAGS_BASE -D_BOARD_STM32F767ZI_NUCLEO)
list(APPEND CXXFLAGS_BASE -D_BOARD_STM32F767ZI_NUCLEO)
- ## Select the SDMMC peripheral to use for the filesystem
- set(SD -D__SDMMC1)
- # set(SD -D__SDMMC2)
-
## Enables the initialization of the external 16MB SDRAM memory
set(XRAM -D__ENABLE_XRAM)
@@ -3189,10 +3181,6 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
list(APPEND CFLAGS_BASE -D_BOARD_STM32F769NI_DISCO)
list(APPEND CXXFLAGS_BASE -D_BOARD_STM32F769NI_DISCO)
- ## Select the SDMMC peripheral to use for the filesystem
- # set(SD -D__SDMMC1)
- set(SD -D__SDMMC2)
-
## Enables the initialization of the external 16MB SDRAM memory
set(XRAM -D__ENABLE_XRAM)
@@ -3213,8 +3201,8 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
endif()
set(AFLAGS_BASE ${ARCHOPTS})
- list(APPEND CFLAGS_BASE -D_ARCH_CORTEXM7_STM32F7 ${CLOCK_FREQ} ${XRAM} ${SRAM_BOOT} ${SD} ${ARCHOPTS} ${OPT_OPTIMIZATION} -c)
- list(APPEND CXXFLAGS_BASE -D_ARCH_CORTEXM7_STM32F7 ${CLOCK_FREQ} ${XRAM} ${SRAM_BOOT} ${SD} ${ARCHOPTS} ${OPT_EXCEPT} ${OPT_OPTIMIZATION} -c)
+ list(APPEND CFLAGS_BASE -D_ARCH_CORTEXM7_STM32F7 ${CLOCK_FREQ} ${XRAM} ${SRAM_BOOT} ${ARCHOPTS} ${OPT_OPTIMIZATION} -c)
+ list(APPEND CXXFLAGS_BASE -D_ARCH_CORTEXM7_STM32F7 ${CLOCK_FREQ} ${XRAM} ${SRAM_BOOT} ${ARCHOPTS} ${OPT_EXCEPT} ${OPT_OPTIMIZATION} -c)
set(LFLAGS_BASE ${ARCHOPTS} -Wl,--gc-sections,-Map=main.map -Wl,-T${LINKER_SCRIPT} ${OPT_EXCEPT} ${OPT_OPTIMIZATION} -nostdlib)
## Select architecture specific files