From 8dbca5ad04aa3c52603ef98a516e1049171a8405 Mon Sep 17 00:00:00 2001
From: Alberto Nidasio <alberto.nidasio@skywarder.eu>
Date: Fri, 9 Jun 2023 14:44:29 +0200
Subject: [PATCH] Updated compute unit board with 16MB ram
---
.../interfaces-impl/bsp.cpp | 23 ++++++++++---------
.../interfaces-impl/bsp_impl.h | 21 +++++++++++++----
...m32_2m+8m_xram.ld => stm32_2m+16m_xram.ld} | 8 +++----
miosix/config/options.cmake | 2 +-
4 files changed, 33 insertions(+), 21 deletions(-)
rename miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/{stm32_2m+8m_xram.ld => stm32_2m+16m_xram.ld} (96%)
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp.cpp
index 30f6b33a..8e255466 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp.cpp
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp.cpp
@@ -76,7 +76,7 @@ void configureSdram() {
// - PG8: FMC_SDCLK (sdram clock)
// - PB5: FMC_SDCKE1 (sdram bank 2 clock enable)
// - PB6: FMC_SDNE1 (sdram bank 2 chip enable)
- // - PF0: FMC_A0
+ // - PF0: FMC_A0
// - PF1: FMC_A1
// - PF2: FMC_A2
// - PF3: FMC_A3
@@ -128,7 +128,7 @@ void configureSdram() {
GPIOE->AFR[1] = 0xcccccccc;
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xccccc000;
- GPIOG->AFR[0] = 0x00cc00cc;
+ GPIOG->AFR[0] = 0x00cc0ccc;
GPIOG->AFR[1] = 0xc000000c;
// Mode
@@ -137,7 +137,7 @@ void configureSdram() {
GPIOD->MODER = 0xa02a000a;
GPIOE->MODER = 0xaaaa800a;
GPIOF->MODER = 0xaa800aaa;
- GPIOG->MODER = 0x80020a0a;
+ GPIOG->MODER = 0x80020a2a;
// Speed (high speed for all, very high speed for SDRAM pins)
GPIOB->OSPEEDR = 0x00003c00;
@@ -145,7 +145,7 @@ void configureSdram() {
GPIOD->OSPEEDR = 0xf03f000f;
GPIOE->OSPEEDR = 0xffffc00f;
GPIOF->OSPEEDR = 0xffc00fff;
- GPIOG->OSPEEDR = 0xc0030f0f;
+ GPIOG->OSPEEDR = 0xc0030f3f;
// Since we'we un-configured PB3 and PB4 (by default they are SWO and NJRST)
// finish the job and remove the default pull-up
@@ -166,7 +166,7 @@ void configureSdram() {
| FMC_SDCR2_CAS_1 // 2 cycles CAS latency
| FMC_SDCR2_NB // 4 internal banks
| FMC_SDCR2_MWID_0 // 16 bit data bus
- | FMC_SDCR2_NR_0 // 12 bit row address
+ | FMC_SDCR2_NR_1 // 13 bit row address
| 0; // 8 bit column address
// 2. Memory device timings
@@ -175,10 +175,10 @@ void configureSdram() {
FMC_Bank5_6->SDTR[0] = (2 - 1) << FMC_SDTR1_TRP_Pos // 2 cycles TRP (18.52ns > 18ns)
| (7 - 1) << FMC_SDTR1_TRC_Pos; // 7 cycles TRC (64.82ns > 60ns)
FMC_Bank5_6->SDTR[1] = (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns)
- | (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (min 2 clock cycles)
+ | (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (min 2cc > 12ns)
| (5 - 1) << FMC_SDTR1_TRAS_Pos // 5 cycles TRAS (46.3ns > 42ns)
| (7 - 1) << FMC_SDTR1_TXSR_Pos // 7 cycles TXSR (74.08ns > 61.5ns)
- | (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (min 2 clock cycles)
+ | (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (min 2cc > 12ns)
#else
#error No SDRAM timings for this clock
#endif
@@ -209,10 +209,10 @@ void configureSdram() {
sdramCommandWait();
// 8. Program the refresh rate (4K / 32ms)
-// 32ms / 4096 = 7.8125us
+// 64ms / 8192 = 7.8125us
#ifdef SYSCLK_FREQ_216MHz
- // 7.8125us * 108MHz = 843 - 20 = 823
- FMC_Bank5_6->SDRTR = 823 << FMC_SDRTR_COUNT_Pos;
+ // 7.8125us * 133MHz = 1039 - 20 = 1019
+ FMC_Bank5_6->SDRTR = 1019 << FMC_SDRTR_COUNT_Pos;
#else
#error No SDRAM refresh timings for this clock
#endif
@@ -224,7 +224,8 @@ void IRQbspInit() {
userLed1::mode(Mode::OUTPUT);
userLed2::mode(Mode::OUTPUT);
- userLed3::mode(Mode::OUTPUT);
+ userLed3_1::mode(Mode::OUTPUT);
+ userLed3_2::mode(Mode::OUTPUT);
userLed4::mode(Mode::OUTPUT);
userSwitch::mode(Mode::INPUT);
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp_impl.h
index c1546083..1e3adc25 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp_impl.h
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp_impl.h
@@ -57,7 +57,8 @@ void configureSdram();
*/
typedef Gpio<GPIOB_BASE, 7> userLed1;
typedef Gpio<GPIOE_BASE, 3> userLed2;
-typedef Gpio<GPIOC_BASE, 13> userLed3;
+typedef Gpio<GPIOC_BASE, 13> userLed3_1;
+typedef Gpio<GPIOG_BASE, 9> userLed3_2;
typedef Gpio<GPIOC_BASE, 2> userLed4;
typedef Gpio<GPIOB_BASE, 2> userSwitch;
@@ -65,7 +66,8 @@ inline void ledOn()
{
userLed1::high();
userLed2::high();
- userLed3::high();
+ userLed3_1::high();
+ userLed3_2::high();
userLed4::high();
}
@@ -73,7 +75,8 @@ inline void ledOff()
{
userLed1::low();
userLed2::low();
- userLed3::low();
+ userLed3_1::low();
+ userLed3_2::low();
userLed4::low();
}
@@ -85,9 +88,17 @@ inline void led2On() { userLed2::high(); }
inline void led2Off() { userLed2::low(); }
-inline void led3On() { userLed3::high(); }
+inline void led3On()
+{
+ userLed3_1::high();
+ userLed3_2::high();
+}
-inline void led3Off() { userLed3::low(); }
+inline void led3Off()
+{
+ userLed3_1::low();
+ userLed3_2::low();
+}
/**
* Polls the SD card sense GPIO.
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+8m_xram.ld b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+16m_xram.ld
similarity index 96%
rename from miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+8m_xram.ld
rename to miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+16m_xram.ld
index 50a2e68e..5b3545ab 100644
--- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+8m_xram.ld
+++ b/miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+16m_xram.ld
@@ -1,5 +1,5 @@
/*
- * C++ enabled linker script for stm32f769ni (2M FLASH, 512K RAM, 8MB XRAM)
+ * C++ enabled linker script for stm32f769ni (2M FLASH, 512K RAM, 16MB XRAM)
* Developed by TFT: Terraneo Federico Technologies
* Optimized for use with the Miosix kernel
*/
@@ -8,7 +8,7 @@
* This linker script puts:
* - read only data and code (.text, .rodata, .eh_*) in FLASH
* - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM
- * - .data, .bss, stacks and heap in the external 8MB SDRAM.
+ * - .data, .bss, stacks and heap in the external 16MB SDRAM.
*/
/*
@@ -42,7 +42,7 @@ _main_stack_top = 0x20000000 + _main_stack_size;
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
/* Mapping the heap into XRAM */
-_heap_end = 0xd0000000 + 8M; /* end of available ram */
+_heap_end = 0xd0000000 + 16M; /* end of available ram */
/* Identify the Entry Point */
ENTRY(_Z13Reset_Handlerv)
@@ -59,7 +59,7 @@ ENTRY(_Z13Reset_Handlerv)
*/
MEMORY
{
- xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M
+ xram(wx) : ORIGIN = 0xd0000000, LENGTH = 16M
sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K
dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */
bram(rw) : ORIGIN = 0x40024000, LENGTH = 4K /* Bakup SRAM */
diff --git a/miosix/config/options.cmake b/miosix/config/options.cmake
index a80c0760..ff2df324 100644
--- a/miosix/config/options.cmake
+++ b/miosix/config/options.cmake
@@ -3172,7 +3172,7 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
## Their path must be relative to the miosix directory.
set(BOOT_FILE ${KPATH}/${BOARD_INC}/core/stage_1_boot.cpp)
# set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+384k_ram.ld)
- set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+8m_xram.ld)
+ set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_2m+16m_xram.ld)
## Enables the initialization of the external SDRAM memory
set(XRAM -D__ENABLE_XRAM)
--
GitLab