diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h b/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
index d13672b2fc6237eadb3b730a55af6a4c439b5697..754ca272837766dc8c4895841b8957d9a7cc6883 100644
--- a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
+++ b/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h
@@ -7,7 +7,7 @@
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral�s registers hardware
+ * - Macros to access peripheral�s registers hardware
*
******************************************************************************
* @attention
@@ -10800,6 +10800,9 @@ typedef struct
#define RCC_APB1ENR_LPTIM1EN_Pos (9U)
#define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */
#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk
+#define RCC_APB1ENR_RTCEN_Pos (10U)
+#define RCC_APB1ENR_RTCEN_Msk (0x1U << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */
+#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk
#define RCC_APB1ENR_WWDGEN_Pos (11U)
#define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/core/stage_1_boot.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..e3a6fcc8e93399c3ce792cd178d0cb36d2fce80c
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/core/stage_1_boot.cpp
@@ -0,0 +1,428 @@
+
+#include "interfaces/arch_registers.h"
+#include "core/interrupts.h" //For the unexpected interrupt call
+#include "core/cache_cortexMx.h"
+#include "kernel/stage_2_boot.h"
+#include <string.h>
+
+/*
+ * startup.cpp
+ * STM32 C++ startup.
+ * NOTE: for stm32f756 devices ONLY.
+ * Supports interrupt handlers in C++ without extern "C"
+ * Developed by Terraneo Federico, based on ST startup code.
+ * Additionally modified to boot Miosix.
+ */
+
+/**
+ * Called by Reset_Handler, performs initialization and calls main.
+ * Never returns.
+ */
+void program_startup() __attribute__((noreturn));
+void program_startup()
+{
+ //Cortex M3 core appears to get out of reset with interrupts already enabled
+ __disable_irq();
+
+ //SystemInit() is called *before* initializing .data and zeroing .bss
+ //Despite all startup files provided by ST do the opposite, there are three
+ //good reasons to do so:
+ //First, the CMSIS specifications say that SystemInit() must not access
+ //global variables, so it is actually possible to call it before
+ //Second, when running Miosix with the xram linker scripts .data and .bss
+ //are placed in the external RAM, so we *must* call SystemInit(), which
+ //enables xram, before touching .data and .bss
+ //Third, this is a performance improvement since the loops that initialize
+ //.data and zeros .bss now run with the CPU at full speed instead of 8MHz
+ SystemInit();
+
+ miosix::IRQconfigureCache();
+
+ //These are defined in the linker script
+ extern unsigned char _etext asm("_etext");
+ extern unsigned char _data asm("_data");
+ extern unsigned char _edata asm("_edata");
+ extern unsigned char _bss_start asm("_bss_start");
+ extern unsigned char _bss_end asm("_bss_end");
+
+ //Initialize .data section, clear .bss section
+ unsigned char *etext=&_etext;
+ unsigned char *data=&_data;
+ unsigned char *edata=&_edata;
+ unsigned char *bss_start=&_bss_start;
+ unsigned char *bss_end=&_bss_end;
+ memcpy(data, etext, edata-data);
+ memset(bss_start, 0, bss_end-bss_start);
+
+ //Move on to stage 2
+ _init();
+
+ //If main returns, reboot
+ NVIC_SystemReset();
+ for(;;) ;
+}
+
+/**
+ * Reset handler, called by hardware immediately after reset
+ */
+void Reset_Handler() __attribute__((__interrupt__, noreturn));
+void Reset_Handler()
+{
+ /*
+ * Initialize process stack and switch to it.
+ * This is required for booting Miosix, a small portion of the top of the
+ * heap area will be used as stack until the first thread starts. After,
+ * this stack will be abandoned and the process stack will point to the
+ * current thread's stack.
+ */
+ asm volatile("ldr r0, =_heap_end \n\t"
+ "msr psp, r0 \n\t"
+ "movw r0, #2 \n\n" //Privileged, process stack
+ "msr control, r0 \n\t"
+ "isb \n\t":::"r0");
+
+ program_startup();
+}
+
+/**
+ * All unused interrupts call this function.
+ */
+extern "C" void Default_Handler()
+{
+ unexpectedInterrupt();
+}
+
+//System handlers
+void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not
+void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are
+void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
+void /*__attribute__((weak))*/ MemManage_Handler();
+void /*__attribute__((weak))*/ BusFault_Handler();
+void /*__attribute__((weak))*/ UsageFault_Handler();
+void /*__attribute__((weak))*/ SVC_Handler();
+void /*__attribute__((weak))*/ DebugMon_Handler();
+void /*__attribute__((weak))*/ PendSV_Handler();
+void /*__attribute__((weak))*/ SysTick_Handler();
+
+//Interrupt handlers
+void __attribute__((weak)) WWDG_IRQHandler();
+void __attribute__((weak)) PVD_IRQHandler();
+void __attribute__((weak)) TAMP_STAMP_IRQHandler();
+void __attribute__((weak)) RTC_WKUP_IRQHandler();
+void __attribute__((weak)) FLASH_IRQHandler();
+void __attribute__((weak)) RCC_IRQHandler();
+void __attribute__((weak)) EXTI0_IRQHandler();
+void __attribute__((weak)) EXTI1_IRQHandler();
+void __attribute__((weak)) EXTI2_IRQHandler();
+void __attribute__((weak)) EXTI3_IRQHandler();
+void __attribute__((weak)) EXTI4_IRQHandler();
+void __attribute__((weak)) DMA1_Stream0_IRQHandler();
+void __attribute__((weak)) DMA1_Stream1_IRQHandler();
+void __attribute__((weak)) DMA1_Stream2_IRQHandler();
+void __attribute__((weak)) DMA1_Stream3_IRQHandler();
+void __attribute__((weak)) DMA1_Stream4_IRQHandler();
+void __attribute__((weak)) DMA1_Stream5_IRQHandler();
+void __attribute__((weak)) DMA1_Stream6_IRQHandler();
+void __attribute__((weak)) ADC_IRQHandler();
+void __attribute__((weak)) CAN1_TX_IRQHandler();
+void __attribute__((weak)) CAN1_RX0_IRQHandler();
+void __attribute__((weak)) CAN1_RX1_IRQHandler();
+void __attribute__((weak)) CAN1_SCE_IRQHandler();
+void __attribute__((weak)) EXTI9_5_IRQHandler();
+void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler();
+void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler();
+void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler();
+void __attribute__((weak)) TIM1_CC_IRQHandler();
+void __attribute__((weak)) TIM2_IRQHandler();
+void __attribute__((weak)) TIM3_IRQHandler();
+void __attribute__((weak)) TIM4_IRQHandler();
+void __attribute__((weak)) I2C1_EV_IRQHandler();
+void __attribute__((weak)) I2C1_ER_IRQHandler();
+void __attribute__((weak)) I2C2_EV_IRQHandler();
+void __attribute__((weak)) I2C2_ER_IRQHandler();
+void __attribute__((weak)) SPI1_IRQHandler();
+void __attribute__((weak)) SPI2_IRQHandler();
+void __attribute__((weak)) USART1_IRQHandler();
+void __attribute__((weak)) USART2_IRQHandler();
+void __attribute__((weak)) USART3_IRQHandler();
+void __attribute__((weak)) EXTI15_10_IRQHandler();
+void __attribute__((weak)) RTC_Alarm_IRQHandler();
+void __attribute__((weak)) OTG_FS_WKUP_IRQHandler();
+void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler();
+void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler();
+void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler();
+void __attribute__((weak)) TIM8_CC_IRQHandler();
+void __attribute__((weak)) DMA1_Stream7_IRQHandler();
+void __attribute__((weak)) FMC_IRQHandler();
+void __attribute__((weak)) SDMMC1_IRQHandler();
+void __attribute__((weak)) TIM5_IRQHandler();
+void __attribute__((weak)) SPI3_IRQHandler();
+void __attribute__((weak)) UART4_IRQHandler();
+void __attribute__((weak)) UART5_IRQHandler();
+void __attribute__((weak)) TIM6_DAC_IRQHandler();
+void __attribute__((weak)) TIM7_IRQHandler();
+void __attribute__((weak)) DMA2_Stream0_IRQHandler();
+void __attribute__((weak)) DMA2_Stream1_IRQHandler();
+void __attribute__((weak)) DMA2_Stream2_IRQHandler();
+void __attribute__((weak)) DMA2_Stream3_IRQHandler();
+void __attribute__((weak)) DMA2_Stream4_IRQHandler();
+void __attribute__((weak)) ETH_IRQHandler();
+void __attribute__((weak)) ETH_WKUP_IRQHandler();
+void __attribute__((weak)) CAN2_TX_IRQHandler();
+void __attribute__((weak)) CAN2_RX0_IRQHandler();
+void __attribute__((weak)) CAN2_RX1_IRQHandler();
+void __attribute__((weak)) CAN2_SCE_IRQHandler();
+void __attribute__((weak)) OTG_FS_IRQHandler();
+void __attribute__((weak)) DMA2_Stream5_IRQHandler();
+void __attribute__((weak)) DMA2_Stream6_IRQHandler();
+void __attribute__((weak)) DMA2_Stream7_IRQHandler();
+void __attribute__((weak)) USART6_IRQHandler();
+void __attribute__((weak)) I2C3_EV_IRQHandler();
+void __attribute__((weak)) I2C3_ER_IRQHandler();
+void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler();
+void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler();
+void __attribute__((weak)) OTG_HS_WKUP_IRQHandler();
+void __attribute__((weak)) OTG_HS_IRQHandler();
+void __attribute__((weak)) DCMI_IRQHandler();
+void __attribute__((weak)) RNG_IRQHandler();
+void __attribute__((weak)) FPU_IRQHandler();
+void __attribute__((weak)) UART7_IRQHandler();
+void __attribute__((weak)) UART8_IRQHandler();
+void __attribute__((weak)) SPI4_IRQHandler();
+void __attribute__((weak)) SPI5_IRQHandler();
+void __attribute__((weak)) SPI6_IRQHandler();
+void __attribute__((weak)) SAI1_IRQHandler();
+void __attribute__((weak)) LTDC_IRQHandler();
+void __attribute__((weak)) LTDC_ER_IRQHandler();
+void __attribute__((weak)) DMA2D_IRQHandler();
+void __attribute__((weak)) SAI2_IRQHandler();
+void __attribute__((weak)) QUADSPI_IRQHandler();
+void __attribute__((weak)) LPTIM1_IRQHandler();
+void __attribute__((weak)) CEC_IRQHandler();
+void __attribute__((weak)) I2C4_EV_IRQHandler();
+void __attribute__((weak)) I2C4_ER_IRQHandler();
+void __attribute__((weak)) SPDIF_RX_IRQHandler();
+
+//Stack top, defined in the linker script
+extern char _main_stack_top asm("_main_stack_top");
+
+//Interrupt vectors, must be placed @ address 0x00000000
+//The extern declaration is required otherwise g++ optimizes it out
+extern void (* const __Vectors[])();
+void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
+{
+ reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
+ Reset_Handler, /* Reset Handler */
+ NMI_Handler, /* NMI Handler */
+ HardFault_Handler, /* Hard Fault Handler */
+ MemManage_Handler, /* MPU Fault Handler */
+ BusFault_Handler, /* Bus Fault Handler */
+ UsageFault_Handler, /* Usage Fault Handler */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ 0, /* Reserved */
+ SVC_Handler, /* SVCall Handler */
+ DebugMon_Handler, /* Debug Monitor Handler */
+ 0, /* Reserved */
+ PendSV_Handler, /* PendSV Handler */
+ SysTick_Handler, /* SysTick Handler */
+
+ /* External Interrupts */
+ WWDG_IRQHandler,
+ PVD_IRQHandler,
+ TAMP_STAMP_IRQHandler,
+ RTC_WKUP_IRQHandler,
+ FLASH_IRQHandler,
+ RCC_IRQHandler,
+ EXTI0_IRQHandler,
+ EXTI1_IRQHandler,
+ EXTI2_IRQHandler,
+ EXTI3_IRQHandler,
+ EXTI4_IRQHandler,
+ DMA1_Stream0_IRQHandler,
+ DMA1_Stream1_IRQHandler,
+ DMA1_Stream2_IRQHandler,
+ DMA1_Stream3_IRQHandler,
+ DMA1_Stream4_IRQHandler,
+ DMA1_Stream5_IRQHandler,
+ DMA1_Stream6_IRQHandler,
+ ADC_IRQHandler,
+ CAN1_TX_IRQHandler,
+ CAN1_RX0_IRQHandler,
+ CAN1_RX1_IRQHandler,
+ CAN1_SCE_IRQHandler,
+ EXTI9_5_IRQHandler,
+ TIM1_BRK_TIM9_IRQHandler,
+ TIM1_UP_TIM10_IRQHandler,
+ TIM1_TRG_COM_TIM11_IRQHandler,
+ TIM1_CC_IRQHandler,
+ TIM2_IRQHandler,
+ TIM3_IRQHandler,
+ TIM4_IRQHandler,
+ I2C1_EV_IRQHandler,
+ I2C1_ER_IRQHandler,
+ I2C2_EV_IRQHandler,
+ I2C2_ER_IRQHandler,
+ SPI1_IRQHandler,
+ SPI2_IRQHandler,
+ USART1_IRQHandler,
+ USART2_IRQHandler,
+ USART3_IRQHandler,
+ EXTI15_10_IRQHandler,
+ RTC_Alarm_IRQHandler,
+ OTG_FS_WKUP_IRQHandler,
+ TIM8_BRK_TIM12_IRQHandler,
+ TIM8_UP_TIM13_IRQHandler,
+ TIM8_TRG_COM_TIM14_IRQHandler,
+ TIM8_CC_IRQHandler,
+ DMA1_Stream7_IRQHandler,
+ FMC_IRQHandler,
+ SDMMC1_IRQHandler,
+ TIM5_IRQHandler,
+ SPI3_IRQHandler,
+ UART4_IRQHandler,
+ UART5_IRQHandler,
+ TIM6_DAC_IRQHandler,
+ TIM7_IRQHandler,
+ DMA2_Stream0_IRQHandler,
+ DMA2_Stream1_IRQHandler,
+ DMA2_Stream2_IRQHandler,
+ DMA2_Stream3_IRQHandler,
+ DMA2_Stream4_IRQHandler,
+ ETH_IRQHandler,
+ ETH_WKUP_IRQHandler,
+ CAN2_TX_IRQHandler,
+ CAN2_RX0_IRQHandler,
+ CAN2_RX1_IRQHandler,
+ CAN2_SCE_IRQHandler,
+ OTG_FS_IRQHandler,
+ DMA2_Stream5_IRQHandler,
+ DMA2_Stream6_IRQHandler,
+ DMA2_Stream7_IRQHandler,
+ USART6_IRQHandler,
+ I2C3_EV_IRQHandler,
+ I2C3_ER_IRQHandler,
+ OTG_HS_EP1_OUT_IRQHandler,
+ OTG_HS_EP1_IN_IRQHandler,
+ OTG_HS_WKUP_IRQHandler,
+ OTG_HS_IRQHandler,
+ DCMI_IRQHandler,
+ 0,
+ RNG_IRQHandler,
+ FPU_IRQHandler,
+ UART7_IRQHandler,
+ UART8_IRQHandler,
+ SPI4_IRQHandler,
+ SPI5_IRQHandler,
+ SPI6_IRQHandler,
+ SAI1_IRQHandler,
+ LTDC_IRQHandler,
+ LTDC_ER_IRQHandler,
+ DMA2D_IRQHandler,
+ SAI2_IRQHandler,
+ QUADSPI_IRQHandler,
+ LPTIM1_IRQHandler,
+ CEC_IRQHandler,
+ I2C4_EV_IRQHandler,
+ I2C4_ER_IRQHandler,
+ SPDIF_RX_IRQHandler,
+};
+
+#pragma weak WWDG_IRQHandler = Default_Handler
+#pragma weak PVD_IRQHandler = Default_Handler
+#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
+#pragma weak RTC_WKUP_IRQHandler = Default_Handler
+#pragma weak FLASH_IRQHandler = Default_Handler
+#pragma weak RCC_IRQHandler = Default_Handler
+#pragma weak EXTI0_IRQHandler = Default_Handler
+#pragma weak EXTI1_IRQHandler = Default_Handler
+#pragma weak EXTI2_IRQHandler = Default_Handler
+#pragma weak EXTI3_IRQHandler = Default_Handler
+#pragma weak EXTI4_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
+#pragma weak ADC_IRQHandler = Default_Handler
+#pragma weak CAN1_TX_IRQHandler = Default_Handler
+#pragma weak CAN1_RX0_IRQHandler = Default_Handler
+#pragma weak CAN1_RX1_IRQHandler = Default_Handler
+#pragma weak CAN1_SCE_IRQHandler = Default_Handler
+#pragma weak EXTI9_5_IRQHandler = Default_Handler
+#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
+#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
+#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
+#pragma weak TIM1_CC_IRQHandler = Default_Handler
+#pragma weak TIM2_IRQHandler = Default_Handler
+#pragma weak TIM3_IRQHandler = Default_Handler
+#pragma weak TIM4_IRQHandler = Default_Handler
+#pragma weak I2C1_EV_IRQHandler = Default_Handler
+#pragma weak I2C1_ER_IRQHandler = Default_Handler
+#pragma weak I2C2_EV_IRQHandler = Default_Handler
+#pragma weak I2C2_ER_IRQHandler = Default_Handler
+#pragma weak SPI1_IRQHandler = Default_Handler
+#pragma weak SPI2_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_IRQHandler = Default_Handler
+#pragma weak EXTI15_10_IRQHandler = Default_Handler
+#pragma weak RTC_Alarm_IRQHandler = Default_Handler
+#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
+#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
+#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
+#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
+#pragma weak TIM8_CC_IRQHandler = Default_Handler
+#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
+#pragma weak FMC_IRQHandler = Default_Handler
+#pragma weak SDMMC1_IRQHandler = Default_Handler
+#pragma weak TIM5_IRQHandler = Default_Handler
+#pragma weak SPI3_IRQHandler = Default_Handler
+// #pragma weak UART4_IRQHandler = Default_Handler
+// #pragma weak UART5_IRQHandler = Default_Handler
+#pragma weak TIM6_DAC_IRQHandler = Default_Handler
+#pragma weak TIM7_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
+#pragma weak ETH_IRQHandler = Default_Handler
+#pragma weak ETH_WKUP_IRQHandler = Default_Handler
+#pragma weak CAN2_TX_IRQHandler = Default_Handler
+#pragma weak CAN2_RX0_IRQHandler = Default_Handler
+#pragma weak CAN2_RX1_IRQHandler = Default_Handler
+#pragma weak CAN2_SCE_IRQHandler = Default_Handler
+#pragma weak OTG_FS_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
+#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
+// #pragma weak USART6_IRQHandler = Default_Handler
+#pragma weak I2C3_EV_IRQHandler = Default_Handler
+#pragma weak I2C3_ER_IRQHandler = Default_Handler
+#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
+#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
+#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
+#pragma weak OTG_HS_IRQHandler = Default_Handler
+#pragma weak DCMI_IRQHandler = Default_Handler
+#pragma weak RNG_IRQHandler = Default_Handler
+#pragma weak FPU_IRQHandler = Default_Handler
+// #pragma weak UART7_IRQHandler = Default_Handler
+// #pragma weak UART8_IRQHandler = Default_Handler
+#pragma weak SPI4_IRQHandler = Default_Handler
+#pragma weak SPI5_IRQHandler = Default_Handler
+#pragma weak SPI6_IRQHandler = Default_Handler
+#pragma weak SAI1_IRQHandler = Default_Handler
+#pragma weak LTDC_IRQHandler = Default_Handler
+#pragma weak LTDC_ER_IRQHandler = Default_Handler
+#pragma weak DMA2D_IRQHandler = Default_Handler
+#pragma weak SAI2_IRQHandler = Default_Handler
+#pragma weak QUADSPI_IRQHandler = Default_Handler
+#pragma weak LPTIM1_IRQHandler = Default_Handler
+#pragma weak CEC_IRQHandler = Default_Handler
+#pragma weak I2C4_EV_IRQHandler = Default_Handler
+#pragma weak I2C4_ER_IRQHandler = Default_Handler
+#pragma weak SPDIF_RX_IRQHandler = Default_Handler
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/arch_registers_impl.h
new file mode 100644
index 0000000000000000000000000000000000000000..a634dd95cefe1bf8ab8506039f8167869597193d
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/arch_registers_impl.h
@@ -0,0 +1,18 @@
+
+#ifndef ARCH_REGISTERS_IMPL_H
+#define ARCH_REGISTERS_IMPL_H
+
+//stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and
+//includes core_cm7.h. Do not include core_cm7.h before.
+#define STM32F756xx
+#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
+
+#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1)
+#error "Wrong include order"
+#endif
+
+#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
+
+#define RCC_SYNC() __DSB() //TODO: can this dsb be removed?
+
+#endif //ARCH_REGISTERS_IMPL_H
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp.cpp
new file mode 100644
index 0000000000000000000000000000000000000000..4255b80daaaf96a636c756f851239917c22a2d73
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp.cpp
@@ -0,0 +1,123 @@
+/***************************************************************************
+ * Copyright (C) 2018 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+ * bsp.cpp Part of the Miosix Embedded OS.
+ * Board support package, this file initializes hardware.
+ ************************************************************************/
+
+#include "interfaces/bsp.h"
+
+#include <inttypes.h>
+#include <sys/ioctl.h>
+
+#include <cstdlib>
+
+#include "board_settings.h"
+#include "config/miosix_settings.h"
+#include "drivers/sd_stm32f2_f4_f7.h"
+#include "drivers/serial.h"
+#include "filesystem/console/console_device.h"
+#include "filesystem/file_access.h"
+#include "interfaces/arch_registers.h"
+#include "interfaces/delays.h"
+#include "interfaces/portability.h"
+#include "kernel/kernel.h"
+#include "kernel/logging.h"
+#include "kernel/sync.h"
+
+namespace miosix {
+
+//
+// Initialization
+//
+
+void IRQbspInit() {
+ // Enable all gpios
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
+ RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
+ RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN |
+ RCC_AHB1ENR_GPIOHEN;
+ RCC_SYNC();
+ GPIOA->OSPEEDR = 0xaaaaaaaa; // Default to 50MHz speed for all GPIOS
+ GPIOB->OSPEEDR = 0xaaaaaaaa;
+ GPIOC->OSPEEDR = 0xaaaaaaaa;
+ GPIOD->OSPEEDR = 0xaaaaaaaa;
+ GPIOE->OSPEEDR = 0xaaaaaaaa;
+ GPIOF->OSPEEDR = 0xaaaaaaaa;
+ GPIOH->OSPEEDR = 0xaaaaaaaa;
+
+ userLed1::mode(Mode::OUTPUT);
+ userLed2::mode(Mode::OUTPUT);
+ userLed3::mode(Mode::OUTPUT);
+ userBtn::mode(Mode::INPUT);
+
+ ledOn();
+ delayMs(100);
+ ledOff();
+ auto tx = Gpio<GPIOD_BASE, 8>::getPin();
+ tx.alternateFunction(7);
+ auto rx = Gpio<GPIOD_BASE, 9>::getPin();
+ rx.alternateFunction(7);
+ DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>(
+ new STM32Serial(3, defaultSerialSpeed, tx, rx)));
+}
+
+void bspInit2() {
+#ifdef WITH_FILESYSTEM
+ basicFilesystemSetup(SDIODriver::instance());
+#endif // WITH_FILESYSTEM
+}
+
+//
+// Shutdown and reboot
+//
+
+void shutdown() {
+ ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
+
+#ifdef WITH_FILESYSTEM
+ FilesystemManager::instance().umountAll();
+#endif // WITH_FILESYSTEM
+
+ disableInterrupts();
+ for (;;)
+ ;
+}
+
+void reboot() {
+ ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
+
+#ifdef WITH_FILESYSTEM
+ FilesystemManager::instance().umountAll();
+#endif // WITH_FILESYSTEM
+
+ disableInterrupts();
+ miosix_private::IRQsystemReboot();
+}
+
+} // namespace miosix
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp_impl.h
new file mode 100644
index 0000000000000000000000000000000000000000..a085aeb240565e9c160f88a4babdf1b2e3fb76cd
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/interfaces-impl/bsp_impl.h
@@ -0,0 +1,97 @@
+/***************************************************************************
+ * Copyright (C) 2018 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+/***********************************************************************
+* bsp_impl.h Part of the Miosix Embedded OS.
+* Board support package, this file initializes hardware.
+************************************************************************/
+
+#ifndef BSP_IMPL_H
+#define BSP_IMPL_H
+
+#include "config/miosix_settings.h"
+#include "interfaces/gpio.h"
+
+namespace miosix {
+
+/**
+\addtogroup Hardware
+\{
+*/
+
+/**
+ * \internal
+ * Board pin definition
+ */
+typedef Gpio<GPIOB_BASE, 0> userLed1;
+typedef Gpio<GPIOB_BASE, 7> userLed2;
+typedef Gpio<GPIOB_BASE, 14> userLed3;
+typedef Gpio<GPIOC_BASE, 13> userBtn;
+
+inline void ledOn() {
+ userLed1::high();
+ userLed2::high();
+ userLed3::high();
+}
+
+inline void ledOff() {
+ userLed1::low();
+ userLed2::low();
+ userLed3::low();
+}
+
+inline void led1On() { userLed1::high(); }
+
+inline void led1Off() { userLed1::low(); }
+
+inline void led2On() { userLed2::high(); }
+
+inline void led2Off() { userLed2::low(); }
+
+inline void led3On() { userLed3::high(); }
+
+inline void led3Off() { userLed3::low(); }
+
+/**
+ * Polls the SD card sense GPIO.
+ *
+ * This board has no SD card whatsoever, but a card can be connected to the
+ * following GPIOs:
+ * TODO: never tested
+ *
+ * \return true. As there's no SD card sense switch, let's pretend that
+ * the card is present.
+ */
+inline bool sdCardSense() { return true; }
+
+/**
+\}
+*/
+
+} //namespace miosix
+
+#endif //BSP_IMPL_H
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/openocd.cfg b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/openocd.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..9119116d686c21f5327dd60865d91d62db22d3bd
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/openocd.cfg
@@ -0,0 +1,17 @@
+#
+# OpenOCD configuration file for in-circuit debugging the stm32f4discovery
+# To start debugging issue those commands:
+# arm-miosix-eabi-gdb main.elf
+# target remote :3333
+# monitor reset halt
+# load
+# break main
+# continue
+#
+
+# Daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+# Board support is available in newer oocd
+source [find board/stm32f7discovery.cfg]
diff --git a/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/stm32_1m+256k_rom.ld b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/stm32_1m+256k_rom.ld
new file mode 100644
index 0000000000000000000000000000000000000000..1f81bdcc8c5aa7ce380d9141337a405a7297d5bd
--- /dev/null
+++ b/miosix/arch/cortexM7_stm32f7/stm32f756zg_nucleo/stm32_1m+256k_rom.ld
@@ -0,0 +1,178 @@
+/*
+ * C++ enabled linker script for stm32f746zg (1M FLASH, 256K RAM)
+ * Developed by TFT: Terraneo Federico Technologies
+ * Optimized for use with the Miosix kernel
+ */
+
+/*
+ * This linker script puts:
+ * - read only data and code (.text, .rodata, .eh_*) in FLASH
+ * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 64KB RAM
+ * - .data, .bss, stacks and heap in the internal RAM.
+ */
+
+/*
+ * The main stack is used for interrupt handling by the kernel.
+ *
+ * *** Readme ***
+ * This linker script places the main stack (used by the kernel for interrupts)
+ * at the bottom of the ram, instead of the top. This is done for two reasons:
+ *
+ * - as an optimization for microcontrollers with little ram memory. In fact
+ * the implementation of malloc from newlib requests memory to the OS in 4KB
+ * block (except the first block that can be smaller). This is probably done
+ * for compatibility with OSes with an MMU and paged memory. To see why this
+ * is bad, consider a microcontroller with 8KB of ram: when malloc finishes
+ * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
+ * fail because the top part of the ram is used by the main stack. As a
+ * result, the top part of the memory will not be used by malloc, even if
+ * available (and it is nearly *half* the ram on an 8KB mcu). By placing the
+ * main stack at the bottom of the ram, the upper 4KB block will be entirely
+ * free and available as heap space.
+ *
+ * - In case of main stack overflow the cpu will fault because access to memory
+ * before the beginning of the ram faults. Instead with the default stack
+ * placement the main stack will silently collide with the heap.
+ * Note: if increasing the main stack size also increase the ORIGIN value in
+ * the MEMORY definitions below accordingly.
+ */
+
+_main_stack_size = 512; /* main stack = 512Bytes */
+_main_stack_top = 0x20000000 + _main_stack_size;
+ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
+
+/* Mapping the heap to the end of SRAM2 */
+_heap_end = 0x20000000 + 320K; /* end of available ram */
+
+/* Identify the Entry Point */
+ENTRY(_Z13Reset_Handlerv)
+
+/*
+ * Specify the memory areas
+ *
+ * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled
+ * Memory). Technically, we could use this as normal RAM as there's a way for
+ * the DMA to access it, but the datasheet is unclear about performance
+ * penalties for doing so. To avoid nonuniform DMA memory access latencies,
+ * we leave this 64KB DTCM unused except for the first 512Bytes which are for
+ * the interrupt stack. This leaves us with 384KB of RAM
+ */
+MEMORY
+{
+ sram(wx) : ORIGIN = 0x20010000, LENGTH = 256K
+ dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 64K /* Used for main stack */
+ flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M
+}
+
+/* Now define the output sections */
+SECTIONS
+{
+ . = 0;
+
+ /* .text section: code goes to flash */
+ .text :
+ {
+ /* Startup code must go at address 0 */
+ KEEP(*(.isr_vector))
+
+ *(.text)
+ *(.text.*)
+ *(.gnu.linkonce.t.*)
+ /* These sections for thumb interwork? */
+ *(.glue_7)
+ *(.glue_7t)
+ /* These sections for C++? */
+ *(.gcc_except_table)
+ *(.gcc_except_table.*)
+ *(.ARM.extab*)
+ *(.gnu.linkonce.armextab.*)
+
+ . = ALIGN(4);
+ /* .rodata: constant data */
+ *(.rodata)
+ *(.rodata.*)
+ *(.gnu.linkonce.r.*)
+
+ /* C++ Static constructors/destructors (eabi) */
+ . = ALIGN(4);
+ KEEP(*(.init))
+
+ . = ALIGN(4);
+ __miosix_init_array_start = .;
+ KEEP (*(SORT(.miosix_init_array.*)))
+ KEEP (*(.miosix_init_array))
+ __miosix_init_array_end = .;
+
+ . = ALIGN(4);
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ . = ALIGN(4);
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+
+ . = ALIGN(4);
+ KEEP(*(.fini))
+
+ . = ALIGN(4);
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /* C++ Static constructors/destructors (elf) */
+ . = ALIGN(4);
+ _ctor_start = .;
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*crtend.o(.ctors))
+ _ctor_end = .;
+
+ . = ALIGN(4);
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*crtend.o(.dtors))
+ } > flash
+
+ /* .ARM.exidx is sorted, so has to go in its own output section. */
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > flash
+ __exidx_end = .;
+
+ /*
+ * .data section: global variables go to sram, but also store a copy to
+ * flash to initialize them
+ */
+ .data : ALIGN(8)
+ {
+ _data = .;
+ *(.data)
+ *(.data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ _edata = .;
+ } > sram AT > flash
+ _etext = LOADADDR(.data);
+
+ /* .bss section: uninitialized global variables go to sram */
+ _bss_start = .;
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ *(.gnu.linkonce.b.*)
+ . = ALIGN(8);
+ } > sram
+ _bss_end = .;
+
+ _end = .;
+ PROVIDE(end = .);
+}
diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f756zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f756zg_nucleo/board_settings.h
new file mode 100644
index 0000000000000000000000000000000000000000..2a80518089df7f4114d75d044cc1aba6e3fc502e
--- /dev/null
+++ b/miosix/config/arch/cortexM7_stm32f7/stm32f756zg_nucleo/board_settings.h
@@ -0,0 +1,77 @@
+/***************************************************************************
+ * Copyright (C) 2018-2021 by Terraneo Federico *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * As a special exception, if other files instantiate templates or use *
+ * macros or inline functions from this file, or you compile this file *
+ * and link it with other works to produce a work based on this file, *
+ * this file does not by itself cause the resulting work to be covered *
+ * by the GNU General Public License. However the source code for this *
+ * file must still be made available in accordance with the GNU General *
+ * Public License. This exception does not invalidate any other reasons *
+ * why a work based on this file might be covered by the GNU General *
+ * Public License. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, see <http://www.gnu.org/licenses/> *
+ ***************************************************************************/
+
+#pragma once
+
+/**
+ * \internal
+ * Versioning for board_settings.h for out of git tree projects
+ */
+#define BOARD_SETTINGS_VERSION 100
+
+namespace miosix {
+
+/**
+ * \addtogroup Settings
+ * \{
+ */
+
+/// Size of stack for main().
+/// The C standard library is stack-heavy (iprintf requires 1KB)
+const unsigned int MAIN_STACK_SIZE=4*1024;
+
+/// Frequency of tick (in Hz). For the priority scheduler this is also the
+/// context switch frequency
+const unsigned int TICK_FREQ=1000;
+
+///\internal Aux timer run @ 100KHz
+/// Note that since the timer is only 16 bits this imposes a limit on the
+/// burst measurement of 655ms. If due to a pause_kernel() or
+/// disable_interrupts() section a thread runs for more than that time, a wrong
+/// burst value will be measured
+const unsigned int AUX_TIMER_CLOCK=100000;
+const unsigned int AUX_TIMER_MAX=0xffff; ///<\internal Aux timer is 16 bits
+
+/// Serial port
+const unsigned int defaultSerialSpeed=115200;
+// #define SERIAL_1_DMA
+// #define SERIAL_2_DMA
+#define SERIAL_3_DMA
+
+//SD card driver
+static const unsigned char sdVoltage=33; //Board powered @ 3.3V
+#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus
+#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2
+
+/// Analog supply voltage for ADC, DAC, Reset blocks, RCs and PLL
+#define V_DDA_VOLTAGE 3.3f
+
+/**
+ * \}
+ */
+
+} //namespace miosix
diff --git a/miosix/config/boards.cmake b/miosix/config/boards.cmake
index 00928ad4afe317a63dbcdb177999a3dabb4ed8a1..a7e7995b948eb2b437e71ea77f60acb3a0eb063d 100644
--- a/miosix/config/boards.cmake
+++ b/miosix/config/boards.cmake
@@ -76,6 +76,7 @@ set(BOARDS
stm32f429zi_skyward_pyxis_auxiliary
stm32f429zi_skyward_parafoil
stm32f429zi_skyward_rig
+ stm32f756zg_nucleo
stm32f767zi_compute_unit
stm32f767zi_nucleo
stm32f769ni_discovery
diff --git a/miosix/config/options.cmake b/miosix/config/options.cmake
index e62c9c413b834971d01e94a24e911b93e5b903ab..6ed4c5049bdda6bda95cc035b8bdb940c307831f 100644
--- a/miosix/config/options.cmake
+++ b/miosix/config/options.cmake
@@ -1187,6 +1187,8 @@ elseif(${OPT_BOARD} STREQUAL stm32f769ni_discovery)
set(ARCH cortexM7_stm32f7)
elseif(${OPT_BOARD} STREQUAL stm32f429zi_skyward_rig)
set(ARCH cortexM4_stm32f4)
+elseif(${OPT_BOARD} STREQUAL stm32f756zg_nucleo)
+ set(ARCH cortexM7_stm32f7)
else()
message(FATAL_ERROR "no board specified in miosix/config/options.cmake")
endif()
@@ -3118,6 +3120,45 @@ elseif(${ARCH} STREQUAL cortexM7_stm32f7)
## board.
set(PROGRAM_CMDLINE echo "make program not supported.")
+ ##-------------------------------------------------------------------------
+ ## BOARD: stm32f756zg_nucleo
+ ##
+ elseif(${OPT_BOARD} STREQUAL stm32f756zg_nucleo)
+ ## Select appropriate compiler flags for both ASM/C/C++/linker
+ ## Not all stm32f7 have the double precision FPU. Those that only
+ ## support single precision are built as cortex m4
+ set(ARCHOPTS -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16)
+
+ ## Base directory with header files for this board
+ set(BOARD_INC arch/cortexM7_stm32f7/stm32f756zg_nucleo)
+
+ ## Select linker script and boot file
+ ## Their path must be relative to the miosix directory.
+ set(BOOT_FILE ${KPATH}/${BOARD_INC}/core/stage_1_boot.cpp)
+ set(LINKER_SCRIPT ${KPATH}/${BOARD_INC}/stm32_1m+256k_rom.ld)
+
+ ## Select architecture specific files
+ ## These are the files in arch/<arch name>/<board name>
+ set(ARCH_SRC
+ ${KPATH}/arch/common/drivers/stm32_hardware_rng.cpp
+ ${KPATH}/${BOARD_INC}/interfaces-impl/bsp.cpp
+ )
+
+ ## Add a #define to allow querying board name
+ list(APPEND CFLAGS_BASE -D_BOARD_STM32F756ZG_NUCLEO)
+ list(APPEND CXXFLAGS_BASE -D_BOARD_STM32F756ZG_NUCLEO)
+
+ ## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
+ set(CLOCK_FREQ -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000)
+
+ ## Select programmer command line
+ ## This is the program that is invoked when the user types
+ ## 'make program'
+ ## The command must provide a way to program the board, or print an
+ ## error message saying that 'make program' is not supported for that
+ ## board.
+ set(PROGRAM_CMDLINE echo "make program not supported.")
+
##-------------------------------------------------------------------------
## BOARD: stm32f767zi_compute_unit
##