diff --git a/.vscode/settings.json b/.vscode/settings.json
index 072d70fa988631832257ac7032e75f479dc907ec..7bd8637e6adfb4c38ccb9f9fdb7be981a1925ae4 100644
--- a/.vscode/settings.json
+++ b/.vscode/settings.json
@@ -141,9 +141,12 @@
                 "Canbus",
                 "canprotocol",
                 "Carlucci",
+                "CCMDATAR",
+                "CCMDATARAMEN",
                 "compid",
                 "Corigliano",
                 "CORTEXM",
+                "CPHA",
                 "cpitch",
                 "cppcheck",
                 "croll",
@@ -167,6 +170,8 @@
                 "fiprintf",
                 "FMPIE",
                 "FOVR",
+                "FRLVL",
+                "FRXTH",
                 "Gatttr",
                 "getdetahstate",
                 "Ghirardini",
@@ -209,6 +214,7 @@
                 "LIFCR",
                 "LISR",
                 "logdecoder",
+                "LSBFIRST",
                 "Luca",
                 "Mandelli",
                 "Matteo",
@@ -256,6 +262,7 @@
                 "RFOM",
                 "Riccardo",
                 "RQCP",
+                "RXCRCR",
                 "RXIRQ",
                 "RXNE",
                 "RXNEIE",
@@ -289,6 +296,7 @@
                 "TSCPP",
                 "TSVREFE",
                 "Tweakable",
+                "TXCRCR",
                 "txfp",
                 "TXIRQ",
                 "TXOK",
diff --git a/src/shared/drivers/spi/SPIBus.h b/src/shared/drivers/spi/SPIBus.h
index d1b8d0288c5722f78df3f15fa53fa5a6054ca37b..869683b8344cc103ac045d1da91f36020d937e1e 100644
--- a/src/shared/drivers/spi/SPIBus.h
+++ b/src/shared/drivers/spi/SPIBus.h
@@ -87,6 +87,12 @@ public:
      */
     void disable();
 
+#ifdef _ARCH_CORTEXM7_STM32F7
+    void set8bitRXNE();
+
+    void set16bitRXNE();
+#endif
+
     void set8BitFrameFormat();
 
     void set16BitFrameFormat();
@@ -304,13 +310,29 @@ inline void SPIBus::enable() { spi->CR1 |= SPI_CR1_SPE; }
 inline void SPIBus::disable() { spi->CR1 &= ~SPI_CR1_SPE; }
 
 #ifndef _ARCH_CORTEXM7_STM32F7
+
 inline void SPIBus::set8BitFrameFormat() { spi->CR1 &= ~SPI_CR1_DFF; }
 
 inline void SPIBus::set16BitFrameFormat() { spi->CR1 |= SPI_CR1_DFF; }
+
 #else
-inline void SPIBus::set8BitFrameFormat() { spi->CR1 &= ~SPI_CR1_CRCL; }
 
-inline void SPIBus::set16BitFrameFormat() { spi->CR1 |= SPI_CR1_CRCL; }
+inline void SPIBus::set8bitRXNE() { spi->CR2 |= SPI_CR2_FRXTH; }
+
+inline void SPIBus::set16bitRXNE() { spi->CR2 &= ~SPI_CR2_FRXTH; }
+
+inline void SPIBus::set8BitFrameFormat()
+{
+    spi->CR2 &= ~SPI_CR2_DS;
+    set8bitRXNE();
+}
+
+inline void SPIBus::set16BitFrameFormat()
+{
+    spi->CR2 |= SPI_CR2_DS;
+    set16bitRXNE();
+}
+
 #endif
 
 inline void SPIBus::enableSoftwareSlaveManagement() { spi->CR1 |= SPI_CR1_SSM; }
@@ -403,6 +425,11 @@ inline void SPIBus::configure(SPIBusConfig newConfig)
         enableInternalSlaveSelection();
         setMasterConfiguration();
 
+#ifdef _ARCH_CORTEXM7_STM32F7
+        // By default we use 8 bit transactions
+        spi.set8bitRXNE();
+#endif
+
         // Enable the peripheral
         enable();
     }
diff --git a/src/shared/drivers/spi/SPIDefs.h b/src/shared/drivers/spi/SPIDefs.h
index 0a156966455255b8cbc981fbaeae61ecdc612303..5b9100067617fcd4fd1154dbb78564d2a1d6cd2a 100644
--- a/src/shared/drivers/spi/SPIDefs.h
+++ b/src/shared/drivers/spi/SPIDefs.h
@@ -55,7 +55,7 @@ namespace SPI
 enum class Order : uint16_t
 {
     MSB_FIRST = 0,
-    LSB_FIRST = 0x80
+    LSB_FIRST = SPI_CR1_LSBFIRST
 };
 
 /**
@@ -69,13 +69,13 @@ enum class Order : uint16_t
 enum class ClockDivider : uint8_t
 {
     DIV_2   = 0x00,
-    DIV_4   = 0x08,
-    DIV_8   = 0x10,
-    DIV_16  = 0x18,
-    DIV_32  = 0x20,
-    DIV_64  = 0x28,
-    DIV_128 = 0x30,
-    DIV_256 = 0x38,
+    DIV_4   = SPI_CR1_BR_0,
+    DIV_8   = SPI_CR1_BR_1,
+    DIV_16  = SPI_CR1_BR_1 | SPI_CR1_BR_0,
+    DIV_32  = SPI_CR1_BR_2,
+    DIV_64  = SPI_CR1_BR_2 | SPI_CR1_BR_0,
+    DIV_128 = SPI_CR1_BR_2 | SPI_CR1_BR_1,
+    DIV_256 = SPI_CR1_BR
 };
 
 enum class Mode : uint8_t
@@ -83,11 +83,11 @@ enum class Mode : uint8_t
     ///< CPOL = 0, CPHA = 0 -> Clock low when idle, sample on first edge
     MODE_0 = 0,
     ///< CPOL = 0, CPHA = 1 -> Clock low when idle, sample on second edge
-    MODE_1 = 1,
+    MODE_1 = SPI_CR1_CPHA,
     ///< CPOL = 1, CPHA = 0 -> Clock high when idle, sample on first edge
-    MODE_2 = 2,
+    MODE_2 = SPI_CR1_CPOL,
     ///< CPOL = 1, CPHA = 1 -> Clock high when idle, sample on second edge
-    MODE_3 = 3
+    MODE_3 = SPI_CR1_CPOL | SPI_CR1_CPHA
 };
 
 enum class WriteBit
diff --git a/src/shared/utils/ClockUtils.h b/src/shared/utils/ClockUtils.h
index 3bcad0084cc3f56386f41a6a8399589afcbb6b2a..7d6a021f08a59213fc342b920c22dd5c8253aef1 100644
--- a/src/shared/utils/ClockUtils.h
+++ b/src/shared/utils/ClockUtils.h
@@ -233,7 +233,7 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
                 RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
                 break;
 #endif
-// On some micrcontrollers like the stm32f205, CCMDATARAM_BASE is defined
+// On some microcontrollers like the stm32f205, CCMDATARAM_BASE is defined
 // incorrectly. So we check for the macro bit
 #ifdef RCC_AHB1ENR_CCMDATARAMEN
             case CCMDATARAM_BASE: