From 351dc72853f213902e616167554ba72fa2d2a1e5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Niccol=C3=B2=20Betto?= <niccolo.betto@skywarder.eu> Date: Sun, 15 Sep 2024 15:04:36 +0200 Subject: [PATCH] [BSP][Lyra] Set SD clock to 2 Mhz The previous setting of 6 Mhz was not enough to fix the SD logging issues Lyra boards were experiencing. --- src/bsps/stm32f767zi_lyra_biscotto/config/board_settings.h | 4 ++-- src/bsps/stm32f767zi_lyra_motor/config/board_settings.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/bsps/stm32f767zi_lyra_biscotto/config/board_settings.h b/src/bsps/stm32f767zi_lyra_biscotto/config/board_settings.h index 5a18f96a5..36c176972 100644 --- a/src/bsps/stm32f767zi_lyra_biscotto/config/board_settings.h +++ b/src/bsps/stm32f767zi_lyra_biscotto/config/board_settings.h @@ -51,9 +51,9 @@ const unsigned int defaultSerialSpeed = 115200; static const unsigned char sdVoltage = 33; // Board powered @ 3.3V #define SD_SDMMC 1 // Select either SDMMC1 or SDMMC2 -// Disable 4bit wire mode and set speed to 6Mhz (48Mhz / (6 + 2)) +// Disable 4bit wire mode and set speed to 2Mhz (48Mhz / (22 + 2)) #define SD_ONE_BIT_DATABUS -#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 6 +#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 22 /// Analog supply voltage for ADC, DAC, Reset blocks, RCs and PLL #define V_DDA_VOLTAGE 3.3f diff --git a/src/bsps/stm32f767zi_lyra_motor/config/board_settings.h b/src/bsps/stm32f767zi_lyra_motor/config/board_settings.h index 5a18f96a5..36c176972 100644 --- a/src/bsps/stm32f767zi_lyra_motor/config/board_settings.h +++ b/src/bsps/stm32f767zi_lyra_motor/config/board_settings.h @@ -51,9 +51,9 @@ const unsigned int defaultSerialSpeed = 115200; static const unsigned char sdVoltage = 33; // Board powered @ 3.3V #define SD_SDMMC 1 // Select either SDMMC1 or SDMMC2 -// Disable 4bit wire mode and set speed to 6Mhz (48Mhz / (6 + 2)) +// Disable 4bit wire mode and set speed to 2Mhz (48Mhz / (22 + 2)) #define SD_ONE_BIT_DATABUS -#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 6 +#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 22 /// Analog supply voltage for ADC, DAC, Reset blocks, RCs and PLL #define V_DDA_VOLTAGE 3.3f -- GitLab