diff --git a/src/shared/utils/ClockUtils.h b/src/shared/utils/ClockUtils.h
index 996a1c712e5541af05411b19f0307f07f1fce534..0527a5b11e2432951f6abe85a462e05b235556f2 100644
--- a/src/shared/utils/ClockUtils.h
+++ b/src/shared/utils/ClockUtils.h
@@ -289,6 +289,15 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
 #endif
         }
 
+        // AHB3 peripherals
+        {
+#ifdef QSPI_BASE
+            case QSPI_BASE:
+                RCC->AHB3ENR |= RCC_AHB3ENR_QSPIEN;
+                break;
+#endif
+        }
+
         // APB1 peripherals
         {
 #ifdef TIM2_BASE
@@ -336,6 +345,12 @@ inline bool ClockUtils::enablePeripheralClock(void* peripheral)
                 RCC->APB1ENR |= RCC_APB1ENR_TIM14EN;
                 break;
 #endif
+// RTC register interface gate only on stm32f7 micro controllers
+#if defined(RTC_BASE) && defined(_ARCH_CORTEXM7_STM32F7)
+            case RTC_BASE:
+                RCC->APB1ENR |= RCC_APB1ENR_RTCEN;
+                break;
+#endif
 #ifdef WWDG_BASE
             case WWDG_BASE:
                 RCC->APB1ENR |= RCC_APB1ENR_WWDGEN;
@@ -650,6 +665,15 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral)
 #endif
         }
 
+        // AHB3 peripherals
+        {
+#ifdef QSPI_BASE
+            case QSPI_BASE:
+                RCC->AHB3ENR &= ~RCC_AHB3ENR_QSPIEN;
+                break;
+#endif
+        }
+
         // APB1 peripherals
         {
 #ifdef TIM2_BASE
@@ -697,6 +721,12 @@ inline bool ClockUtils::disablePeripheralClock(void* peripheral)
                 RCC->APB1ENR &= ~RCC_APB1ENR_TIM14EN;
                 break;
 #endif
+// RTC register interface gate only on stm32f7 micro controllers
+#if defined(RTC_BASE) && defined(_ARCH_CORTEXM7_STM32F7)
+            case RTC_BASE:
+                RCC->APB1ENR &= ~RCC_APB1ENR_RTCEN;
+                break;
+#endif
 #ifdef WWDG_BASE
             case WWDG_BASE:
                 RCC->APB1ENR &= ~RCC_APB1ENR_WWDGEN;
diff --git a/src/tests/boards/test-qspi-flash.cpp b/src/tests/boards/test-qspi-flash.cpp
index 700bf2fcea98948a1f429ffaee5e7769fc567483..293ed82149aec98b1a017ddaafcad681225191fa 100644
--- a/src/tests/boards/test-qspi-flash.cpp
+++ b/src/tests/boards/test-qspi-flash.cpp
@@ -29,6 +29,7 @@
 #include <utils/ClockUtils.h>
 
 using namespace miosix;
+using namespace Boardcore;
 
 /**
  * QSPI Flash pins
@@ -73,8 +74,7 @@ int main()
     flash_io3.alternateFunction(9);
     flash_io3.speed(Speed::_100MHz);
 
-    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOFEN;
-    RCC->AHB3ENR |= RCC_AHB3ENR_QSPIEN;
+    ClockUtils::enablePeripheralClock((QUADSPI_TypeDef*)QSPI_BASE);
 
     RCC_SYNC();
 
diff --git a/src/tests/test-rtc.cpp b/src/tests/test-rtc.cpp
index c1df7512dcf0a82615bf56cd16891b4a8ab515ba..e70bccbd7e9e80c929bf600305fa0bfc0b7c152d 100644
--- a/src/tests/test-rtc.cpp
+++ b/src/tests/test-rtc.cpp
@@ -1,5 +1,5 @@
-/* Copyright (c) 2015-2017 Skyward Experimental Rocketry
- * Author: Luca Erbetta
+/* Copyright (c) 2023 Skyward Experimental Rocketry
+ * Author: Alberto Nidasio
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy
  * of this software and associated documentation files (the "Software"), to deal
@@ -30,8 +30,10 @@
 // PA15 -> OSC32_OUT
 
 #include <miosix.h>
+#include <utils/ClockUtils.h>
 
 using namespace miosix;
+using namespace Boardcore;
 
 typedef struct RTC_Date
 {
@@ -55,8 +57,9 @@ int main()
     }
 
     // Enable clock to RTC and PWR peripherals
-    RCC->APB1ENR |= RCC_APB1ENR_RTCEN;
-    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    ClockUtils::enablePeripheralClock((RTC_TypeDef*)RTC_BASE);
+    ClockUtils::enablePeripheralClock((PWR_TypeDef*)PWR_BASE);
+
     RCC_SYNC();
 
     // Disable backup domain write protection