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miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h 100755 → 100644
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miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h 100755 → 100644
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miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h 100755 → 100644
View file @ a52d94ac
......@@ -8,41 +8,23 @@
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F0xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
......@@ -69,8 +51,14 @@
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
/** Uncomment the line below according to the target STM32 device used in your application.
* stm32f0xxxx.h file contains:
* - All the peripheral register's definitions, bits definitions and memory mapping for STM32F0xxxx devices
* - IRQ channel definition
* - Peripheral memory mapping and physical registers address definition
* - Peripheral pointer declaration and driver header file inclusion
* - Product miscellaneous configuration: assert macros, …
* Note: These CMSIS drivers (stm32f0xxxx.h) are always supporting features of the sub-family's superset.
*/
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
......@@ -84,7 +72,7 @@
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F048xx */ /*!< STM32F048xx Devices (STM32F048xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
......@@ -96,6 +84,10 @@
/* #define STM32F091xC */ /*!< STM32F091xB, STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory ranges between 128 and 256 Kbytes) */
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
#endif
/* Legacy aliases */
#if defined (STM32F048x6)
#define STM32F048xx
#endif /* STM32F048x6 */
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
......@@ -110,11 +102,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.3.3
* @brief CMSIS Device version number V2.3.7
*/
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_SUB2 (0x07) /*!< [15:8] sub2 version */
#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\
......@@ -174,21 +166,21 @@
*/
typedef enum
{
RESET = 0,
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
......@@ -213,6 +205,45 @@ typedef enum
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/* Use of interrupt control for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
SET_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
CLEAR_BIT((REG), (BIT)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t primask; \
primask = __get_PRIMASK(); \
__set_PRIMASK(1); \
MODIFY_REG((REG), (CLEARMSK), (SETMASK)); \
__set_PRIMASK(primask); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) ATOMIC_SET_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT) \
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
/**
* @}
......@@ -236,7 +267,3 @@ typedef enum
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h 100755 → 100644
View file @ a52d94ac
......@@ -6,33 +6,15 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
......@@ -118,4 +100,4 @@ extern void SystemCoreClockUpdate(void);
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
miosix/arch/common/CMSIS/Device/ST/STM32F0xx/LICENSE.md 0 → 100644
View file @ a52d94ac
Apache License
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http://www.apache.org/licenses/
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<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
Notes for STM32F0xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
2016 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.3 / 25-August-2017<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-weight: normal;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Remove&nbsp;</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">support of </span><span style="font-family: Verdana; font-size: 10pt;">Atollic TrueSTUDIO STM32 (TrueSTUDIO) </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">toolchain.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-weight: normal;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Performance improvement of the startup code for GCC.<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.2 / 07-April-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename </span><span style="font-size: 10pt; font-family: Verdana;">GPIO_AFRH&nbsp;and GPIO_AFRL bitfields for alignment with all STM32 series.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add macro definition : IS_TIM_ADVANCED.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename RTC_CR register bit definition to be aligned with STM32F0xx Reference Manual : RTC_CR_BCK ==&gt; RTC_CR_BKP<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.1 / 04-November-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add TIM6_IRQHandler in vectors table for </span><span style="font-size: 10pt; font-family: Verdana;">STM32F030x8 devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.3.0 / 27-May-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;"></span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">General updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Updated CMSIS Device compliancy with MISRA C 2004 rules:</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.5 (bitwise operators ~ and &lt;&lt;).</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">MISRA C 2004 rule 10.6 </span><span style="font-size: 10pt; font-family: Verdana;">('U' suffix applied to all constants of 'unsigned' type)</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">U</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">pdated system_stm32f3xx.h/.c files:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Added AHBPrescTable definition as external.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Added APBPrescTable definition&nbsp;as external.</span></li></ul></ul></ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">EXTI updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added definitions of bit 31 in EXTI registers for STM32F04x, STM32F078xx and STM32F098xx devices.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">I2C updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added IS_I2C_WAKEUP_FROMSTOP_INSTANCE definition for I2C instances supporting Wakeup from Stop mode</span><span style="font-size: 10pt; font-family: Verdana;">.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">I2S updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Removed SPI_I2S prescaler register not supported by&nbsp;STM32F030x6 and&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">STM32F030x8 devices.</span><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RCC updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added missing RCC_CFGR_PLLNODIV definition for STM32F030x4/6 devices.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">RTC updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Removed cast from RTC_BKP_NUMBER definition.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">SYSCFG updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Renamed SYSCFG_CFGR1_IRDA_ENV_SEL bit definitions to SYSCFG_CFGR1_IR_MOD for SYSCFG_CFGR1 register.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">TIM updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE definition.</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Added IS_TIM_ETR_INSTANCE definition.<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">UART updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Renamed IS_UART_WAKEUP_INSTANCE&nbsp;to IS_UART_WAKEUP_FROMSTOP_INSTANCE.</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">USART updates</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Defined USART_ISR_RWU bit for all STM32F0xx devices.</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.3 / 29-January-2016</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Added mention to STM32F091xB mcus missing in the list of mcus of stm32f0xx.h.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated CMSIS Device compliancy with MISRA C 2004 rule 10.6.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated CMSIS Device compliancy with MISRA C 2004 rule 5.1.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added HSI48_VALUE definition in system_stm32f0xx.c file.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Put variable AHBPrescTable as external in system_stm32f0xx.h.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added channel selection bit definitions for for DMA1_CSELR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Used RCC_CFGR_MCOSEL as reference in all the families.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed RCC_CFGR_MCOSEL_PLL to RCC_CFGR_MCOSEL_PLL_DIV2 for alignment between all families.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated EWUPx pins defintions for STM32F042x6 and STM32F048xx devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added FLASHSIZE_BASE and UID_BASE defines.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added missing bits definition for RTC_TAFCR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added missing bits definition for I2C_OAR2 register (I2C_OAR2 mask values).</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Renamed I2C_CR1_DFN to I2C_CR1_DNF bit definition for I2C_CR1 register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed __IO or __I on constant table declaration.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Used default DAC instance naming DAC1 in macro IS_DAC_ALL_INSTANCE().</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned EXTI registers Bits naming between all families.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned WWDG registers Bits naming between all families.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Aligned COMP common instance definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected
CRC defines: Replaced POL field by RESERVED3 for STM32F030x6,
STM32F030x8, STM32F031x6, STM32F038xx, STM32F042x6, STM32F048xx devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected CRC defines: </span><span style="font-size: 10pt; font-family: Verdana;">Removed Bit definitions related to Polynomial in CRC_CR and CRC_POL registers for STM32F030xC.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Updated for ADC: removed conditions on CCR_TS definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected SYSCFG_RTC_WAKEUP and SYSCFG_RTC_ALRA Bits definition for SYSCFG_xxx ISR Wrapper register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Added ADC_CHSELR_CHSEL Bit definition for ADC_CHSELR register.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed RCC_CSR_V18PWRRSTF Bit definition for STM32F0x8xx devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected USART defines for STM32F030xx, STM32F070xx devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE macro definition.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Adapted IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE to device feature support.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed IS_UART_DRIVER_ENABLE_INSTANCE definition for&nbsp; STM32F030x8, STM32F030xC and STM32F070xB devices.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Corrected FLASH_OBR_nBOOT0 value.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed Synchronous mode support on USART5/6 for STM32F030xC.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Removed HW Flow Control support on USART5/6/7/8 for STM32F091xC.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.2 / 26-June-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Add missing WUT bits in EXTI_IMR/EMR/RTSR/FTSR/PR/SWIER for different IT lines.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add preprocessor compilation switch #define STM32F0 in stm32f0xx.h.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Correct FLASH_KEY name difference between&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">STM32F0</span><span style="font-size: 10pt; font-family: Verdana;"> and </span><span style="font-size: 10pt; font-family: Verdana;">STM32F3.</span></li><li><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;">Remove RCC_CFGR3_USART2SW from CMSIS, present only for STM32F07x and STM32F09x.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Modify EXTI/COMP defines from uint16 to uint32.<br></span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add missing definitions of EXTI_IMR_MR31 used by PWREx in stm32f042x6 and stm32f048xx files.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add FLASH_BANK1_END defines.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Remove WRP defines for few defines under devices swicthes.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add FLASH_OBR_RAM_PARITY_CHECK and FLASH_OBR_BOOT_SEL CMSIS files.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.1 / 09-January-2015</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c: replace wrong compilation switch</span><span style="font-size: 10pt; font-family: Verdana;"> STM32F078xB&nbsp;by STM32F078xx.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">stm32F070xb.h: correct wrong DMA remap mask value for STM32f070xB.</span></li><li><span style="font-family: Verdana; font-size: 10pt;">stm32F070xb.h,
</span><span style="font-family: Verdana; font-size: 10pt;">stm32F070x6.h,
</span><span style="font-family: Verdana; font-size: 10pt;">stm32F030xc.h</span><span style="font-family: Verdana; font-size: 10pt;">: add missing macro
IS_UART_DRIVER_ENABLE_INSTANCE()</span>
</li><li><span style="font-family: Verdana; font-size: 10pt;">stm32F070xb.h, </span><span style="font-family: Verdana; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">stm32F030xc.h: add missing RTC
periodic Wakeup register &amp; bits description</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.2.0 / 05-December-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="font-size: 10pt; font-family: Verdana;">Add CMSIS files for new STM32F0 value line devices: <span style="font-weight: bold;">STM32F030xC</span> and </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32F070x6</span>/<span style="font-weight: bold;">xB</span>.</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Add macro to check AF capability of gpio instance</span></li><li><span style="font-size: 10pt; font-family: Verdana;">uint32_t alignement&nbsp;done on all Peripheral registers structures &amp; bits definition</span></li><li><span style="font-size: 10pt; font-family: Verdana;">stm32f091xc.h: DMA channel remap register&nbsp;renamed for compatibility with other STM32 devices</span></li><li><span style="font-size: 10pt; font-family: Verdana;">startup_stm32f042x6.s&nbsp;&amp;&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">startup_stm32f070x6.s:&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">fix boot issue&nbsp; </span><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: rgb(0, 32, 82);" lang="EN-US"><span style="color: rgb(0, 6, 16);"></span> </span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.1.0 / 03-October-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul><li><span style="font-size: 10pt; font-family: Verdana;">Add new CMSIS files for STM32F091xc&nbsp;and </span><span style="font-size: 10pt; font-family: Verdana;">STM32F098xx products</span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li><span style="font-size: 10pt; font-family: Verdana;">VDDIO2 IRQ missing in F07xx/F09xx/F04xx product</span></li><li><span style="font-size: 10pt; font-family: Verdana;">IS_DAC_CHANNEL_INSTANCE macro removed as unused<br></span></li><li><span style="font-size: 10pt; font-family: Verdana;">uint32_t partial alignement&nbsp;done on peripheral Bit definition &amp; register structure</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Bit definition name error for DMA_RMPCR1 register of STM32F091xC</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Remove PDV feature on REGoff part</span></li><li><span style="font-size: 10pt; font-family: Verdana;">Remove POSITION_VAL macro as it uses RBIT, CLZ instructions, that are not supported by Cortex-M0<br></span></li><li><span style="font-size: 10pt; font-family: Verdana;">GPIOS BSRR regsiter should not be split in BSRRH/BSRRL<br></span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.1 / 18-June-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">General</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new macros&nbsp;</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IS_GPIO_LOCK_INSTANCE</span> to check GPIO port with lock capability</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IS_UART_HALFDUPLEX_INSTANCE</span>,
<span style="font-style: italic;">IS_UART_LIN_INSTANCE</span> and <span style="font-style: italic;">IS_UART_WAKEUP_INSTANCE</span> to &nbsp;check
&nbsp;the UART instance supported features.</span></li></ul></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">STM32F042x8 and </span><span style="font-size: 10pt; font-family: Verdana;">STM32F048xx </span><span style="font-size: 10pt; font-family: Verdana;">update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">DMA1_Channel4_5_6_7_IRQn</span> to <span style="font-style: italic;">DMA1_Channel4_5</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">_IRQn</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC1_COMP_IRQn</span> to <span style="font-style: italic;">ADC1_IRQn</span></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Remove SPI2 instance<br></span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">STM32F051x8, STM32F058xx, </span><span style="font-size: 10pt; font-family: Verdana;">STM32F071xB, STM32F072xB and STM32F078xx update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Fix COMP2 instance base address</span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Add new macro </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">IS_COMP_DAC1SWITCH_INSTANCE</span> to check COMP instance with switch of DAC1 channel1 output to non inverting input</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">STM32F051x8 and STM32F058xx</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">DMA1_Channel4_5_6_7_IRQn</span> to <span style="font-style: italic;">DMA1_Channel4_5</span></span><span style="font-size: 10pt; font-family: Verdana; font-style: italic;">_IRQn</span></li></ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">STM32F078xx</span><span style="font-size: 10pt; font-family: Verdana;">&nbsp;update</span></li><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Remove CAN peripheral description</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V2.0.0 / 28-May-2014</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><b><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></b><span style="font-size: 10pt; font-family: Verdana;">Major update
based on STM32Cube specification: </span><span style="font-size: 10pt; font-family: Verdana;">new CMSIS device files
release dedicated to </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F030x4/x6, STM32F030x8, STM32F031x4/x6, STM32F051x4/x6/x8, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F071x8/xB, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F042x4/x6,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F072x8/xB, </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"></span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F038xx,&nbsp;</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">STM32F048xx,</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;"> STM32F058xx and STM32F078xx
</span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;; font-weight: bold;">devices.</span></li><li style="font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">This version has to be used for </span><span style="font-size: 10pt; font-family: Verdana;">STM32CubeF0</span><span style="font-size: 10pt; font-family: Verdana;"> based development although files can be used independently too.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 22-November-2013</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F030 devices definition: <br>
</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the&nbsp;<span style="font-style: italic;">STM32F030X8 and STM32FO30X6</span> defines and replace them with the&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F030 define</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F030</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to support <span style="font-style: italic;">STM32F030</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the&nbsp;startup files </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030x8.s and startup_stm32f030x6.s</span> and replace them by&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030.s</span></span><span style="font-size: 10pt; font-family: Verdana;">, for EWARM, MDK-ARM and Truestudio supported compilers</span></li></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 01-August-2013</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support of <span style="font-weight: bold; font-style: italic;">STM32F030&nbsp; devices</span> (STM32F030x8 and STM32F030x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F0xx devices definition: <br>
</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definition <span style="font-style: italic;">STM32F030X8 and STM32FO30X6</span> for </span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F030 devices</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F030</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to support <span style="font-style: italic;">STM32F030</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup files, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030x8.s and startup_stm32f030x6.s</span>, for EWARM, MDK-ARM and Truestudio supported compilers</span></li></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 31-July-2013</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Extend <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span> and <span style="font-style: italic;">HSI_STARTUP_TIMEOUT</span> values to 0x5000</span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-May-2013</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support of <span style="font-weight: bold; font-style: italic;">STM32F0xx Low-density devices</span> (STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F0xx devices definition: <br>
</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Define for <span style="font-style: italic;">STM32F0xx Medium-density devices</span> changed from <span style="font-style: italic;">STM32F0XX</span> to <span style="font-style: italic;">STM32F0XX_MD</span><br>
</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definition <span style="font-style: italic;">STM32F0XX_LD</span> for </span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F0xx Low-density devices</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F0XX_LD</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new bits definition</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_CFGR</span></span><span style="font-size: 10pt; font-family: Verdana;"> register</span><span style="font-size: 10pt; font-family: Verdana;">: <span style="font-style: italic;">MCOPRE[0:2]</span> and <span style="font-style: italic;">PLLNODIV</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SYSCFG_CFGR1</span> register: <span style="font-style: italic;">FMP_I2C1</span>, <span style="font-style: italic;">FMP_PA9</span> and <span style="font-style: italic;">FMP_PA10</span><br>
</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to reset new bits added in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_CFGR</span></span><span style="font-size: 10pt; font-family: Verdana;"> register</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup files, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f0xx_ld.s</span>, for the supported compilers</span></li></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 13-July-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix issue with gcc_ride7 startup file </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-April-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add reference to STM32F050xx (Flash memory up to 32 Kbytes) and STM32F051xx (</span><span style="font-size: 10pt; font-family: Verdana;">Flash memory up to 64 Kbytes</span><span style="font-size: 10pt; font-family: Verdana;">) devices</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC register bits definition: remove reference to Tamper3</span></li></ul></ul>
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0
/ 04-September-2012<o:p></o:p></span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes<o:p></o:p></span></u></b></p>
<ul style="margin-top: 0cm;" type="square">
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First
official release for&nbsp;</span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32F30x</span>
devices (Standard Library)</span></li>
</ul>
<span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
<ul style="margin-top: 0in;" type="disc">
</ul>
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
<div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistribution
and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:</span><br>
</font>
<ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
of source code must retain the above copyright notice, this list of
conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the
documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the
name of STMicroelectronics nor the names of its contributors may be
used to endorse or promote products derived</span></font><small><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> from this software without specific prior written permission.</span></small><br></li></ol><font size="-1">
<span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
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complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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\ No newline at end of file
miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c 100755 → 100644
View file @ a52d94ac
......@@ -18,55 +18,19 @@
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. This file configures the system clock as follows:
*=============================================================================
* Supported STM32F0xx device
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 8000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
......@@ -131,11 +95,15 @@
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock there is no need to
call the 2 first functions listed above, since SystemCoreClock variable is
updated automatically.
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
#ifdef SYSCLK_FREQ_32MHz
uint32_t SystemCoreClock = 32000000;
#else
uint32_t SystemCoreClock = 8000000;
#endif
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
......@@ -157,70 +125,39 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
*/
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @brief Setup the microcontroller system
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001U;
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80CU;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80CU;
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFFU;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFFU;
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
#elif defined (STM32F071xB)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
#elif defined (STM32F051x8) || defined (STM32F058xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
#elif defined (STM32F042x6) || defined (STM32F048xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
#elif defined (STM32F070x6) || defined (STM32F070xB)
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
/* Set default USB clock to PLLCLK, since there is no HSI48 */
RCC->CFGR3 |= (uint32_t)0x00000080U;
//TODO: support more clocking options
#ifndef RUN_WITH_HSI
#error "Implement HSE support"
#endif
#ifdef SYSCLK_FREQ_32MHz
RCC->CR |= RCC_CR_HSION;
while((RCC->CR & RCC_CR_HSIRDY)==0) ;
RCC->CR &= ~RCC_CR_PLLON;
while(RCC->CR & RCC_CR_PLLRDY) ;
RCC->CFGR &= ~RCC_CFGR_SW; //Selects HSI
RCC->CFGR = RCC_CFGR_PLLMUL4 //4*8=32MHz
| RCC_CFGR_PLLSRC_HSI_PREDIV;
RCC->CR |= RCC_CR_PLLON;
while((RCC->CR & RCC_CR_PLLRDY)==0) ;
FLASH->ACR &= ~FLASH_ACR_LATENCY;
FLASH->ACR |= 1; //1 wait state for freq > 24MHz
RCC->CFGR |= RCC_CFGR_SW_PLL;
#else
#warning "No target selected"
//Run @ 8MHz
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
/* Disable all interrupts */
RCC->CIR = 0x00000000U;
/* NOTE :SystemInit(): This function is called at startup just after reset and
before branch to main program. This call is made inside
the "startup_stm32f0xx.s" file.
User can setups the default system clock (System clock source, PLL Multiplier
and Divider factors, AHB/APBx prescalers and Flash settings).
*/
}
/**
......@@ -244,14 +181,20 @@ void SystemInit(void)
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***)
*
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
* 48 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
......@@ -286,13 +229,13 @@ void SystemCoreClockUpdate (void)
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
}
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
{
/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
}
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
......@@ -331,5 +274,3 @@ void SystemCoreClockUpdate (void)
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
miosix/arch/common/CMSIS/Device/ST/STM32F10x/Source/Templates/system_stm32f10x.c
View file @ a52d94ac
......@@ -625,10 +625,6 @@ static void SetSysClockTo24(void)
{
HSEStatus = (uint32_t)0x00;
}
#else
#ifndef STM32F10X_MD_VL
#warning Untested configuration
#endif
#endif //RUN_WITH_HSI //By TFT
if (HSEStatus == (uint32_t)0x01)
......
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h
View file @ a52d94ac
Source diff could not be displayed: it is too large. Options to address this: view the blob.
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h
View file @ a52d94ac
Source diff could not be displayed: it is too large. Options to address this: view the blob.
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f215xx.h
View file @ a52d94ac
Source diff could not be displayed: it is too large. Options to address this: view the blob.
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f217xx.h
View file @ a52d94ac
Source diff could not be displayed: it is too large. Options to address this: view the blob.
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h
View file @ a52d94ac
......@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f2xx.h
* @author MCD Application Team
* @version V2.0.1
* @date 25-March-2014
* @brief CMSIS STM32F2xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
......@@ -18,29 +16,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
......@@ -64,16 +46,25 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F2)
#define STM32F2
#endif /* STM32F2 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F205xx) && !defined (STM32F215xx) && !defined (STM32F207xx) && !defined (STM32F217xx)
/* #define STM32F205xx */ /*!< STM32Fxx Devices */
/* #define STM32F215xx */ /*!< STM32Fxx Devices */
/* #define STM32F207xx */ /*!< STM32Fxx Devices */
/* #define STM32F217xx */ /*!< STM32Fxx Devices */
/* #define STM32F205xx */ /*!< STM32F205RG, STM32F205VG, STM32F205ZG, STM32F205RF, STM32F205VF, STM32F205ZF,
STM32F205RE, STM32F205VE, STM32F205ZE, STM32F205RC, STM32F205VC, STM32F205ZC,
STM32F205RB and STM32F205VB Devices */
/* #define STM32F215xx */ /*!< STM32F215RG, STM32F215VG, STM32F215ZG, STM32F215RE, STM32F215VE and STM32F215ZE Devices */
/* #define STM32F207xx */ /*!< STM32F207VG, STM32F207ZG, STM32F207IG, STM32F207VF, STM32F207ZF, STM32F207IF,
STM32F207VE, STM32F207ZE, STM32F207IE, STM32F207VC, STM32F207ZC and STM32F207IC Devices */
/* #define STM32F217xx */ /*!< STM32F217VG, STM32F217ZG, STM32F217IG, STM32F217VE, STM32F217ZE and STM32F217IE Devices */
#endif
......@@ -90,16 +81,16 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.0.1
* @brief CMSIS Device version number V2.2.5
*/
#define __STM32F2xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F2xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F2xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F2xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
#define __STM32F2xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F2xx_CMSIS_VERSION_SUB1 (0x02U) /*!< [23:16] sub1 version */
#define __STM32F2xx_CMSIS_VERSION_SUB2 (0x05U) /*!< [15:8] sub2 version */
#define __STM32F2xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F2xx_CMSIS_VERSION ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F2xx_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F2xx_CMSIS_VERSION))
/**
* @}
......@@ -130,21 +121,21 @@
*/
typedef enum
{
RESET = 0,
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
......@@ -176,6 +167,9 @@ typedef enum
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f2xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
......
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h 100644 → 100755
View file @ a52d94ac
......@@ -2,35 +2,17 @@
******************************************************************************
* @file system_stm32f2xx.h
* @author MCD Application Team
* @version V2.0.1
* @date 25-March-2014
* @brief CMSIS Cortex-M3 Device System Source File for STM32F2xx devices.
******************************************************************************
****************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
* <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
* All rights reserved.</center></h2>
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
......@@ -75,6 +57,8 @@
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
......
miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c
View file @ a52d94ac
......@@ -2,8 +2,6 @@
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V2.0.1
* @date 25-March-2014
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
*
* This file provides two functions and one global variable to be called from
......@@ -23,29 +21,13 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
* All rights reserved.</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
......@@ -65,11 +47,17 @@
//By TFT: was #include "stm32f4xx_hal.h", but the specific chip is #defined in
//arch_registers_impl.h
#include "interfaces/arch_registers.h"
//By TFT: the .h file for the chip used to define this
#define HSI_VALUE 16000000
//By TFT: was in the old stm32f4xx.h
#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500)
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
......@@ -95,15 +83,38 @@
#define DATA_IN_ExtSRAM
#endif //__ENABLE_XRAM
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#ifndef _BOARD_SONY_NEWMAN //By TFT: the smartwatch has a bootloader
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#else //_BOARD_SONY_NEWMAN
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
//By TFT -- begin
// the smartwatch has a bootloader
#ifdef _BOARD_SONY_NEWMAN
#define USER_VECT_TAB_ADDRESS
#define VECT_TAB_BASE_ADDRESS FLASH_BASE
#define VECT_TAB_OFFSET 0x40000
#endif //_BOARD_SONY_NEWMAN
//By TFT -- end
//By TFT -- begin
// this was backported from an older version. Now this code seems to be
......@@ -137,7 +148,7 @@
* @{
*/
/* This varaible can be updated in Three ways :
/* This variable can be updated in Three ways :
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
......@@ -146,8 +157,8 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
/**
* @}
*/
......@@ -178,25 +189,6 @@ static void SetSysClock(void);
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
......@@ -205,12 +197,10 @@ void SystemInit(void)
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
......@@ -238,10 +228,10 @@ void SystemInit(void)
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
* (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
* depends on the application requirements), user has to ensure that HSE_VALUE
* is same as the real frequency of the crystal used. Otherwise, this function
* may have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
......@@ -393,12 +383,6 @@ static void SetSysClock(void)
}
// By TFT -- end
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
......@@ -411,116 +395,66 @@ static void SetSysClock(void)
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
RCC->AHB1ENR |= 0x00000078;
RCC_SYNC();
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
//GPIOD->AFR[1] = 0xcc0ccccc;
GPIOD->AFR[1] = 0xcccccccc; //By TFT: enable PD13 as A18
GPIOD->AFR[0] = 0x00CCC0CC;
GPIOD->AFR[1] = 0xCCCCCCCC;
/* Configure PDx pins in Alternate function mode */
//GPIOD->MODER = 0xa2aa0a0a;
GPIOD->MODER = 0xaaaa0a0a; //By TFT: enable PD13 as A18
GPIOD->MODER = 0xAAAA0A8A;
/* Configure PDx pins speed to 100 MHz */
//GPIOD->OSPEEDR = 0xf3ff0f0f;
GPIOD->OSPEEDR = 0xffff0f0f; //By TFT: enable PD13 as A18
GPIOD->OSPEEDR = 0xFFFF0FCF;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
//GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[0] = 0xc00cc0cc; //By TFT: enable PE3,PE4 as A19,A20
GPIOE->AFR[1] = 0xcccccccc;
GPIOE->AFR[0] = 0xC00CC0CC;
GPIOE->AFR[1] = 0xCCCCCCCC;
/* Configure PEx pins in Alternate function mode */
//GPIOE->MODER = 0xaaaa800a;
GPIOE->MODER = 0xaaaa828a; //By TFT: enable PE3,PE4 as A19,A20
GPIOE->MODER = 0xAAAA828A;
/* Configure PEx pins speed to 100 MHz */
//GPIOE->OSPEEDR = 0xffffc00f;
GPIOE->OSPEEDR = 0xffffc3cf; //By TFT: enable PE3,PE4 as A19,A20
GPIOE->OSPEEDR = 0xFFFFC3CF;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
GPIOF->AFR[0] = 0x00CCCCCC;
GPIOF->AFR[1] = 0xCCCC0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
GPIOF->MODER = 0xAA000AAA;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
GPIOF->OSPEEDR = 0xFF000FFF;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
GPIOG->AFR[0] = 0x00CCCCCC;
GPIOG->AFR[1] = 0x000000C0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
GPIOG->MODER = 0x00085AAA;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
GPIOG->OSPEEDR = 0x000CAFFF;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/*--FSMC Configuration -------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
RCC->AHB3ENR |= 0x00000001;
RCC_SYNC();
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
FSMC_Bank1->BTCR[2] = 0x00001011;
FSMC_Bank1->BTCR[3] = 0x00000201;
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
}
#endif /* DATA_IN_ExtSRAM */
......
miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
View file @ a52d94ac
......@@ -98,6 +98,36 @@
This value must be a multiple of 0x200. */
/******************************************************************************/
// By Alberto Nidasio and TFT -- begin
#if (HSE_VALUE % 2000000) == 0
//PLL input frequency set to 2MHz to reduce jitter as suggested by the datasheet.
const unsigned int PLL_M=HSE_VALUE/2000000;
#ifdef SYSCLK_FREQ_216MHz
const unsigned int PLL_Q=9;
const unsigned int PLL_R=7;
const unsigned int PLL_N=216;
const unsigned int PLL_P=2;
#else
#error Clock not selected
#endif
#else // HSE_VALUE not divisible by 2MHz
//PLL Input frequency set to 1MHz
const unsigned int PLL_M=HSE_VALUE/1000000;
#ifdef SYSCLK_FREQ_216MHz
const unsigned int PLL_Q=9;
const unsigned int PLL_R=7;
const unsigned int PLL_N=432;
const unsigned int PLL_P=2;
#else
#error Clock not selected
#endif
#endif // HSE_VALUE divisibility check
// By Alberto Nidasio and TFT -- end
/**
* @}
*/
......@@ -292,15 +322,6 @@ void SetSysClk(void)
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
/************************* PLL Parameters for clock at 216MHz******************/
//By TFT: the original settings were for a boar with a 25MHz clock, not 8MHz
//They also mention a PLL_R that doesn't exist in the datasheet and maps to
//reseved bits. Finally, the PLL input frequency was set to 2MHz to reduce
//PLL jitter as suggested by the datasheet.
//uint32_t PLL_M = 25,PLL_Q = 9, PLL_R = 7, PLL_N = 432, PLL_P = 2;
uint32_t PLL_M = 4,PLL_Q = 9, PLL_R = 7, PLL_N = 216, PLL_P = 2;
/* Enable Power Control clock */
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
......
miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Include/stm32l4r9xx.h 0 → 100644
View file @ a52d94ac
Source diff could not be displayed: it is too large. Options to address this: view the blob.
miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c
View file @ a52d94ac
......@@ -209,9 +209,6 @@ static void SetSysClock(void);
static void SetSysClockTo80(void);
#endif
static uint32_t EnableHSE();
static uint32_t EnableHSI();
/**
* @}
*/
......@@ -377,6 +374,8 @@ void SystemCoreClockUpdate(void)
// Added by silseva
#ifdef RUN_WITH_HSE
/**
* @brief Activates HSE oscillator and waits until is ready
* @param None
......@@ -409,6 +408,7 @@ static uint32_t EnableHSE()
return HSEStatus;
}
#elif defined(RUN_WITH_HSI)
/**
* @brief Activates HSI oscillator and waits until is ready
......@@ -442,6 +442,8 @@ static uint32_t EnableHSI()
return HSIStatus;
}
#endif //RUN_WITH_HSI
/**
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
......@@ -549,7 +551,7 @@ static void SetSysClockTo24(void)
#ifdef RUN_WITH_HSE //By silseva
HSEStatus = EnableHSE();
#elif defined RUN_WITH_HSI
#elif defined(RUN_WITH_HSI)
HSEStatus = EnableHSI();
#endif //RUN_WITH_HSI
......
miosix/arch/common/core/atomic_ops_impl_cortexM0.h
View file @ a52d94ac
......@@ -38,56 +38,66 @@
*/
#include "interfaces/arch_registers.h"
#include <kernel/kernel.h>
namespace miosix {
// Can't include kernel.h as it would cause an include loop
void disableInterrupts();
void enableInterrupts();
inline int atomicSwap(volatile int *p, int v)
{
InterruptDisableLock dLock;
disableInterrupts();
int result = *p;
*p = v;
enableInterrupts();
asm volatile("":::"memory");
return result;
}
inline void atomicAdd(volatile int *p, int incr)
{
InterruptDisableLock dLock;
disableInterrupts();
*p += incr;
enableInterrupts();
asm volatile("":::"memory");
}
inline int atomicAddExchange(volatile int *p, int incr)
{
InterruptDisableLock dLock;
disableInterrupts();
int result = *p;
*p += incr;
enableInterrupts();
asm volatile("":::"memory");
return result;
}
inline int atomicCompareAndSwap(volatile int *p, int prev, int next)
{
InterruptDisableLock dLock;
disableInterrupts();
int result = *p;
if(*p == prev) *p = next;
enableInterrupts();
asm volatile("":::"memory");
return result;
}
inline void *atomicFetchAndIncrement(void * const volatile * p, int offset,
int incr)
{
InterruptDisableLock dLock;
volatile uint32_t *pt;
disableInterrupts();
void *result = *p;
if(result == 0) return 0;
pt = reinterpret_cast<uint32_t*>(result) + offset;
if(result == 0)
{
enableInterrupts();
return 0;
}
volatile uint32_t *pt = reinterpret_cast<uint32_t*>(result) + offset;
*pt += incr;
enableInterrupts();
asm volatile("":::"memory");
return result;
}
......
miosix/arch/common/core/interrupts.h
View file @ a52d94ac
......@@ -3,7 +3,7 @@
#ifdef _ARCH_ARM7_LPC2000
#include "interrupts_arm7.h"
#elif defined(_ARCH_CORTEXM0_STM32) || defined(_ARCH_CORTEXM3_STM32) \
#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
|| defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
|| defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
|| defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \
......@@ -13,11 +13,3 @@
#else
#error "Unknown arch"
#endif
// Cortex M0 and M0+ does not have some SCB registers, in order to avoid
// compilation issues a flag is defined to disable code that accesses to
// registers not present in these families
#if defined(_ARCH_CORTEXM0_STM32)
#define _ARCH_CORTEXM0
#endif