[SPI] Fixed transmission at low baudrates for the f7 spi busses on APB1

On stm32f7 boards when using SPI peripherals on the APB1 bus with clockdividers too high (so slower clock) the chip select (cs) pin would be set high again too early, before the transaction finishes.

The following screens are taken running test-spi for an stm32f767zi_nucleo target with a clock divider of DIV_256 on the SPI3. We can see how before the fix the cs in the last 6 transactions (the read/write registers methods) is released too early while in the fixed version the transaction finishes and then the cs is set.

Image of the previous version:

Image of the fixed version: