miosix/arch/cortexM3_stm32/stm32f100c8_vaisala_rs41/core/stage_1_boot.cpp → miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/core/stage_1_boot.cpp

@@ -270,9 +270,9 @@ void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
 #pragma weak I2C2_ER_IRQHandler = Default_Handler
 #pragma weak SPI1_IRQHandler = Default_Handler
 #pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_IRQHandler = Default_Handler
 #pragma weak EXTI15_10_IRQHandler = Default_Handler
 #pragma weak RTCAlarm_IRQHandler = Default_Handler
 #pragma weak CEC_IRQHandler = Default_Handler

miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/core/stage_1_boot.cpp

+
+#include "interfaces/arch_registers.h"
+#include "core/interrupts.h" //For the unexpected interrupt call
+#include "kernel/stage_2_boot.h"
+#include <string.h>
+
+/*
+ * startup.cpp
+ * STM32 C++ startup.
+ * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices).
+ * Supports interrupt handlers in C++ without extern "C"
+ * Developed by Terraneo Federico, based on ST startup code.
+ * Additionally modified to boot Miosix.
+ */
+
+/**
+ * Called by Reset_Handler, performs initialization and calls main.
+ * Never returns.
+ */
+void program_startup() __attribute__((noreturn));
+void program_startup()
+{
+    //Cortex M3 core appears to get out of reset with interrupts already enabled
+    __disable_irq();
+
+	//SystemInit() is called *before* initializing .data and zeroing .bss
+	//Despite all startup files provided by ST do the opposite, there are three
+	//good reasons to do so:
+	//First, the CMSIS specifications say that SystemInit() must not access
+	//global variables, so it is actually possible to call it before
+	//Second, when running Miosix with the xram linker scripts .data and .bss
+	//are placed in the external RAM, so we *must* call SystemInit(), which
+	//enables xram, before touching .data and .bss
+	//Third, this is a performance improvement since the loops that initialize
+	//.data and zeros .bss now run with the CPU at full speed instead of 8MHz
+    SystemInit();
+
+	//These are defined in the linker script
+	extern unsigned char _etext asm("_etext");
+	extern unsigned char _data asm("_data");
+	extern unsigned char _edata asm("_edata");
+	extern unsigned char _bss_start asm("_bss_start");
+	extern unsigned char _bss_end asm("_bss_end");
+
+    //Initialize .data section, clear .bss section
+    unsigned char *etext=&_etext;
+    unsigned char *data=&_data;
+    unsigned char *edata=&_edata;
+    unsigned char *bss_start=&_bss_start;
+    unsigned char *bss_end=&_bss_end;
+    memcpy(data, etext, edata-data);
+    memset(bss_start, 0, bss_end-bss_start);
+
+	//Move on to stage 2
+	_init();
+
+	//If main returns, reboot
+	NVIC_SystemReset();
+    for(;;) ;
+}
+
+/**
+ * Reset handler, called by hardware immediately after reset
+ */
+void Reset_Handler() __attribute__((__interrupt__, noreturn));
+void Reset_Handler()
+{
+    /*
+     * Initialize process stack and switch to it.
+     * This is required for booting Miosix, a small portion of the top of the
+     * heap area will be used as stack until the first thread starts. After,
+     * this stack will be abandoned and the process stack will point to the
+     * current thread's stack.
+     */
+    asm volatile("ldr r0,  =_heap_end          \n\t"
+                 "msr psp, r0                  \n\t"
+                 "movw r0, #2                  \n\n" //Privileged, process stack
+                 "msr control, r0              \n\t"
+                 "isb                          \n\t":::"r0");
+
+    program_startup();
+}
+
+/**
+ * All unused interrupts call this function.
+ */
+extern "C" void Default_Handler() 
+{
+    unexpectedInterrupt();
+}
+
+//System handlers
+void /*__attribute__((weak))*/ Reset_Handler();     //These interrupts are not
+void /*__attribute__((weak))*/ NMI_Handler();       //weak because they are
+void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
+void /*__attribute__((weak))*/ MemManage_Handler();
+void /*__attribute__((weak))*/ BusFault_Handler();
+void /*__attribute__((weak))*/ UsageFault_Handler();
+void /*__attribute__((weak))*/ SVC_Handler();
+void /*__attribute__((weak))*/ DebugMon_Handler();
+void /*__attribute__((weak))*/ PendSV_Handler();
+void /*__attribute__((weak))*/ SysTick_Handler();
+
+//Interrupt handlers
+void __attribute__((weak)) WWDG_IRQHandler();
+void __attribute__((weak)) PVD_IRQHandler();
+void __attribute__((weak)) TAMPER_IRQHandler();
+void __attribute__((weak)) RTC_IRQHandler();
+void __attribute__((weak)) FLASH_IRQHandler();
+void __attribute__((weak)) RCC_IRQHandler();
+void __attribute__((weak)) EXTI0_IRQHandler();
+void __attribute__((weak)) EXTI1_IRQHandler();
+void __attribute__((weak)) EXTI2_IRQHandler();
+void __attribute__((weak)) EXTI3_IRQHandler();
+void __attribute__((weak)) EXTI4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel1_IRQHandler();
+void __attribute__((weak)) DMA1_Channel2_IRQHandler();
+void __attribute__((weak)) DMA1_Channel3_IRQHandler();
+void __attribute__((weak)) DMA1_Channel4_IRQHandler();
+void __attribute__((weak)) DMA1_Channel5_IRQHandler();
+void __attribute__((weak)) DMA1_Channel6_IRQHandler();
+void __attribute__((weak)) DMA1_Channel7_IRQHandler();
+void __attribute__((weak)) ADC1_IRQHandler();
+void __attribute__((weak)) EXTI9_5_IRQHandler();
+void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler();
+void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler();
+void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler();
+void __attribute__((weak)) TIM1_CC_IRQHandler();
+void __attribute__((weak)) TIM2_IRQHandler();
+void __attribute__((weak)) TIM3_IRQHandler();
+void __attribute__((weak)) TIM4_IRQHandler();
+void __attribute__((weak)) I2C1_EV_IRQHandler();
+void __attribute__((weak)) I2C1_ER_IRQHandler();
+void __attribute__((weak)) I2C2_EV_IRQHandler();
+void __attribute__((weak)) I2C2_ER_IRQHandler();
+void __attribute__((weak)) SPI1_IRQHandler();
+void __attribute__((weak)) SPI2_IRQHandler();
+void __attribute__((weak)) USART1_IRQHandler();
+void __attribute__((weak)) USART2_IRQHandler();
+void __attribute__((weak)) USART3_IRQHandler();
+void __attribute__((weak)) EXTI15_10_IRQHandler();
+void __attribute__((weak)) RTCAlarm_IRQHandler();
+void __attribute__((weak)) CEC_IRQHandler();
+void __attribute__((weak)) TIM6_DAC_IRQHandler();
+void __attribute__((weak)) TIM7_IRQHandler();
+
+//Stack top, defined in the linker script
+extern char _main_stack_top asm("_main_stack_top");
+
+//Interrupt vectors, must be placed @ address 0x00000000
+//The extern declaration is required otherwise g++ optimizes it out
+extern void (* const __Vectors[])();
+void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
+{
+    reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
+    Reset_Handler,              /* Reset Handler */
+    NMI_Handler,                /* NMI Handler */
+    HardFault_Handler,          /* Hard Fault Handler */
+    MemManage_Handler,          /* MPU Fault Handler */
+    BusFault_Handler,           /* Bus Fault Handler */
+    UsageFault_Handler,         /* Usage Fault Handler */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    0,                          /* Reserved */
+    SVC_Handler,                /* SVCall Handler */
+    DebugMon_Handler,           /* Debug Monitor Handler */
+    0,                          /* Reserved */
+    PendSV_Handler,             /* PendSV Handler */
+    SysTick_Handler,            /* SysTick Handler */
+
+    /* External Interrupts */
+	WWDG_IRQHandler,
+	PVD_IRQHandler,
+	TAMPER_IRQHandler,
+	RTC_IRQHandler,
+	FLASH_IRQHandler,
+	RCC_IRQHandler,
+	EXTI0_IRQHandler,
+	EXTI1_IRQHandler,
+	EXTI2_IRQHandler,
+	EXTI3_IRQHandler,
+	EXTI4_IRQHandler,
+	DMA1_Channel1_IRQHandler,
+	DMA1_Channel2_IRQHandler,
+	DMA1_Channel3_IRQHandler,
+	DMA1_Channel4_IRQHandler,
+	DMA1_Channel5_IRQHandler,
+	DMA1_Channel6_IRQHandler,
+	DMA1_Channel7_IRQHandler,
+	ADC1_IRQHandler,
+	0,
+	0,
+	0,
+	0,
+	EXTI9_5_IRQHandler,
+	TIM1_BRK_TIM15_IRQHandler,
+	TIM1_UP_TIM16_IRQHandler,
+	TIM1_TRG_COM_TIM17_IRQHandler,
+	TIM1_CC_IRQHandler,
+	TIM2_IRQHandler,
+	TIM3_IRQHandler,
+	TIM4_IRQHandler,
+	I2C1_EV_IRQHandler,
+	I2C1_ER_IRQHandler,
+	I2C2_EV_IRQHandler,
+	I2C2_ER_IRQHandler,
+	SPI1_IRQHandler,
+	SPI2_IRQHandler,
+	USART1_IRQHandler,
+	USART2_IRQHandler,
+	USART3_IRQHandler,
+	EXTI15_10_IRQHandler,
+	RTCAlarm_IRQHandler,
+	CEC_IRQHandler,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0,
+	0, 
+	0,
+	0,
+	0,
+	TIM6_DAC_IRQHandler,
+	TIM7_IRQHandler,
+	0,0,0,0,0,0,0,0,
+	0,0,0,0,0,0,0,0,
+	0,0,0,0,0,0,0,0,
+	0,0,0,0,0,0,0,0,
+	0,0,0,0,0,0,0,0,
+	0,0,0,
+    reinterpret_cast<void (*)()>(0xF108F85F)
+                                /* @0x1E0. This is for boot in RAM mode for
+                                   STM32F10x Medium Value Line Density devices.*/
+};
+
+#pragma weak WWDG_IRQHandler = Default_Handler
+#pragma weak PVD_IRQHandler = Default_Handler
+#pragma weak TAMPER_IRQHandler = Default_Handler
+#pragma weak RTC_IRQHandler = Default_Handler
+#pragma weak FLASH_IRQHandler = Default_Handler
+#pragma weak RCC_IRQHandler = Default_Handler
+#pragma weak EXTI0_IRQHandler = Default_Handler
+#pragma weak EXTI1_IRQHandler = Default_Handler
+#pragma weak EXTI2_IRQHandler = Default_Handler
+#pragma weak EXTI3_IRQHandler = Default_Handler
+#pragma weak EXTI4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel1_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel2_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel3_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel4_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel5_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel6_IRQHandler = Default_Handler
+#pragma weak DMA1_Channel7_IRQHandler = Default_Handler
+#pragma weak ADC1_IRQHandler = Default_Handler
+#pragma weak EXTI9_5_IRQHandler = Default_Handler
+#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler
+#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler
+#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler
+#pragma weak TIM1_CC_IRQHandler = Default_Handler
+#pragma weak TIM2_IRQHandler = Default_Handler
+#pragma weak TIM3_IRQHandler = Default_Handler
+#pragma weak TIM4_IRQHandler = Default_Handler
+#pragma weak I2C1_EV_IRQHandler = Default_Handler
+#pragma weak I2C1_ER_IRQHandler = Default_Handler
+#pragma weak I2C2_EV_IRQHandler = Default_Handler
+#pragma weak I2C2_ER_IRQHandler = Default_Handler
+#pragma weak SPI1_IRQHandler = Default_Handler
+#pragma weak SPI2_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_IRQHandler = Default_Handler
+#pragma weak EXTI15_10_IRQHandler = Default_Handler
+#pragma weak RTCAlarm_IRQHandler = Default_Handler
+#pragma weak CEC_IRQHandler = Default_Handler
+#pragma weak TIM6_DAC_IRQHandler = Default_Handler
+#pragma weak TIM7_IRQHandler = Default_Handler

miosix/arch/cortexM3_stm32/stm32f100rc_solertegiard/core/stage_1_boot.cpp → miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/core/stage_1_boot.cpp

@@ -288,9 +288,9 @@ void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
 #pragma weak I2C2_ER_IRQHandler = Default_Handler
 #pragma weak SPI1_IRQHandler = Default_Handler
 #pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_IRQHandler = Default_Handler
 #pragma weak EXTI15_10_IRQHandler = Default_Handler
 #pragma weak RTC_Alarm_IRQHandler = Default_Handler
 #pragma weak CEC_IRQHandler = Default_Handler
@@ -299,8 +299,8 @@ void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
 #pragma weak TIM14_IRQHandler = Default_Handler
 #pragma weak TIM5_IRQHandler = Default_Handler
 #pragma weak SPI3_IRQHandler = Default_Handler
-#pragma weak UART4_IRQHandler = Default_Handler
-#pragma weak UART5_IRQHandler = Default_Handler
+// #pragma weak UART4_IRQHandler = Default_Handler
+// #pragma weak UART5_IRQHandler = Default_Handler
 #pragma weak TIM6_DAC_IRQHandler = Default_Handler
 #pragma weak TIM7_IRQHandler = Default_Handler
 #pragma weak DMA2_Channel1_IRQHandler = Default_Handler

miosix/arch/cortexM3_stm32/stm32f103c8_breakout/core/stage_1_boot.cpp → miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/core/stage_1_boot.cpp

@@ -260,9 +260,9 @@ void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
 #pragma weak I2C2_ER_IRQHandler = Default_Handler
 #pragma weak SPI1_IRQHandler = Default_Handler
 #pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_IRQHandler = Default_Handler
 #pragma weak EXTI15_10_IRQHandler = Default_Handler
 #pragma weak RTC_Alarm_IRQHandler = Default_Handler
 #pragma weak USBWakeUp_IRQHandler = Default_Handler