miosix/arch/common/drivers/serial_stm32.h

@@ -34,7 +34,9 @@
 #include "interfaces/gpio.h"
 #include "board_settings.h"
 
-#if defined(_ARCH_CORTEXM3_STM32) && defined(__ENABLE_XRAM)
+#define MAX_SERIAL_PORTS 8
+
+#if defined(_ARCH_CORTEXM3_STM32F1) && defined(__ENABLE_XRAM)
 //Quirk: concurrent access to the FSMC from both core and DMA is broken in
 //the stm32f1, so disable DMA mode if XRAM is enabled.
 #undef SERIAL_1_DMA
@@ -46,7 +48,7 @@
 #define SERIAL_DMA
 #endif
 
-#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32)
+#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32F0)
 #undef SERIAL_1_DMA
 #undef SERIAL_2_DMA
 #undef SERIAL_3_DMA
@@ -198,6 +200,10 @@ public:
      */
     int getId() const { return portId; }
     
+    static STM32Serial *ports[MAX_SERIAL_PORTS];  ///< Pointer to serial port classes to
+                                   ///< let interrupts access the classes
+
+	
     /**
      * Destructor
      */
@@ -248,7 +254,7 @@ private:
     void waitSerialTxFifoEmpty()
     {
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         while((port->SR & USART_SR_TC)==0) ;
         #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -265,14 +271,14 @@ private:
     
     USART_TypeDef *port;              ///< Pointer to USART peripheral
     #ifdef SERIAL_DMA
-    #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     DMA_Channel_TypeDef *dmaTx;       ///< Pointer to DMA TX peripheral
     DMA_Channel_TypeDef *dmaRx;       ///< Pointer to DMA RX peripheral
-    #else //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+    #else //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
     DMA_Stream_TypeDef *dmaTx;        ///< Pointer to DMA TX peripheral
     DMA_Stream_TypeDef *dmaRx;        ///< Pointer to DMA RX peripheral
-    #endif //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+    #endif //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
     Thread *txWaiting;                ///< Thread waiting for tx, or 0
     static const unsigned int txBufferSize=16; ///< Size of tx buffer, for tx speedup
     /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the

miosix/arch/common/drivers/servo_stm32.cpp

@@ -96,7 +96,7 @@ void SynchronizedServo::enable(int channel)
             case 0:
                 TIM4->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
                 TIM4->CCER |= TIM_CCER_CC1E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo1out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo1out::mode(Mode::ALTERNATE);
@@ -104,7 +104,7 @@ void SynchronizedServo::enable(int channel)
             case 1:
                 TIM4->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
                 TIM4->CCER |= TIM_CCER_CC2E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo2out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo2out::mode(Mode::ALTERNATE);
@@ -112,7 +112,7 @@ void SynchronizedServo::enable(int channel)
             case 2:
                 TIM4->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE;
                 TIM4->CCER |= TIM_CCER_CC3E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo3out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo3out::mode(Mode::ALTERNATE);
@@ -120,7 +120,7 @@ void SynchronizedServo::enable(int channel)
             case 3:
                 TIM4->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE;
                 TIM4->CCER |= TIM_CCER_CC4E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo4out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo4out::mode(Mode::ALTERNATE);

miosix/arch/common/drivers/stm32_sgm.cpp → miosix/arch/common/drivers/stm32_backup_domain.cpp

@@ -25,12 +25,25 @@
  *   along with this program; if not, see <http://www.gnu.org/licenses/>   *
  ***************************************************************************/
 
-#include "board_settings.h"
-#include "stm32_sgm.h"
+#include "stm32_backup_domain.h"
+
 #include <string.h>
+
+#include "board_settings.h"
 #include "miosix.h"
 
-namespace miosix {
+#if defined(_ARCH_CORTEXM3_STM32F2) || defined(_ARCH_CORTEXM4_STM32F4)
+#define PWR_CR1 PWR->CR
+#define PWR_CR1_DBP PWR_CR_DBP
+#define PWR_CSR1 PWR->CSR
+#define PWR_CSR1_BRE PWR_CSR_BRE
+#define PWR_CSR1_BRR PWR_CSR_BRR
+#define RCC_CSR_IWDGRSTF RCC_CSR_WDGRSTF
+#define RCC_CSR_PINRSTF RCC_CSR_PADRSTF
+#elif defined(_ARCH_CORTEXM7_STM32F7)
+#define PWR_CSR1 PWR->CSR1
+#define PWR_CR1 PWR->CR1
+#endif
 
 extern unsigned char _preserve_start asm("_preserve_start");
 extern unsigned char _preserve_end asm("_preserve_end");
@@ -38,92 +51,97 @@ extern unsigned char _preserve_end asm("_preserve_end");
 static unsigned char *preserve_start = &_preserve_start;
 static unsigned char *preserve_end   = &_preserve_end;
 
-SGM& SGM::instance()
+namespace miosix
+{
+
+BackupDomain &BackupDomain::instance()
 {
-    static SGM singleton;
+    static BackupDomain singleton;
     return singleton;
 }
 
-SGM::SGM()
+void BackupDomain::enable()
 {
-    /* Enable PWR clock */
+    // Enable PWR clock
     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 
-    /* Enable backup SRAM Clock */
-    RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
-
-    enableWrite();
-
-    /* Enable Backup regulator */
-    PWR->CSR |= PWR_CSR_BRE;  
-
-    /* Enable the Backup SRAM low power Regulator */
-    PWR->CSR |= PWR_CSR_BRE;
+    // Enable access to the backup domain
+    PWR_CR1 |= PWR_CR1_DBP;
+}
 
-    /* Wait for backup regulator */
-    while (!(PWR->CSR & (PWR_CSR_BRR)));
+void BackupDomain::disable()
+{
+    // Disable PWR clock
+    RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;
 
-    /* Retrive last reset reason and clear the pending flag */
-    readResetRegister();
+    // Disable access to the backup domain
+    PWR_CR1 &= ~PWR_CR1_DBP;
+}
 
-    /* 
-     * If the reset wasn't caused by software failure we cannot trust
-     * the content of the backup memory and we need to clear it.
-     */
-    if(lastReset != RST_SW)
+void BackupDomain::enableBackupSRAM()
 {
-        memset(preserve_start, 0, preserve_end-preserve_start);
-    }
+    // Enable backup SRAM Clock
+    RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
+
+    // Enable Backup regulator
+    PWR_CSR1 |= PWR_CSR1_BRE;
 }
 
-void SGM::disableWrite()
+void BackupDomain::disableBackupSRAM()
 {
-    /* Enable Backup Domain write protection */
-    PWR->CR &= ~PWR_CR_DBP;
+    // Disable backup SRAM Clock
+    RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN;
+
+    // Disable Backup regulator
+    PWR_CSR1 &= ~PWR_CSR1_BRE;
 }
 
-void SGM::enableWrite()
+void clearBackupSRAM()
 {
-    /* Disable Backup Domain write protection */
-     PWR->CR |= PWR_CR_DBP; 
+    memset(preserve_start, 0, preserve_end - preserve_start);
 }
 
-void SGM::clearResetFlag()
+BackupDomain::BackupDomain()
 {
-    RCC->CSR |= RCC_CSR_RMVF;
+    // Retrieve last reset reason and clear the pending flag
+    readResetRegister();
 }
 
-void SGM::readResetRegister()
+void BackupDomain::clearResetFlag() { RCC->CSR |= RCC_CSR_RMVF; }
+
+void BackupDomain::readResetRegister()
 {
     uint32_t resetReg = RCC->CSR;
+
     clearResetFlag();
+
     if (resetReg & RCC_CSR_LPWRRSTF)
     {
-        lastReset = RST_LOW_PWR;
+        lastReset = ResetReason::RST_LOW_PWR;
     }
     else if (resetReg & RCC_CSR_WWDGRSTF)
     {
-        lastReset = RST_WINDOW_WDG;
+        lastReset = ResetReason::RST_WINDOW_WDG;
     }
-    else if( resetReg & RCC_CSR_WDGRSTF)
+    else if (resetReg & RCC_CSR_IWDGRSTF)
     {
-        lastReset = RST_INDEPENDENT_WDG;
+        lastReset = ResetReason::RST_INDEPENDENT_WDG;
     }
     else if (resetReg & RCC_CSR_SFTRSTF)
     {
-        lastReset = RST_SW;
+        lastReset = ResetReason::RST_SW;
     }
     else if (resetReg & RCC_CSR_PORRSTF)
     {
-        lastReset = RST_POWER_ON;
+        lastReset = ResetReason::RST_POWER_ON;
     }
-    else if( resetReg & RCC_CSR_PADRSTF)
+    else if (resetReg & RCC_CSR_PINRSTF)
     {
-        lastReset = RST_PIN;
+        lastReset = ResetReason::RST_PIN;
     }
     else
     {
-        lastReset = RST_UNKNOWN;
+        lastReset = ResetReason::RST_UNKNOWN;
     }
 }
 

miosix/arch/common/drivers/stm32_sgm.h → miosix/arch/common/drivers/stm32_backup_domain.h

@@ -29,46 +29,60 @@
 
 #define PRESERVE __attribute__((section(".preserve")))
 
-namespace miosix {
+namespace miosix
+{
 
 /**
  * Possible causes for an STM32 reset
  */
-enum ResetReason
+enum class ResetReason
 {
-    RST_LOW_PWR=0,
-    RST_WINDOW_WDG=1,
-    RST_INDEPENDENT_WDG=2,
-    RST_SW=3,
-    RST_POWER_ON=4,
-    RST_PIN=5,
-    RST_UNKNOWN=6,
+    RST_LOW_PWR         = 0,  // Low power
+    RST_WINDOW_WDG      = 1,  // Reset from the windows watchdog
+    RST_INDEPENDENT_WDG = 2,  // Reset from the independent watchdog
+    RST_SW              = 3,  // Software reset
+    RST_POWER_ON        = 4,  // System power on
+    RST_PIN             = 5,  // Reset pin
+    RST_UNKNOWN         = 6,  // Unknown
 };
 
 /**
- * Driver for the STM32F2 and STM32F4 backup SRAM, here used as
- * SafeGuard Memory, that is, a memory whose value is preseved across resets.
+ * Driver for the backup SRAM.
+ *
+ * @warning Tested only on stm32f2, stm32f4 and stm32f7 microcontrollers.
  */
-class SGM 
+class BackupDomain
 {
 public:
     /**
-     * \return an instance of this class (singleton)
+     * @return An instance of this class (singleton).
+     */
+    static BackupDomain& instance();
+
+    /**
+     * Enables the backup domain clock and write access.
+     */
+    void enable();
+
+    /**
+     * Disable the backup domain clock and write access.
+     */
+    void disable();
+
+    /**
+     * Enable the backup SRAM.
      */
-    static SGM& instance();
+    void enableBackupSRAM();
 
     /**
-     * Temporarily disable writing to the safeguard memory.
-     * By deafult, from reset to when the contrsuctor of this class is called
-     * the safeguard memory is not writable. After the constructor is called,
-     * the safeguard memory is writable.
+     * Disable the backup SRAM.
      */
-    void disableWrite();
+    void disableBackupSRAM();
 
     /**
-     * Make the safeguard memory writable again, after a call to disableWrite()
+     * Clear the backup SRAM.
      */
-    void enableWrite();
+    void clearBackupSRAM();
 
     /**
      * Return the cause of the last reset of the micro controller
@@ -78,14 +92,12 @@ public:
 private:
     ResetReason lastReset;
 
-    SGM(const SGM&)=delete;
-    SGM& operator=(const SGM&)=delete;
+    BackupDomain(const BackupDomain&)            = delete;
+    BackupDomain& operator=(const BackupDomain&) = delete;
 
-    SGM();
+    BackupDomain();
     void readResetRegister();
     void clearResetFlag();
-
 };
 
-
-}
\ No newline at end of file
+}  // namespace miosix
\ No newline at end of file

miosix/arch/cortexM0_stm32/common/interfaces-impl/gpio_impl.h → miosix/arch/cortexM0_stm32f0/common/interfaces-impl/gpio_impl.h

@@ -57,14 +57,22 @@ public:
      */
     enum Mode_
     {
-        INPUT              =  0, ///Floating Input       (MODE=00 TYPE=0 PUP=00)
-        INPUT_PULL_UP      =  1, ///Pullup   Input       (MODE=00 TYPE=0 PUP=01)
-        INPUT_PULL_DOWN    =  2, ///Pulldown Input       (MODE=00 TYPE=0 PUP=10)
-        INPUT_ANALOG       = 24, ///Analog   Input       (MODE=11 TYPE=0 PUP=00)
-        OUTPUT             =  8, ///Push Pull  Output    (MODE=01 TYPE=0 PUP=00)
-        OPEN_DRAIN         = 12, ///Open Drain Output    (MODE=01 TYPE=1 PUP=00)
-        ALTERNATE          = 16, ///Alternate function   (MODE=10 TYPE=0 PUP=00)
-        ALTERNATE_OD       = 20, ///Alternate Open Drain (MODE=10 TYPE=1 PUP=00)
+        INPUT_ANALOG           = 0b11000, ///Input Analog            (MODE=11 TYPE=0 PUP=00)
+        INPUT                  = 0b00000, ///Input Floating          (MODE=00 TYPE=0 PUP=00)
+        INPUT_PULL_UP          = 0b00001, ///Input PullUp            (MODE=00 TYPE=0 PUP=01)
+        INPUT_PULL_DOWN        = 0b00010, ///Input PullDown          (MODE=00 TYPE=0 PUP=10)
+        OUTPUT                 = 0b01000, ///Push Pull  Output       (MODE=01 TYPE=0 PUP=00)
+        OUTPUT_PULL_UP         = 0b01001, ///Push Pull  Output PU    (MODE=01 TYPE=0 PUP=01)
+        OUTPUT_PULL_DOWN       = 0b01010, ///Push Pull  Output PD    (MODE=01 TYPE=0 PUP=10)
+        OPEN_DRAIN             = 0b01100, ///Open Drain Output       (MODE=01 TYPE=1 PUP=00)
+        OPEN_DRAIN_PULL_UP     = 0b01101, ///Open Drain Output PU    (MODE=01 TYPE=1 PUP=01)
+        OPEN_DRAIN_PULL_DOWN   = 0b01110, ///Open Drain Output PD    (MODE=01 TYPE=1 PUP=10)
+        ALTERNATE              = 0b10000, ///Alternate function      (MODE=10 TYPE=0 PUP=00)
+        ALTERNATE_PULL_UP      = 0b10001, ///Alternate function PU   (MODE=10 TYPE=0 PUP=01)
+        ALTERNATE_PULL_DOWN    = 0b10010, ///Alternate function PD   (MODE=10 TYPE=0 PUP=10)
+        ALTERNATE_OD           = 0b10100, ///Alternate Open Drain    (MODE=10 TYPE=1 PUP=00)
+        ALTERNATE_OD_PULL_UP   = 0b10101, ///Alternate Open Drain PU (MODE=10 TYPE=1 PUP=01)
+        ALTERNATE_OD_PULL_DOWN = 0b10110, ///Alternate Open Drain PD (MODE=10 TYPE=1 PUP=10)
     };
 private:
     Mode(); //Just a wrapper class, disallow creating instances

miosix/arch/cortexM0_stm32/stm32f072rb_stm32f0discovery/core/stage_1_boot.cpp → miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/core/stage_1_boot.cpp

@@ -224,8 +224,8 @@ void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
 #pragma weak I2C2_IRQHandler = Default_Handler
 #pragma weak SPI1_IRQHandler = Default_Handler
 #pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_4_IRQHandler = Default_Handler
+// #pragma weak USART1_IRQHandler = Default_Handler
+// #pragma weak USART2_IRQHandler = Default_Handler
+// #pragma weak USART3_4_IRQHandler = Default_Handler
 #pragma weak CEC_CAN_IRQHandler = Default_Handler
 #pragma weak USB_IRQHandler = Default_Handler
\ No newline at end of file

miosix/arch/cortexM0_stm32/stm32f072rb_stm32f0discovery/stm32vldiscovery.cfg → miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32vldiscovery.cfg

@@ -15,4 +15,4 @@
 telnet_port 4444
 gdb_port 3333
 
-source [find arch/cortexM0_stm32/stm32f072rb_stm32f0discovery/stm32f0discovery.cfg]
+source [find arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32f0discovery.cfg]

miosix/arch/cortexM3_stm32/stm32f100rb_stm32vldiscovery/core/stage_1_boot.cpp

-
-#include "interfaces/arch_registers.h"
-#include "core/interrupts.h" //For the unexpected interrupt call
-#include "kernel/stage_2_boot.h"
-#include <string.h>
-
-/*
- * startup.cpp
- * STM32 C++ startup.
- * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices).
- * Supports interrupt handlers in C++ without extern "C"
- * Developed by Terraneo Federico, based on ST startup code.
- * Additionally modified to boot Miosix.
- */
-
-/**
- * Called by Reset_Handler, performs initialization and calls main.
- * Never returns.
- */
-void program_startup() __attribute__((noreturn));
-void program_startup()
-{
-    //Cortex M3 core appears to get out of reset with interrupts already enabled
-    __disable_irq();
-
-	//SystemInit() is called *before* initializing .data and zeroing .bss
-	//Despite all startup files provided by ST do the opposite, there are three
-	//good reasons to do so:
-	//First, the CMSIS specifications say that SystemInit() must not access
-	//global variables, so it is actually possible to call it before
-	//Second, when running Miosix with the xram linker scripts .data and .bss
-	//are placed in the external RAM, so we *must* call SystemInit(), which
-	//enables xram, before touching .data and .bss
-	//Third, this is a performance improvement since the loops that initialize
-	//.data and zeros .bss now run with the CPU at full speed instead of 8MHz
-    SystemInit();
-
-	//These are defined in the linker script
-	extern unsigned char _etext asm("_etext");
-	extern unsigned char _data asm("_data");
-	extern unsigned char _edata asm("_edata");
-	extern unsigned char _bss_start asm("_bss_start");
-	extern unsigned char _bss_end asm("_bss_end");
-
-    //Initialize .data section, clear .bss section
-    unsigned char *etext=&_etext;
-    unsigned char *data=&_data;
-    unsigned char *edata=&_edata;
-    unsigned char *bss_start=&_bss_start;
-    unsigned char *bss_end=&_bss_end;
-    memcpy(data, etext, edata-data);
-    memset(bss_start, 0, bss_end-bss_start);
-
-	//Move on to stage 2
-	_init();
-
-	//If main returns, reboot
-	NVIC_SystemReset();
-    for(;;) ;
-}
-
-/**
- * Reset handler, called by hardware immediately after reset
- */
-void Reset_Handler() __attribute__((__interrupt__, noreturn));
-void Reset_Handler()
-{
-    /*
-     * Initialize process stack and switch to it.
-     * This is required for booting Miosix, a small portion of the top of the
-     * heap area will be used as stack until the first thread starts. After,
-     * this stack will be abandoned and the process stack will point to the
-     * current thread's stack.
-     */
-    asm volatile("ldr r0,  =_heap_end          \n\t"
-                 "msr psp, r0                  \n\t"
-                 "movw r0, #2                  \n\n" //Privileged, process stack
-                 "msr control, r0              \n\t"
-                 "isb                          \n\t":::"r0");
-
-    program_startup();
-}
-
-/**
- * All unused interrupts call this function.
- */
-extern "C" void Default_Handler() 
-{
-    unexpectedInterrupt();
-}
-
-//System handlers
-void /*__attribute__((weak))*/ Reset_Handler();     //These interrupts are not
-void /*__attribute__((weak))*/ NMI_Handler();       //weak because they are
-void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix
-void /*__attribute__((weak))*/ MemManage_Handler();
-void /*__attribute__((weak))*/ BusFault_Handler();
-void /*__attribute__((weak))*/ UsageFault_Handler();
-void /*__attribute__((weak))*/ SVC_Handler();
-void /*__attribute__((weak))*/ DebugMon_Handler();
-void /*__attribute__((weak))*/ PendSV_Handler();
-void /*__attribute__((weak))*/ SysTick_Handler();
-
-//Interrupt handlers
-void __attribute__((weak)) WWDG_IRQHandler();
-void __attribute__((weak)) PVD_IRQHandler();
-void __attribute__((weak)) TAMPER_IRQHandler();
-void __attribute__((weak)) RTC_IRQHandler();
-void __attribute__((weak)) FLASH_IRQHandler();
-void __attribute__((weak)) RCC_IRQHandler();
-void __attribute__((weak)) EXTI0_IRQHandler();
-void __attribute__((weak)) EXTI1_IRQHandler();
-void __attribute__((weak)) EXTI2_IRQHandler();
-void __attribute__((weak)) EXTI3_IRQHandler();
-void __attribute__((weak)) EXTI4_IRQHandler();
-void __attribute__((weak)) DMA1_Channel1_IRQHandler();
-void __attribute__((weak)) DMA1_Channel2_IRQHandler();
-void __attribute__((weak)) DMA1_Channel3_IRQHandler();
-void __attribute__((weak)) DMA1_Channel4_IRQHandler();
-void __attribute__((weak)) DMA1_Channel5_IRQHandler();
-void __attribute__((weak)) DMA1_Channel6_IRQHandler();
-void __attribute__((weak)) DMA1_Channel7_IRQHandler();
-void __attribute__((weak)) ADC1_IRQHandler();
-void __attribute__((weak)) EXTI9_5_IRQHandler();
-void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler();
-void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler();
-void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler();
-void __attribute__((weak)) TIM1_CC_IRQHandler();
-void __attribute__((weak)) TIM2_IRQHandler();
-void __attribute__((weak)) TIM3_IRQHandler();
-void __attribute__((weak)) TIM4_IRQHandler();
-void __attribute__((weak)) I2C1_EV_IRQHandler();
-void __attribute__((weak)) I2C1_ER_IRQHandler();
-void __attribute__((weak)) I2C2_EV_IRQHandler();
-void __attribute__((weak)) I2C2_ER_IRQHandler();
-void __attribute__((weak)) SPI1_IRQHandler();
-void __attribute__((weak)) SPI2_IRQHandler();
-void __attribute__((weak)) USART1_IRQHandler();
-void __attribute__((weak)) USART2_IRQHandler();
-void __attribute__((weak)) USART3_IRQHandler();
-void __attribute__((weak)) EXTI15_10_IRQHandler();
-void __attribute__((weak)) RTCAlarm_IRQHandler();
-void __attribute__((weak)) CEC_IRQHandler();
-void __attribute__((weak)) TIM6_DAC_IRQHandler();
-void __attribute__((weak)) TIM7_IRQHandler();
-
-//Stack top, defined in the linker script
-extern char _main_stack_top asm("_main_stack_top");
-
-//Interrupt vectors, must be placed @ address 0x00000000
-//The extern declaration is required otherwise g++ optimizes it out
-extern void (* const __Vectors[])();
-void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) =
-{
-    reinterpret_cast<void (*)()>(&_main_stack_top),/* Stack pointer*/
-    Reset_Handler,              /* Reset Handler */
-    NMI_Handler,                /* NMI Handler */
-    HardFault_Handler,          /* Hard Fault Handler */
-    MemManage_Handler,          /* MPU Fault Handler */
-    BusFault_Handler,           /* Bus Fault Handler */
-    UsageFault_Handler,         /* Usage Fault Handler */
-    0,                          /* Reserved */
-    0,                          /* Reserved */
-    0,                          /* Reserved */
-    0,                          /* Reserved */
-    SVC_Handler,                /* SVCall Handler */
-    DebugMon_Handler,           /* Debug Monitor Handler */
-    0,                          /* Reserved */
-    PendSV_Handler,             /* PendSV Handler */
-    SysTick_Handler,            /* SysTick Handler */
-
-    /* External Interrupts */
-	WWDG_IRQHandler,
-	PVD_IRQHandler,
-	TAMPER_IRQHandler,
-	RTC_IRQHandler,
-	FLASH_IRQHandler,
-	RCC_IRQHandler,
-	EXTI0_IRQHandler,
-	EXTI1_IRQHandler,
-	EXTI2_IRQHandler,
-	EXTI3_IRQHandler,
-	EXTI4_IRQHandler,
-	DMA1_Channel1_IRQHandler,
-	DMA1_Channel2_IRQHandler,
-	DMA1_Channel3_IRQHandler,
-	DMA1_Channel4_IRQHandler,
-	DMA1_Channel5_IRQHandler,
-	DMA1_Channel6_IRQHandler,
-	DMA1_Channel7_IRQHandler,
-	ADC1_IRQHandler,
-	0,
-	0,
-	0,
-	0,
-	EXTI9_5_IRQHandler,
-	TIM1_BRK_TIM15_IRQHandler,
-	TIM1_UP_TIM16_IRQHandler,
-	TIM1_TRG_COM_TIM17_IRQHandler,
-	TIM1_CC_IRQHandler,
-	TIM2_IRQHandler,
-	TIM3_IRQHandler,
-	TIM4_IRQHandler,
-	I2C1_EV_IRQHandler,
-	I2C1_ER_IRQHandler,
-	I2C2_EV_IRQHandler,
-	I2C2_ER_IRQHandler,
-	SPI1_IRQHandler,
-	SPI2_IRQHandler,
-	USART1_IRQHandler,
-	USART2_IRQHandler,
-	USART3_IRQHandler,
-	EXTI15_10_IRQHandler,
-	RTCAlarm_IRQHandler,
-	CEC_IRQHandler,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0,
-	0, 
-	0,
-	0,
-	0,
-	TIM6_DAC_IRQHandler,
-	TIM7_IRQHandler,
-	0,0,0,0,0,0,0,0,
-	0,0,0,0,0,0,0,0,
-	0,0,0,0,0,0,0,0,
-	0,0,0,0,0,0,0,0,
-	0,0,0,0,0,0,0,0,
-	0,0,0,
-    reinterpret_cast<void (*)()>(0xF108F85F)
-                                /* @0x1E0. This is for boot in RAM mode for
-                                   STM32F10x Medium Value Line Density devices.*/
-};
-
-#pragma weak WWDG_IRQHandler = Default_Handler
-#pragma weak PVD_IRQHandler = Default_Handler
-#pragma weak TAMPER_IRQHandler = Default_Handler
-#pragma weak RTC_IRQHandler = Default_Handler
-#pragma weak FLASH_IRQHandler = Default_Handler
-#pragma weak RCC_IRQHandler = Default_Handler
-#pragma weak EXTI0_IRQHandler = Default_Handler
-#pragma weak EXTI1_IRQHandler = Default_Handler
-#pragma weak EXTI2_IRQHandler = Default_Handler
-#pragma weak EXTI3_IRQHandler = Default_Handler
-#pragma weak EXTI4_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel1_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel2_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel3_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel4_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel5_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel6_IRQHandler = Default_Handler
-#pragma weak DMA1_Channel7_IRQHandler = Default_Handler
-#pragma weak ADC1_IRQHandler = Default_Handler
-#pragma weak EXTI9_5_IRQHandler = Default_Handler
-#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler
-#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler
-#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler
-#pragma weak TIM1_CC_IRQHandler = Default_Handler
-#pragma weak TIM2_IRQHandler = Default_Handler
-#pragma weak TIM3_IRQHandler = Default_Handler
-#pragma weak TIM4_IRQHandler = Default_Handler
-#pragma weak I2C1_EV_IRQHandler = Default_Handler
-#pragma weak I2C1_ER_IRQHandler = Default_Handler
-#pragma weak I2C2_EV_IRQHandler = Default_Handler
-#pragma weak I2C2_ER_IRQHandler = Default_Handler
-#pragma weak SPI1_IRQHandler = Default_Handler
-#pragma weak SPI2_IRQHandler = Default_Handler
-#pragma weak USART1_IRQHandler = Default_Handler
-#pragma weak USART2_IRQHandler = Default_Handler
-#pragma weak USART3_IRQHandler = Default_Handler
-#pragma weak EXTI15_10_IRQHandler = Default_Handler
-#pragma weak RTCAlarm_IRQHandler = Default_Handler
-#pragma weak CEC_IRQHandler = Default_Handler
-#pragma weak TIM6_DAC_IRQHandler = Default_Handler
-#pragma weak TIM7_IRQHandler = Default_Handler