Progress in STM32H5 port

miosix/arch/common/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.c

@@ -109,7 +109,9 @@
   * @{
   */
 
-#include "stm32h5xx.h"
+//By TFT: was #include "stm32h5xx.h", but the specific chip is #defined in
+//arch_registers_impl.h
+#include "interfaces/arch_registers.h"
 
 /**
   * @}

miosix/arch/common/os_timer/stm32_32bit_os_timer.cpp

@@ -41,8 +41,10 @@ public:
     static inline int IRQgetClock()
     {
         unsigned int result=SystemCoreClock;
-        #if _ARCH_CORTEXM0_STM32F0
+        #if defined(_ARCH_CORTEXM0_STM32F0)
         if(RCC->CFGR & RCC_CFGR_PPRE_2) result/=1<<((RCC->CFGR>>8) & 0x3);
+        #elif defined(_ARCH_CORTEXM33_STM32H5)
+        if(RCC->CFGR2 & RCC_CFGR2_PPRE1_2) result/=1<<((RCC->CFGR2>>4) & 0x3);
         #else
         if(RCC->CFGR & RCC_CFGR_PPRE1_2) result/=1<<((RCC->CFGR>>8) & 0x3);
         #endif
@@ -50,9 +52,15 @@ public:
     }
     static inline void IRQenable()
     {
+        #if defined(_ARCH_CORTEXM33_STM32H5)
+        RCC->APB1LENR |= RCC_APB1LENR_TIM2EN;
+        RCC_SYNC();
+        DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP; //Stop while debugging
+        #else
         RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
         RCC_SYNC();
         DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP; //Stop while debugging
+        #endif
     }
 };
 using STM32TimerHW = STM32Timer2HW;

miosix/arch/cortexM33_stm32h5/stm32h503rb_generic/interfaces-impl/bsp.cpp

@@ -57,9 +57,9 @@ namespace miosix {
 void IRQbspInit()
 {
     //Enable all gpios
-    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
-                    RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
-                    RCC_AHB1ENR_GPIOHEN;
+    RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN |
+                    RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN |
+                    RCC_AHB2ENR_GPIOHEN;
     RCC_SYNC();
     GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS
     GPIOB->OSPEEDR=0xaaaaaaaa;