Recalibrate delay loops for stm3220g-eval board when code is in XRAM.

CMSIS update improved FSMC configuration to use lower delays.

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>

miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/delays.cpp

@@ -44,16 +44,16 @@ void delayMs(unsigned int mseconds)
         // This delay has been calibrated to take 1 millisecond
         // It is written in assembler to be independent on compiler optimization
         asm volatile("   mov   r1, #0     \n"
-                     "___loop_m: cmp   r1, %0     \n"
+                     "1: cmp   r1, %0     \n"
                      "   itt   lo         \n"
                      "   addlo r1, r1, #1 \n"
-                     "           blo   ___loop_m  \n"::"r"(count):"r1");
+                     "   blo   1b         \n"::"r"(count):"r1");
     }
 
     #else //__CODE_IN_XRAM
 
     #ifdef SYSCLK_FREQ_120MHz
-    register const unsigned int count=2662;
+    register const unsigned int count=4998;
     #else
     #warning "Delays are uncalibrated for this clock frequency"    
     #endif
@@ -62,11 +62,10 @@ void delayMs(unsigned int mseconds)
     {
         // This delay has been calibrated to take 1 millisecond
         // It is written in assembler to be independent on compiler optimization
-        asm volatile("           mov   r1, #0     \n"
-                     "___loop_m: cmp   r1, %0     \n"
-                     "           itt   lo         \n"
-                     "           addlo r1, r1, #1 \n"
-                     "           blo   ___loop_m  \n"::"r"(count):"r1");
+        asm volatile("   mov   r1, %0     \n"
+                     "   .align 2         \n" // <- important!
+                     "1: subs  r1, r1, #1 \n"
+                     "   bpl   1b         \n"::"r"(count):"r1");
     }
 
     #endif //__CODE_IN_XRAM
@@ -81,23 +80,21 @@ void delayUs(unsigned int useconds)
     asm volatile("   mov   r1, #30    \n"
                  "   mul   r2, %0, r1 \n"
                  "   mov   r1, #0     \n"
-                 "___loop_u: cmp   r1, r2     \n"
+                 "1: cmp   r1, r2     \n"
                  "   itt   lo         \n"
                  "   addlo r1, r1, #1 \n"
-                 "           blo   ___loop_u  \n"::"r"(useconds):"r1","r2");
+                 "   blo   1b         \n"::"r"(useconds):"r1","r2");
 
     #else //__CODE_IN_XRAM
 
     // This delay has been calibrated to take x microseconds
     // It is written in assembler to be independent on compiler optimization
-    asm volatile("           mov   r1, #2     \n"
-                 "           mul   r2, %0, r1 \n"
-                 "           mov   r1, #0     \n"
-                 "___loop_u: cmp   r1, r2     \n"
-                 "           nop              \n"
-                 "           itt   lo         \n"
-                 "           addlo r1, r1, #1 \n"
-                 "           blo   ___loop_u  \n"::"r"(useconds):"r1","r2");
+    asm volatile("   mov   r1, #5     \n"
+                 "   mul   r1, %0, r1 \n"
+                 "   sub   r1, r1, #1 \n"
+                 "   .align 2         \n" // <- important!
+                 "1: subs  r1, r1, #1 \n"
+                 "   bpl   1b      \n"::"r"(useconds):"r1");
     
     #endif //__CODE_IN_XRAM
 }