Alberto Nidasio authored 2 years ago and Federico committed 2 years ago

Renamed macros _ARCH_CORTEXM0_STM32 and _ARCH_CORTEXM3_STM32 to _ARCH_CORTEXM0_STM32F0 and _ARCH_CORTEXM3_STM32F1

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>

Alberto Nidasio authored 2 years ago and Federico committed 2 years ago

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>

Alberto Nidasio authored 2 years ago and Federico committed 2 years ago

Also fixed a missing memory configuration step in stage_1_boot.cpp. The IRQconfigureCache function has to be called with the position of the external memory in order to setup the MPU properly

Signed-off-by: Terraneo Federico <fede.tft@miosix.org>

Sasan Golchin authored 9 years ago and Federico committed 3 years ago

In this subproject, an 64 bit apriodic timer is created based on
TIM2 in which the overflow is managed automatically and the user
is able to set checkpoints (in terms of timer ticks) to fire IRQ.

An expected usecase is the use this driver as the context switch
tool for the kernel.
There might be some errors in which overflows/checkpoints are not
managed correctly that will be OK asap.

Signed-off-by: sasan_golchin <ahmad.golchin@mail.polimi.it>

Signed-off-by: sasan_golchin <ahmad.golchin@mail.polimi.it>
Signed-off-by: Terraneo Federico <fede.tft@miosix.org>

The kernel used to have a null pointer as process,
now it has a ProcessBase instance, and is the only entity that has an
instance of PRocessBase that is not also an instance of Process.

First process running in testing branch. Problem was the new context save code accounting for floating point registers. Still much work to do.