Makefile

@@ -11,14 +11,6 @@ KPATH := miosix
 CONFPATH := $(KPATH)
 include $(CONFPATH)/config/Makefile.inc
 
-ifeq ("$(BUILD_VERBOSE)","1")
-Q := @
-ECHO := @echo
-else
-Q :=
-ECHO := @true
-endif
-
 ##
 ## List here subdirectories which contains makefiles
 ##

miosix/Makefile

@@ -9,14 +9,6 @@ GCCMAJOR := $(shell arm-miosix-eabi-gcc --version | \
 ## KPATH and CONFPATH are forwarded by the parent Makefile
 include $(CONFPATH)/config/Makefile.inc
 
-ifeq ("$(BUILD_VERBOSE)","1")
-Q :=
-ECHO := @true
-else
-Q := @
-ECHO := @echo
-endif
-
 ## List of all Miosix OS source files that have no special requirements
 ## and that must be built for each architecture (both .c and .cpp)
 ## These files will end up in libmiosix.a
@@ -68,7 +60,6 @@ Q := @
 ECHO := @echo
 endif
 
-BINDIR := bin/$(OPT_BOARD)
 ## Replaces both "foo.cpp"-->"foo.o" and "foo.c"-->"foo.o"
 OBJ := $(addsuffix .o, $(basename $(SRC)))
 
@@ -84,17 +75,14 @@ DFLAGS    := -MMD -MP
 ## Build libmiosix.a and stage_1_boot.o (whose path is in BOOT_FILE)
 ## The file stage_1_boot.o is compiled separately because
 ## it must not end up in libmiosix.a
-all: makedir $(OBJ) $(BOOT_FILE)
+all: $(OBJ) $(BOOT_FILE)
 	$(ECHO) "[PERL] Checking global objects"
 	$(Q)perl _tools/kernel_global_objects.pl $(OBJ)
 	$(ECHO) "[AR  ] libmiosix.a"
-	$(Q)$(AR) rcs $(BINDIR)/libmiosix.a $(OBJ)
-
-makedir:
-	$(Q) mkdir -p $(BINDIR)
+	$(Q)$(AR) rcs libmiosix.a $(OBJ)
 
 clean:
-	-rm -f $(OBJ) $(BOOT_FILE) $(BINDIR)/libmiosix.a $(OBJ:.o=.d)
+	-rm -f $(OBJ) $(BOOT_FILE) libmiosix.a $(OBJ:.o=.d)
 	-rm -f $(BOOT_FILE:.o=.d)
 
 %.o: %.s
@@ -111,6 +99,3 @@ clean:
 
 #pull in dependecy info for existing .o files
 -include $(OBJ:.o=.d)
-
-.PHONY: clean makedir
-.NOTPARALLEL: clean makedir

miosix/_doc/textdoc/stm32-bootloader.txt

@@ -76,7 +76,7 @@ interrupts @ 0x6800000, or Miosix will fail at the first interrupt.
 
 Then run openocd in a shell:
 
-sudo openocd -f miosix/arch/cortexM3_stm32/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg
+sudo openocd -f miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg
 
 and in another shell type:
 

miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c

@@ -98,6 +98,22 @@
                                    This value must be a multiple of 0x200. */
 /******************************************************************************/
 
+// By Alberto Nidasio -- begin
+
+// Divide the input clock
+#define PLL_M (HSE_VALUE/1000000)
+
+#ifdef SYSCLK_FREQ_216MHz
+#define PLL_Q      9
+#define PLL_R      7
+#define PLL_N      432
+#define PLL_P      2
+#else
+#error Clock not selected
+#endif
+
+// By Alberto Nidasio -- end
+
 /**
   * @}
   */
@@ -237,7 +253,7 @@ void SystemInit(void)
   */
 void SystemCoreClockUpdate(void)
 {
-  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllSource = 0, pllm = 2;
   
   /* Get SYSCLK source -------------------------------------------------------*/
   tmp = RCC->CFGR & RCC_CFGR_SWS;
@@ -255,10 +271,10 @@ void SystemCoreClockUpdate(void)
       /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
          SYSCLK = PLL_VCO / PLL_P
          */    
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
       
-      if (pllsource != 0)
+      if (pllSource != 0)
       {
         /* HSE used as PLL clock source */
         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
@@ -286,21 +302,12 @@ void SystemCoreClockUpdate(void)
 //By TFT: added PLL initialization that was not present in the CMSIS code
 void SetSysClk(void)
 {
-  register uint32_t tmpreg = 0, timeout = 0xFFFF;
+  register uint32_t tmpReg = 0, timeout = 0xFFFF;
   
 /******************************************************************************/
 /*            PLL (clocked by HSE) used as System clock source                */
 /******************************************************************************/
   
-/************************* PLL Parameters for clock at 216MHz******************/
-  //By TFT: the original settings were for a boar with a 25MHz clock, not 8MHz
-  //They also mention a PLL_R that doesn't exist in the datasheet and maps to
-  //reseved bits. Finally, the PLL input frequency was set to 2MHz to reduce
-  //PLL jitter as suggested by the datasheet.
-  
-  //uint32_t PLL_M = 25,PLL_Q = 9, PLL_R = 7, PLL_N = 432, PLL_P = 2;
-  uint32_t PLL_M = 4,PLL_Q = 9, PLL_R = 7, PLL_N = 216, PLL_P = 2;
-  
   /* Enable Power Control clock */
   RCC->APB1ENR |= RCC_APB1ENR_PWREN;
  
@@ -313,8 +320,8 @@ void SetSysClk(void)
   /* Wait till HSE is ready and if Time out is reached exit */
   do
   {
-    tmpreg = RCC->CR & RCC_CR_HSERDY;
-  } while((tmpreg != RCC_CR_HSERDY) && (timeout-- > 0));
+    tmpReg = RCC->CR & RCC_CR_HSERDY;
+  } while((tmpReg != RCC_CR_HSERDY) && (timeout-- > 0));
   
   if(timeout != 0)
   {  
@@ -330,8 +337,8 @@ void SetSysClk(void)
     /* Wait till ODR is ready and if Time out is reached exit */
     do
     {
-      tmpreg = PWR->CSR1 & PWR_CSR1_ODRDY;
-    } while((tmpreg != PWR_CSR1_ODRDY) && (timeout-- > 0));
+      tmpReg = PWR->CSR1 & PWR_CSR1_ODRDY;
+    } while((tmpReg != PWR_CSR1_ODRDY) && (timeout-- > 0));
     
     /* Enable ODSW */
     PWR->CR1 |= 0x00020000;
@@ -339,8 +346,8 @@ void SetSysClk(void)
     /* Wait till ODR is ready and if Time out is reached exit */
     do
     {
-      tmpreg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
-    } while((tmpreg != PWR_CSR1_ODSWRDY) && (timeout-- > 0)); 
+      tmpReg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
+    } while((tmpReg != PWR_CSR1_ODSWRDY) && (timeout-- > 0)); 
    
     /* HCLK = SYSCLK / 1*/
     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
@@ -362,8 +369,8 @@ void SetSysClk(void)
   timeout = 0xFFFF;
   do
   {
-    tmpreg = (RCC->CR & RCC_CR_PLLRDY); 
-  } while((tmpreg != RCC_CR_PLLRDY) && (timeout-- > 0));
+    tmpReg = (RCC->CR & RCC_CR_PLLRDY); 
+  } while((tmpReg != RCC_CR_PLLRDY) && (timeout-- > 0));
   
   if(timeout != 0)
   {
@@ -377,8 +384,8 @@ void SetSysClk(void)
     timeout = 0xFFFF;
     do
     {
-      tmpreg = (RCC->CFGR & RCC_CFGR_SWS); 
-    } while((tmpreg != RCC_CFGR_SWS) && (timeout-- > 0));
+      tmpReg = (RCC->CFGR & RCC_CFGR_SWS); 
+    } while((tmpReg != RCC_CFGR_SWS) && (timeout-- > 0));
   }   
 }
 

miosix/arch/common/core/interrupts.h

@@ -3,7 +3,7 @@
 
 #ifdef _ARCH_ARM7_LPC2000
 #include "interrupts_arm7.h"
-#elif defined(_ARCH_CORTEXM0_STM32)   || defined(_ARCH_CORTEXM3_STM32)   \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
    || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
    || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
    || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \
@@ -13,11 +13,3 @@
 #else
 #error "Unknown arch"
 #endif
-
-// Cortex M0 and M0+ does not have some SCB registers, in order to avoid
-// compilation issues a flag is defined to disable code that accesses to 
-// registers not present in these families
-
-#if defined(_ARCH_CORTEXM0_STM32)
-#define _ARCH_CORTEXM0
-#endif

miosix/arch/common/core/interrupts_cortexMx.cpp

@@ -99,20 +99,20 @@ void __attribute__((noinline)) HardFault_impl()
     #ifdef WITH_ERRLOG
     IRQerrorLog("\r\n***Unexpected HardFault @ ");
     printUnsignedInt(getProgramCounter());
-    #ifndef _ARCH_CORTEXM0
+    #if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0_STM32L0)
     unsigned int hfsr=SCB->HFSR;
     if(hfsr & 0x40000000) //SCB_HFSR_FORCED
         IRQerrorLog("Fault escalation occurred\r\n");
     if(hfsr & 0x00000002) //SCB_HFSR_VECTTBL
         IRQerrorLog("A BusFault occurred during a vector table read\r\n");
-    #endif //_ARCH_CORTEXM0
+    #endif // !_ARCH_CORTEXM0_STM32F0 && !_ARCH_CORTEXM0_STM32G0 && !_ARCH_CORTEXM0_STM32L0
     #endif //WITH_ERRLOG
     miosix_private::IRQsystemReboot();
 }
 
 // Cortex M0/M0+ architecture does not have the interrupts handled by code
 // below this point
-#ifndef _ARCH_CORTEXM0
+#if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0_STM32L0)
 
 void __attribute__((naked)) MemManage_Handler()
 {
@@ -262,7 +262,7 @@ void DebugMon_Handler()
     miosix_private::IRQsystemReboot();
 }
 
-#endif //_ARCH_CORTEXM0
+#endif // !_ARCH_CORTEXM0_STM32F0 && !_ARCH_CORTEXM0_STM32G0 && !_ARCH_CORTEXM0_STM32L0
 
 void PendSV_Handler()
 {

miosix/arch/common/drivers/sd_stm32f2_f4.cpp → miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp

@@ -25,7 +25,7 @@
  *   along with this program; if not, see <http://www.gnu.org/licenses/>   *
  ***************************************************************************/
 
-#include "sd_stm32f2_f4.h"
+#include "sd_stm32f2_f4_f7.h"
 #include "interfaces/bsp.h"
 #include "interfaces/arch_registers.h"
 #include "core/cache_cortexMx.h"
@@ -52,9 +52,17 @@
  */
 #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if defined(__SDMMC1)
 #define SDIO                 SDMMC1
 #define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC1EN
 #define SDIO_IRQn            SDMMC1_IRQn
+#elif defined(__SDMMC2)
+#define SDIO SDMMC2
+#define RCC_APB2ENR_SDIOEN   RCC_APB2ENR_SDMMC2EN
+#define SDIO_IRQn            SDMMC2_IRQn
+#else
+#warning This error is a reminder that you have not selected between SDMMC1 and SDMMC2 in Makefile.int
+#endif
 
 #define SDIO_STA_STBITERR    0 //This bit has been removed
 #define SDIO_STA_RXOVERR     SDMMC_STA_RXOVERR
@@ -76,6 +84,7 @@
 #define SDIO_CLKCR_CLKEN     SDMMC_CLKCR_CLKEN
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
 #define SDIO_CLKCR_PWRSAV    SDMMC_CLKCR_PWRSAV
+#define SDIO_CLKCR_WIDBUS_0  SDMMC_CLKCR_WIDBUS_0
 
 #define SDIO_MASK_STBITERRIE 0 //This bit has been removed
 #define SDIO_MASK_RXOVERRIE  SDMMC_MASK_RXOVERRIE
@@ -93,14 +102,24 @@
 
 #endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
 
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+#define DMA_Stream           DMA2_Stream0
+#else
+#define DMA_Stream           DMA2_Stream3
+#endif
+
 /**
  * \internal
- * DMA2 Stream3 interrupt handler
+ * DMA2 Stream interrupt handler
  */
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+void __attribute__((naked)) DMA2_Stream0_IRQHandler()
+#else
 void __attribute__((naked)) DMA2_Stream3_IRQHandler()
+#endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix18DMA2stream3irqImplEv");
+    asm volatile("bl _ZN6miosix12SDDMAirqImplEv");
     restoreContext();
 }
 
@@ -108,14 +127,16 @@ void __attribute__((naked)) DMA2_Stream3_IRQHandler()
  * \internal
  * SDIO interrupt handler
  */
-#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC1)
 void __attribute__((naked)) SDMMC1_IRQHandler()
+#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+void __attribute__((naked)) SDMMC2_IRQHandler()
 #else //stm32f2 and stm32f4
 void __attribute__((naked)) SDIO_IRQHandler()
 #endif
 {
     saveContext();
-    asm volatile("bl _ZN6miosix11SDIOirqImplEv");
+    asm volatile("bl _ZN6miosix9SDirqImplEv");
     restoreContext();
 }
 
@@ -130,9 +151,18 @@ static unsigned int sdioFlags;      ///< \internal SDIO status flags
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) DMA2stream3irqImpl()
+void __attribute__((used)) SDDMAirqImpl()
 {
     dmaFlags=DMA2->LISR;
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    if (dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
+        transferError = true;
+
+    DMA2->LIFCR = DMA_LIFCR_CTCIF0 |
+                    DMA_LIFCR_CTEIF0 |
+                    DMA_LIFCR_CDMEIF0 |
+                    DMA_LIFCR_CFEIF0;
+#else
     if (dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
         transferError = true;
 
@@ -140,6 +170,7 @@ void __attribute__((used)) DMA2stream3irqImpl()
                     DMA_LIFCR_CTEIF3 |
                     DMA_LIFCR_CDMEIF3 |
                     DMA_LIFCR_CFEIF3;
+#endif
     
     if(!waiting) return;
     waiting->IRQwakeup();
@@ -152,7 +183,7 @@ void __attribute__((used)) DMA2stream3irqImpl()
  * \internal
  * DMA2 Stream3 interrupt handler actual implementation
  */
-void __attribute__((used)) SDIOirqImpl()
+void __attribute__((used)) SDirqImpl()
 {
     sdioFlags=SDIO->STA;
     if(sdioFlags & (SDIO_STA_STBITERR | SDIO_STA_RXOVERR  |
@@ -193,12 +224,22 @@ enum CardType
 static CardType cardType=Invalid;
 
 //SD card GPIOs
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+typedef Gpio<GPIOG_BASE, 9> sdD0;
+typedef Gpio<GPIOG_BASE, 10> sdD1;
+typedef Gpio<GPIOB_BASE, 3> sdD2;
+typedef Gpio<GPIOB_BASE, 4> sdD3;
+typedef Gpio<GPIOD_BASE, 6> sdCLK;
+typedef Gpio<GPIOD_BASE, 7> sdCMD;
+#else
 typedef Gpio<GPIOC_BASE, 8> sdD0;
 typedef Gpio<GPIOC_BASE, 9> sdD1;
 typedef Gpio<GPIOC_BASE, 10> sdD2;
 typedef Gpio<GPIOC_BASE, 11> sdD3;
 typedef Gpio<GPIOC_BASE, 12> sdCLK;
 typedef Gpio<GPIOD_BASE, 2> sdCMD;
+#endif
+
 
 //
 // Class BufferConverter
@@ -884,14 +925,12 @@ static void displayBlockTransferError()
 static unsigned int dmaTransferCommonSetup(const unsigned char *buffer)
 {
     //Clear both SDIO and DMA interrupt flags
-    SDIO->ICR=0x7ff;
-    DMA2->LIFCR=DMA_LIFCR_CTCIF3  |
-                DMA_LIFCR_CTEIF3  |
-                DMA_LIFCR_CDMEIF3 |
-                DMA_LIFCR_CFEIF3;
+    SDIO->ICR=0x4005ff;
+    DMA2->LIFCR=0xffffffff;
 
     transferError=false;
-    dmaFlags=sdioFlags=0;
+    dmaFlags=0;
+    sdioFlags=0;
     waiting=Thread::getCurrentThread();
     
     //Select DMA transfer size based on buffer alignment. Best performance
@@ -937,13 +976,17 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
-    DMA2_Stream3->FCR=DMA_SxFCR_FEIE    | //Interrupt on fifo error
+	DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+	DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+	//Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
+    DMA_Stream->FCR=DMA_SxFCR_FEIE    | //Interrupt on fifo error
                       DMA_SxFCR_DMDIS   | //Fifo enabled
                       DMA_SxFCR_FTH_0;    //Take action if fifo half full
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
+#else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2 | // Channel 4 (SDIO)
+#endif
                      DMA_SxCR_PBURST_0  | //4-beat bursts read from SDIO
                      DMA_SxCR_PL_0      | //Medium priority DMA stream
                      memoryTransferSize | //RAM data size depends on alignment
@@ -977,8 +1020,8 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1040,16 +1083,20 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
                SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun
                SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail
                SDIO_MASK_DTIMEOUTIE;  //Interrupt on data timeout
-	DMA2_Stream3->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
-	DMA2_Stream3->M0AR=reinterpret_cast<unsigned int>(buffer);
-	//Note: DMA2_Stream3->NDTR is don't care in peripheral flow control mode
+	DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
+	DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
+	//Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
     //Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate
     //a spurious fifo error. The code was tested and the transfer completes
     //successfully even in the presence of this fifo error
-    DMA2_Stream3->FCR=DMA_SxFCR_DMDIS   | //Fifo enabled
+    DMA_Stream->FCR=DMA_SxFCR_DMDIS   | //Fifo enabled
                       DMA_SxFCR_FTH_1   | //Take action if fifo full
                       DMA_SxFCR_FTH_0;
-	DMA2_Stream3->CR=DMA_SxCR_CHSEL_2   | //Channel 4 (SDIO)
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
+#else
+    DMA_Stream->CR = DMA_SxCR_CHSEL_2 |   // Channel 4 (SDIO)
+#endif
                      DMA_SxCR_PBURST_0  | //4-beat bursts write to SDIO
                      DMA_SxCR_PL_0      | //Medium priority DMA stream
                      memoryTransferSize | //RAM data size depends on alignment
@@ -1082,8 +1129,8 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
             }
         }
     } else transferError=true;
-    DMA2_Stream3->CR=0;
-    while(DMA2_Stream3->CR & DMA_SxCR_EN) ; //DMA may take time to stop
+    DMA_Stream->CR=0;
+    while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop
     SDIO->DCTRL=0; //Disable data path state machine
     SDIO->MASK=0;
 
@@ -1161,6 +1208,22 @@ static void initSDIOPeripheral()
         RCC_SYNC();
         RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
         RCC_SYNC();
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+        sdD0::mode(Mode::ALTERNATE);
+        sdD0::alternateFunction(11);
+#ifndef SD_ONE_BIT_DATABUS
+        sdD1::mode(Mode::ALTERNATE);
+        sdD1::alternateFunction(11);
+        sdD2::mode(Mode::ALTERNATE);
+        sdD2::alternateFunction(10);
+        sdD3::mode(Mode::ALTERNATE);
+        sdD3::alternateFunction(10);
+#endif // SD_ONE_BIT_DATABUS
+        sdCLK::mode(Mode::ALTERNATE);
+        sdCLK::alternateFunction(11);
+        sdCMD::mode(Mode::ALTERNATE);
+        sdCMD::alternateFunction(11);
+#else
         sdD0::mode(Mode::ALTERNATE);
         sdD0::alternateFunction(12);
 #ifndef SD_ONE_BIT_DATABUS
@@ -1175,9 +1238,16 @@ static void initSDIOPeripheral()
         sdCLK::alternateFunction(12);
         sdCMD::mode(Mode::ALTERNATE);
         sdCMD::alternateFunction(12);
+#endif
     }
+
+#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
+    NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA
+    NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+#else
     NVIC_SetPriority(DMA2_Stream3_IRQn,15);//Low priority for DMA
     NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+#endif
     NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO
     NVIC_EnableIRQ(SDIO_IRQn);
     

miosix/arch/common/drivers/serial.h

@@ -3,7 +3,7 @@
 
 #ifdef _ARCH_ARM7_LPC2000
 #include "serial_lpc2000.h"
-#elif defined(_ARCH_CORTEXM0_STM32)   || defined(_ARCH_CORTEXM3_STM32)   \
+#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \
    || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \
    || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \
    || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM4_STM32F3) \

miosix/arch/common/drivers/serial_stm32.cpp

@@ -156,7 +156,7 @@ void __attribute__((naked, weak)) UART4_IRQHandler()
  */
 void __attribute__((noinline)) usart1txDmaImpl()
 {
-    #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     DMA1->IFCR=DMA_IFCR_CGIF4;
     DMA1_Channel4->CCR=0; //Disable DMA
@@ -177,8 +177,7 @@ void __attribute__((noinline)) usart1rxDmaImpl()
     if(miosix::STM32Serial::ports[0]) miosix::STM32Serial::ports[0]->IRQhandleDMArx();
 }
 
-
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
  || defined(_ARCH_CORTEXM4_STM32L4)
 /**
  * \internal DMA1 Channel 4 IRQ (configured as USART1 TX)
@@ -231,7 +230,7 @@ void __attribute__((naked)) DMA2_Stream5_IRQHandler()
  */
 void __attribute__((noinline)) usart2txDmaImpl()
 {
-    #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     DMA1->IFCR=DMA_IFCR_CGIF7;
     DMA1_Channel7->CCR=0; //Disable DMA
@@ -252,7 +251,7 @@ void __attribute__((noinline)) usart2rxDmaImpl()
     if(miosix::STM32Serial::ports[1]) miosix::STM32Serial::ports[1]->IRQhandleDMArx();
 }
 
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
  || defined(_ARCH_CORTEXM4_STM32L4)
 /**
  * \internal DMA1 Channel 7 IRQ (configured as USART2 TX)
@@ -304,7 +303,7 @@ void __attribute__((naked)) DMA1_Stream5_IRQHandler()
  */
 void __attribute__((noinline)) usart3txDmaImpl()
 {
-    #if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     DMA1->IFCR=DMA_IFCR_CGIF2;
     DMA1_Channel2->CCR=0; //Disable DMA
@@ -325,7 +324,7 @@ void __attribute__((noinline)) usart3rxDmaImpl()
     if(miosix::STM32Serial::ports[2]) miosix::STM32Serial::ports[2]->IRQhandleDMArx();
 }
 
-#if defined(_ARCH_CORTEXM3_STM32) || defined (_ARCH_CORTEXM4_STM32F3) \
+#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \
  || defined(_ARCH_CORTEXM4_STM32L4)
 /**
  * \internal DMA1 Channel 2 IRQ (configured as USART3 TX)
@@ -404,14 +403,14 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
         : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500),
           flowControl(flowControl==RTSCTS), portId(id)
 {
-    #if !defined(_ARCH_CORTEXM3_STM32)
+    #if !defined(_ARCH_CORTEXM3_STM32F1)
     //stm32f2, f4, l4, l1, f7, h7 require alternate function mapping
     //stm32f0 family has different alternate function mapping
     //with respect to the other families
     switch(id)
     {
         case 1:
-            #if !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM0_STM32F0)
             u1tx::alternateFunction(7);
             u1rx::alternateFunction(7);
             if(flowControl)
@@ -419,7 +418,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u1rts::alternateFunction(7);
                 u1cts::alternateFunction(7);
             }
-            #else  //!defined(_ARCH_CORTEXM0_STM32)
+            #else  //!defined(_ARCH_CORTEXM0_STM32F0)
             u1tx::alternateFunction(1);
             u1rx::alternateFunction(1);
             if(flowControl)
@@ -427,10 +426,10 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u1rts::alternateFunction(1);
                 u1cts::alternateFunction(1);
             }
-            #endif //!defined(_ARCH_CORTEXM0_STM32)
+            #endif //!defined(_ARCH_CORTEXM0_STM32F0)
             break;
         case 2:
-            #if !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM0_STM32F0)
             u2tx::alternateFunction(7);
             u2rx::alternateFunction(7);
             if(flowControl)
@@ -438,7 +437,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u2rts::alternateFunction(7);
                 u2cts::alternateFunction(7);
             }
-            #else  //!defined(_ARCH_CORTEXM0_STM32)
+            #else  //!defined(_ARCH_CORTEXM0_STM32F0)
             u2tx::alternateFunction(1);
             u2rx::alternateFunction(1);
             if(flowControl)
@@ -446,10 +445,10 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u2rts::alternateFunction(1);
                 u2cts::alternateFunction(1);
             }
-            #endif //!defined(_ARCH_CORTEXM0_STM32)            
+            #endif //!defined(_ARCH_CORTEXM0_STM32F0)            
             break;
         case 3:
-            #if !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM0_STM32F0)
             u3tx::alternateFunction(7);
             u3rx::alternateFunction(7);
             if(flowControl)
@@ -457,7 +456,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u3rts::alternateFunction(7);
                 u3cts::alternateFunction(7);
             }
-            #else  //!defined(_ARCH_CORTEXM0_STM32)
+            #else  //!defined(_ARCH_CORTEXM0_STM32F0)
             u3tx::alternateFunction(4);
             u3rx::alternateFunction(4);
             if(flowControl)
@@ -465,7 +464,7 @@ STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl)
                 u3rts::alternateFunction(4);
                 u3cts::alternateFunction(4);
             }
-            #endif //!defined(_ARCH_CORTEXM0_STM32)            
+            #endif //!defined(_ARCH_CORTEXM0_STM32F0)            
             break;
         case 4:
             u4tx::alternateFunction(8);
@@ -526,11 +525,11 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
     //Quirk the position of the PPRE1 and PPRE2 bitfields in RCC->CFGR changes
     //STM32F0 does not have ppre1 and ppre2, in this case the variables are not
     //defined in order to avoid "unused variable" warning
-    #if defined(_ARCH_CORTEXM3_STM32)   || defined(_ARCH_CORTEXM3_STM32L1) \
+    #if defined(_ARCH_CORTEXM3_STM32F1)   || defined(_ARCH_CORTEXM3_STM32L1) \
      || defined(_ARCH_CORTEXM4_STM32F3) || defined(_ARCH_CORTEXM4_STM32L4)
     const unsigned int ppre1=8;
     const unsigned int ppre2=11;
-    #elif !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+    #elif !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
     const unsigned int ppre1=10;
     const unsigned int ppre2=13;
     #endif
@@ -541,7 +540,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
             RCC_SYNC();
             #ifdef SERIAL_1_DMA
-            #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+            #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
              || defined(_ARCH_CORTEXM4_STM32L4)
             #ifdef _ARCH_CORTEXM4_STM32L4
             RCC->AHB1ENR |= RCC_AHBENR_DMA1EN;
@@ -575,9 +574,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             #endif //SERIAL_1_DMA
             NVIC_SetPriority(USART1_IRQn,15);//Lowest priority for serial
             NVIC_EnableIRQ(USART1_IRQn);
-            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
             if(RCC->CFGR & RCC_CFGR_PPRE2_2) freq/=1<<(((RCC->CFGR>>ppre2) & 0x3)+1);
-            #elif defined(_ARCH_CORTEXM0_STM32)
+            #elif defined(_ARCH_CORTEXM0_STM32F0)
             // STM32F0 family has only PPRE2 register
             if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
             #else
@@ -606,7 +605,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             #endif //_ARCH_CORTEXM7_STM32H7
             RCC_SYNC();
             #ifdef SERIAL_2_DMA
-            #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+            #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
              || defined(_ARCH_CORTEXM4_STM32L4)
             #ifdef _ARCH_CORTEXM4_STM32L4
             RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
@@ -640,9 +639,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             #endif //SERIAL_2_DMA
             NVIC_SetPriority(USART2_IRQn,15);//Lowest priority for serial
             NVIC_EnableIRQ(USART2_IRQn);
-            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
             if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>ppre1) & 0x3)+1);
-            #elif defined(_ARCH_CORTEXM0_STM32)
+            #elif defined(_ARCH_CORTEXM0_STM32F0)
             // STM32F0 family has only PPRE2 register
             if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
             #else //_ARCH_CORTEXM7_STM32H7
@@ -670,7 +669,7 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             #endif //_ARCH_CORTEXM7_STM32H7
             RCC_SYNC();
             #ifdef SERIAL_3_DMA
-            #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+            #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
              || defined(_ARCH_CORTEXM4_STM32L4)
             #ifdef _ARCH_CORTEXM4_STM32L4
             RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
@@ -709,9 +708,9 @@ void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx,
             NVIC_SetPriority(USART3_4_IRQn,15);
             NVIC_EnableIRQ(USART3_4_IRQn);
             #endif //STM32F072xB
-            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32)
+            #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0)
             if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>ppre1) & 0x3)+1);
-            #elif defined(_ARCH_CORTEXM0_STM32)
+            #elif defined(_ARCH_CORTEXM0_STM32F0)
             // STM32F0 family has only PPRE2 register
             if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>8) & 0x3)+1);
             #else //_ARCH_CORTEXM7_STM32H7
@@ -867,7 +866,7 @@ ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where)
     for(size_t i=0;i<size;i++)
     {
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         while((port->SR & USART_SR_TXE)==0) ;
         port->DR=*buf++;
@@ -888,7 +887,7 @@ void STM32Serial::IRQwrite(const char *str)
     #ifdef SERIAL_DMA
     if(dmaTx)
     {
-        #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+        #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
          || defined(_ARCH_CORTEXM4_STM32L4)
         //If no DMA transfer is in progress bit EN is zero. Otherwise wait until
         //DMA xfer ends, by waiting for the TC (or TE) interrupt flag
@@ -912,7 +911,7 @@ void STM32Serial::IRQwrite(const char *str)
     while(*str)
     {
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         while((port->SR & USART_SR_TXE)==0) ;
         port->DR=*str++;
@@ -954,7 +953,7 @@ int STM32Serial::ioctl(int cmd, void* arg)
 void STM32Serial::IRQhandleInterrupt()
 {
     #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-     && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+     && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
      && !defined(_ARCH_CORTEXM4_STM32L4)
     unsigned int status=port->SR;
     #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -972,7 +971,7 @@ void STM32Serial::IRQhandleInterrupt()
     {
         //Always read data, since this clears interrupt flags
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         c=port->DR;
         #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -986,7 +985,7 @@ void STM32Serial::IRQhandleInterrupt()
     if(status & USART_SR_IDLE)
     {
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         c=port->DR; //clears interrupt flags
         #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -1047,7 +1046,7 @@ STM32Serial::~STM32Serial()
             case 1:
                 #ifdef SERIAL_1_DMA
                 IRQdmaReadStop();
-                #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+                #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
                  || defined(_ARCH_CORTEXM4_STM32L4)
                 NVIC_DisableIRQ(DMA1_Channel4_IRQn);
                 NVIC_ClearPendingIRQ(DMA1_Channel4_IRQn);
@@ -1069,7 +1068,7 @@ STM32Serial::~STM32Serial()
             case 2:
                 #ifdef SERIAL_2_DMA
                 IRQdmaReadStop();
-                #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+                #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
                  || defined(_ARCH_CORTEXM4_STM32L4)
                 NVIC_DisableIRQ(DMA1_Channel7_IRQn);
                 NVIC_ClearPendingIRQ(DMA1_Channel7_IRQn);
@@ -1098,7 +1097,7 @@ STM32Serial::~STM32Serial()
             case 3:
                 #ifdef SERIAL_3_DMA
                 IRQdmaReadStop();
-                #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+                #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
                  || defined(_ARCH_CORTEXM4_STM32L4)
                 NVIC_DisableIRQ(DMA1_Channel2_IRQn);
                 NVIC_ClearPendingIRQ(DMA1_Channel2_IRQn);
@@ -1180,7 +1179,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
     //instruction, it reads SR. When we start the DMA, the DMA controller
     //writes to DR and completes the TC clear sequence.
     #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-     && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+     && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
      && !defined(_ARCH_CORTEXM4_STM32L4)
     while((port->SR & USART_SR_TXE)==0) ;
     #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -1188,7 +1187,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
     #endif //_ARCH_CORTEXM7_STM32F7/H7
     
     dmaTxInProgress=true;
-    #if defined(_ARCH_CORTEXM3_STM32)
+    #if defined(_ARCH_CORTEXM3_STM32F1)
     dmaTx->CPAR=reinterpret_cast<unsigned int>(&port->DR);
     dmaTx->CMAR=reinterpret_cast<unsigned int>(buffer);
     dmaTx->CNDTR=size;
@@ -1209,7 +1208,7 @@ void STM32Serial::writeDma(const char *buffer, size_t size)
              | DMA_CCR_EN;   //Start DMA
     #else  //_ARCH_CORTEXM4_STM32F3
     #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-     && !defined(_ARCH_CORTEXM0_STM32)
+     && !defined(_ARCH_CORTEXM0_STM32F0)
     dmaTx->PAR=reinterpret_cast<unsigned int>(&port->DR);
     #else //_ARCH_CORTEXM7_STM32F7/H7
     dmaTx->PAR=reinterpret_cast<unsigned int>(&port->TDR);
@@ -1243,7 +1242,7 @@ void STM32Serial::IRQreadDma()
 
 void STM32Serial::IRQdmaReadStart()
 {
-    #if defined(_ARCH_CORTEXM3_STM32)
+    #if defined(_ARCH_CORTEXM3_STM32F1)
     dmaRx->CPAR=reinterpret_cast<unsigned int>(&port->DR);
     dmaRx->CMAR=reinterpret_cast<unsigned int>(rxBuffer);
     dmaRx->CNDTR=rxQueueMin;
@@ -1264,7 +1263,7 @@ void STM32Serial::IRQdmaReadStart()
              | DMA_CCR_EN;   //Start DMA
     #else //_ARCH_CORTEXM4_STM32F3
     #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-     && !defined(_ARCH_CORTEXM0_STM32)
+     && !defined(_ARCH_CORTEXM0_STM32F0)
     dmaRx->PAR=reinterpret_cast<unsigned int>(&port->DR);
     #else //_ARCH_CORTEXM7_STM32F7/H7
     dmaRx->PAR=reinterpret_cast<unsigned int>(&port->RDR);
@@ -1284,7 +1283,7 @@ void STM32Serial::IRQdmaReadStart()
 
 int STM32Serial::IRQdmaReadStop()
 {
-    #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     dmaRx->CCR=0;
     static const unsigned int irqMask[]=

miosix/arch/common/drivers/serial_stm32.h

@@ -36,7 +36,7 @@
 
 #define MAX_SERIAL_PORTS 8
 
-#if defined(_ARCH_CORTEXM3_STM32) && defined(__ENABLE_XRAM)
+#if defined(_ARCH_CORTEXM3_STM32F1) && defined(__ENABLE_XRAM)
 //Quirk: concurrent access to the FSMC from both core and DMA is broken in
 //the stm32f1, so disable DMA mode if XRAM is enabled.
 #undef SERIAL_1_DMA
@@ -48,7 +48,7 @@
 #define SERIAL_DMA
 #endif
 
-#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32)
+#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32F0)
 #undef SERIAL_1_DMA
 #undef SERIAL_2_DMA
 #undef SERIAL_3_DMA
@@ -254,7 +254,7 @@ private:
     void waitSerialTxFifoEmpty()
     {
         #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \
-         && !defined(_ARCH_CORTEXM0_STM32)   && !defined(_ARCH_CORTEXM4_STM32F3) \
+         && !defined(_ARCH_CORTEXM0_STM32F0)   && !defined(_ARCH_CORTEXM4_STM32F3) \
          && !defined(_ARCH_CORTEXM4_STM32L4)
         while((port->SR & USART_SR_TC)==0) ;
         #else //_ARCH_CORTEXM7_STM32F7/H7
@@ -271,14 +271,14 @@ private:
     
     USART_TypeDef *port;              ///< Pointer to USART peripheral
     #ifdef SERIAL_DMA
-    #if defined(_ARCH_CORTEXM3_STM32) || defined(_ARCH_CORTEXM4_STM32F3) \
+    #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \
      || defined(_ARCH_CORTEXM4_STM32L4)
     DMA_Channel_TypeDef *dmaTx;       ///< Pointer to DMA TX peripheral
     DMA_Channel_TypeDef *dmaRx;       ///< Pointer to DMA RX peripheral
-    #else //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+    #else //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
     DMA_Stream_TypeDef *dmaTx;        ///< Pointer to DMA TX peripheral
     DMA_Stream_TypeDef *dmaRx;        ///< Pointer to DMA RX peripheral
-    #endif //_ARCH_CORTEXM3_STM32 and _ARCH_CORTEXM4_STM32F3
+    #endif //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3
     Thread *txWaiting;                ///< Thread waiting for tx, or 0
     static const unsigned int txBufferSize=16; ///< Size of tx buffer, for tx speedup
     /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the

miosix/arch/common/drivers/servo_stm32.cpp

@@ -96,7 +96,7 @@ void SynchronizedServo::enable(int channel)
             case 0:
                 TIM4->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE;
                 TIM4->CCER |= TIM_CCER_CC1E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo1out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo1out::mode(Mode::ALTERNATE);
@@ -104,7 +104,7 @@ void SynchronizedServo::enable(int channel)
             case 1:
                 TIM4->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE;
                 TIM4->CCER |= TIM_CCER_CC2E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo2out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo2out::mode(Mode::ALTERNATE);
@@ -112,7 +112,7 @@ void SynchronizedServo::enable(int channel)
             case 2:
                 TIM4->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE;
                 TIM4->CCER |= TIM_CCER_CC3E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo3out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo3out::mode(Mode::ALTERNATE);
@@ -120,7 +120,7 @@ void SynchronizedServo::enable(int channel)
             case 3:
                 TIM4->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE;
                 TIM4->CCER |= TIM_CCER_CC4E;
-                #ifndef _ARCH_CORTEXM3_STM32 //Only stm32f2 and stm32f4 have it
+                #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it
                 servo4out::alternateFunction(2);
                 #endif //_ARCH_CORTEXM3_STM32
                 servo4out::mode(Mode::ALTERNATE);