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  • avn/swd/miosix-kernel
  • emilio.corigliano/miosix-kernel
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with 1708 additions and 370 deletions
miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c
View file @ ca9c636f
......@@ -98,21 +98,35 @@
This value must be a multiple of 0x200. */
/******************************************************************************/
// By Alberto Nidasio -- begin
// By Alberto Nidasio and TFT -- begin
#if (HSE_VALUE % 2000000) == 0
// Divide the input clock
#define PLL_M (HSE_VALUE/1000000)
//PLL input frequency set to 2MHz to reduce jitter as suggested by the datasheet.
const unsigned int PLL_M=HSE_VALUE/2000000;
#ifdef SYSCLK_FREQ_216MHz
const unsigned int PLL_Q=9;
const unsigned int PLL_R=7;
const unsigned int PLL_N=216;
const unsigned int PLL_P=2;
#else
#error Clock not selected
#endif
#else // HSE_VALUE not divisible by 2MHz
//PLL Input frequency set to 1MHz
const unsigned int PLL_M=HSE_VALUE/1000000;
#ifdef SYSCLK_FREQ_216MHz
#define PLL_Q 9
#define PLL_R 7
#define PLL_N 432
#define PLL_P 2
const unsigned int PLL_Q=9;
const unsigned int PLL_R=7;
const unsigned int PLL_N=432;
const unsigned int PLL_P=2;
#else
#error Clock not selected
#endif
// By Alberto Nidasio -- end
#endif // HSE_VALUE divisibility check
// By Alberto Nidasio and TFT -- end
/**
* @}
......@@ -253,7 +267,7 @@ void SystemInit(void)
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllSource = 0, pllm = 2;
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
......@@ -271,10 +285,10 @@ void SystemCoreClockUpdate(void)
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllSource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllSource != 0)
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
......@@ -302,7 +316,7 @@ void SystemCoreClockUpdate(void)
//By TFT: added PLL initialization that was not present in the CMSIS code
void SetSysClk(void)
{
register uint32_t tmpReg = 0, timeout = 0xFFFF;
register uint32_t tmpreg = 0, timeout = 0xFFFF;
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
......@@ -320,8 +334,8 @@ void SetSysClk(void)
/* Wait till HSE is ready and if Time out is reached exit */
do
{
tmpReg = RCC->CR & RCC_CR_HSERDY;
} while((tmpReg != RCC_CR_HSERDY) && (timeout-- > 0));
tmpreg = RCC->CR & RCC_CR_HSERDY;
} while((tmpreg != RCC_CR_HSERDY) && (timeout-- > 0));
if(timeout != 0)
{
......@@ -337,8 +351,8 @@ void SetSysClk(void)
/* Wait till ODR is ready and if Time out is reached exit */
do
{
tmpReg = PWR->CSR1 & PWR_CSR1_ODRDY;
} while((tmpReg != PWR_CSR1_ODRDY) && (timeout-- > 0));
tmpreg = PWR->CSR1 & PWR_CSR1_ODRDY;
} while((tmpreg != PWR_CSR1_ODRDY) && (timeout-- > 0));
/* Enable ODSW */
PWR->CR1 |= 0x00020000;
......@@ -346,8 +360,8 @@ void SetSysClk(void)
/* Wait till ODR is ready and if Time out is reached exit */
do
{
tmpReg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
} while((tmpReg != PWR_CSR1_ODSWRDY) && (timeout-- > 0));
tmpreg = PWR->CSR1 & PWR_CSR1_ODSWRDY;
} while((tmpreg != PWR_CSR1_ODSWRDY) && (timeout-- > 0));
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
......@@ -369,8 +383,8 @@ void SetSysClk(void)
timeout = 0xFFFF;
do
{
tmpReg = (RCC->CR & RCC_CR_PLLRDY);
} while((tmpReg != RCC_CR_PLLRDY) && (timeout-- > 0));
tmpreg = (RCC->CR & RCC_CR_PLLRDY);
} while((tmpreg != RCC_CR_PLLRDY) && (timeout-- > 0));
if(timeout != 0)
{
......@@ -384,8 +398,8 @@ void SetSysClk(void)
timeout = 0xFFFF;
do
{
tmpReg = (RCC->CFGR & RCC_CFGR_SWS);
} while((tmpReg != RCC_CFGR_SWS) && (timeout-- > 0));
tmpreg = (RCC->CFGR & RCC_CFGR_SWS);
} while((tmpreg != RCC_CFGR_SWS) && (timeout-- > 0));
}
}
......
miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp
View file @ ca9c636f
......@@ -52,16 +52,16 @@
*/
#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
#if defined(__SDMMC1)
#if SD_SDMMC==1
#define SDIO SDMMC1
#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC1EN
#define SDIO_IRQn SDMMC1_IRQn
#elif defined(__SDMMC2)
#elif SD_SDMMC==2
#define SDIO SDMMC2
#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC2EN
#define SDIO_IRQn SDMMC2_IRQn
#else
#warning This error is a reminder that you have not selected between SDMMC1 and SDMMC2 in Makefile.int
#error SD_SDMMC undefined or not in range
#endif
#define SDIO_STA_STBITERR 0 //This bit has been removed
......@@ -100,9 +100,15 @@
#define SDIO_POWER_PWRCTRL_1 SDMMC_POWER_PWRCTRL_1
#define SDIO_POWER_PWRCTRL_0 SDMMC_POWER_PWRCTRL_0
constexpr int ICR_FLAGS_CLR=0x4005ff;
#else //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
constexpr int ICR_FLAGS_CLR=0xc007ff;
#endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
#define DMA_Stream DMA2_Stream0
#else
#define DMA_Stream DMA2_Stream3
......@@ -112,7 +118,7 @@
* \internal
* DMA2 Stream interrupt handler
*/
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
void __attribute__((naked)) DMA2_Stream0_IRQHandler()
#else
void __attribute__((naked)) DMA2_Stream3_IRQHandler()
......@@ -127,9 +133,9 @@ void __attribute__((naked)) DMA2_Stream3_IRQHandler()
* \internal
* SDIO interrupt handler
*/
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC1)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==1
void __attribute__((naked)) SDMMC1_IRQHandler()
#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
void __attribute__((naked)) SDMMC2_IRQHandler()
#else //stm32f2 and stm32f4
void __attribute__((naked)) SDIO_IRQHandler()
......@@ -154,22 +160,22 @@ static unsigned int sdioFlags; ///< \internal SDIO status flags
void __attribute__((used)) SDDMAirqImpl()
{
dmaFlags=DMA2->LISR;
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0))
transferError=true;
DMA2->LIFCR = DMA_LIFCR_CTCIF0 |
DMA_LIFCR_CTEIF0 |
DMA_LIFCR_CDMEIF0 |
DMA_LIFCR_CFEIF0;
DMA2->LIFCR = DMA_LIFCR_CTCIF0
| DMA_LIFCR_CTEIF0
| DMA_LIFCR_CDMEIF0
| DMA_LIFCR_CFEIF0;
#else
if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3))
transferError=true;
DMA2->LIFCR = DMA_LIFCR_CTCIF3 |
DMA_LIFCR_CTEIF3 |
DMA_LIFCR_CDMEIF3 |
DMA_LIFCR_CFEIF3;
DMA2->LIFCR = DMA_LIFCR_CTCIF3
| DMA_LIFCR_CTEIF3
| DMA_LIFCR_CDMEIF3
| DMA_LIFCR_CFEIF3;
#endif
if(!waiting) return;
......@@ -190,7 +196,7 @@ void __attribute__((used)) SDirqImpl()
SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL))
transferError=true;
SDIO->ICR=0x7ff;//Clear flags
SDIO->ICR=ICR_FLAGS_CLR; //Clear flags
if(!waiting) return;
waiting->IRQwakeup();
......@@ -224,7 +230,7 @@ enum CardType
static CardType cardType=Invalid;
//SD card GPIOs
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
typedef Gpio<GPIOG_BASE,9> sdD0;
typedef Gpio<GPIOG_BASE,10> sdD1;
typedef Gpio<GPIOB_BASE,3> sdD2;
......@@ -672,12 +678,12 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
{
if(SDIO->STA & SDIO_STA_CMDSENT)
{
SDIO->ICR=0x7ff;//Clear flags
SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
return CmdResult(cc,CmdResult::Ok);
}
delayUs(1);
}
SDIO->ICR=0x7ff;//Clear flags
SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
return CmdResult(cc,CmdResult::Timeout);
}
......@@ -687,7 +693,7 @@ CmdResult Command::send(CommandType cmd, unsigned int arg)
unsigned int status=SDIO->STA;
if(status & SDIO_STA_CMDREND)
{
SDIO->ICR=0x7ff;//Clear flags
SDIO->ICR=ICR_FLAGS_CLR;//Clear flags
if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok);
else return CmdResult(cc,CmdResult::RespNotMatch);
}
......@@ -925,12 +931,21 @@ static void displayBlockTransferError()
static unsigned int dmaTransferCommonSetup(const unsigned char *buffer)
{
//Clear both SDIO and DMA interrupt flags
SDIO->ICR=0x4005ff;
DMA2->LIFCR=0xffffffff;
SDIO->ICR=ICR_FLAGS_CLR;
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
DMA2->LIFCR = DMA_LIFCR_CTCIF0
| DMA_LIFCR_CTEIF0
| DMA_LIFCR_CDMEIF0
| DMA_LIFCR_CFEIF0;
#else
DMA2->LIFCR = DMA_LIFCR_CTCIF3
| DMA_LIFCR_CTEIF3
| DMA_LIFCR_CDMEIF3
| DMA_LIFCR_CFEIF3;
#endif
transferError=false;
dmaFlags=0;
sdioFlags=0;
dmaFlags=sdioFlags=0;
waiting=Thread::getCurrentThread();
//Select DMA transfer size based on buffer alignment. Best performance
......@@ -979,25 +994,25 @@ static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk,
DMA_Stream->PAR=reinterpret_cast<unsigned int>(&SDIO->FIFO);
DMA_Stream->M0AR=reinterpret_cast<unsigned int>(buffer);
//Note: DMA_Stream->NDTR is don't care in peripheral flow control mode
DMA_Stream->FCR=DMA_SxFCR_FEIE | //Interrupt on fifo error
DMA_SxFCR_DMDIS | //Fifo enabled
DMA_SxFCR_FTH_0; //Take action if fifo half full
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
DMA_Stream->FCR = DMA_SxFCR_FEIE //Interrupt on fifo error
| DMA_SxFCR_DMDIS //Fifo enabled
| DMA_SxFCR_FTH_0; //Take action if fifo half full
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO)
#else
DMA_Stream->CR = DMA_SxCR_CHSEL_2 | // Channel 4 (SDIO)
DMA_Stream->CR = DMA_SxCR_CHSEL_2 //Channel 4 (SDIO)
#endif
DMA_SxCR_PBURST_0 | //4-beat bursts read from SDIO
DMA_SxCR_PL_0 | //Medium priority DMA stream
memoryTransferSize | //RAM data size depends on alignment
DMA_SxCR_PSIZE_1 | //Read 32bit at a time from SDIO
DMA_SxCR_MINC | //Increment RAM pointer
0 | //Peripheral to memory direction
DMA_SxCR_PFCTRL | //Peripheral is flow controller
DMA_SxCR_TCIE | //Interrupt on transfer complete
DMA_SxCR_TEIE | //Interrupt on transfer error
DMA_SxCR_DMEIE | //Interrupt on direct mode error
DMA_SxCR_EN; //Start the DMA
| DMA_SxCR_PBURST_0 //4-beat bursts read from SDIO
| DMA_SxCR_PL_0 //Medium priority DMA stream
| memoryTransferSize //RAM data size depends on alignment
| DMA_SxCR_PSIZE_1 //Read 32bit at a time from SDIO
| DMA_SxCR_MINC //Increment RAM pointer
| 0 //Peripheral to memory direction
| DMA_SxCR_PFCTRL //Peripheral is flow controller
| DMA_SxCR_TCIE //Interrupt on transfer complete
| DMA_SxCR_TEIE //Interrupt on transfer error
| DMA_SxCR_DMEIE //Interrupt on direct mode error
| DMA_SxCR_EN; //Start the DMA
SDIO->DLEN=nblk*512;
if(waiting==0)
......@@ -1089,24 +1104,24 @@ static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk,
//Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate
//a spurious fifo error. The code was tested and the transfer completes
//successfully even in the presence of this fifo error
DMA_Stream->FCR=DMA_SxFCR_DMDIS | //Fifo enabled
DMA_SxFCR_FTH_1 | //Take action if fifo full
DMA_SxFCR_FTH_0;
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) | // Channel 4 (SDIO)
DMA_Stream->FCR = DMA_SxFCR_DMDIS //Fifo enabled
| DMA_SxFCR_FTH_1 //Take action if fifo full
| DMA_SxFCR_FTH_0;
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO)
#else
DMA_Stream->CR = DMA_SxCR_CHSEL_2 | // Channel 4 (SDIO)
DMA_Stream->CR = DMA_SxCR_CHSEL_2 // Channel 4 (SDIO)
#endif
DMA_SxCR_PBURST_0 | //4-beat bursts write to SDIO
DMA_SxCR_PL_0 | //Medium priority DMA stream
memoryTransferSize | //RAM data size depends on alignment
DMA_SxCR_PSIZE_1 | //Write 32bit at a time to SDIO
DMA_SxCR_MINC | //Increment RAM pointer
DMA_SxCR_DIR_0 | //Memory to peripheral direction
DMA_SxCR_PFCTRL | //Peripheral is flow controller
DMA_SxCR_TEIE | //Interrupt on transfer error
DMA_SxCR_DMEIE | //Interrupt on direct mode error
DMA_SxCR_EN; //Start the DMA
| DMA_SxCR_PBURST_0 //4-beat bursts write to SDIO
| DMA_SxCR_PL_0 //Medium priority DMA stream
| memoryTransferSize //RAM data size depends on alignment
| DMA_SxCR_PSIZE_1 //Write 32bit at a time to SDIO
| DMA_SxCR_MINC //Increment RAM pointer
| DMA_SxCR_DIR_0 //Memory to peripheral direction
| DMA_SxCR_PFCTRL //Peripheral is flow controller
| DMA_SxCR_TEIE //Interrupt on transfer error
| DMA_SxCR_DMEIE //Interrupt on direct mode error
| DMA_SxCR_EN; //Start the DMA
SDIO->DLEN=nblk*512;
if(waiting==0)
......@@ -1208,7 +1223,7 @@ static void initSDIOPeripheral()
RCC_SYNC();
RCC->APB2ENR |= RCC_APB2ENR_SDIOEN;
RCC_SYNC();
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
sdD0::mode(Mode::ALTERNATE);
sdD0::alternateFunction(11);
#ifndef SD_ONE_BIT_DATABUS
......@@ -1241,7 +1256,7 @@ static void initSDIOPeripheral()
#endif
}
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && defined(__SDMMC2)
#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2
NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA
NVIC_EnableIRQ(DMA2_Stream0_IRQn);
#else
......@@ -1256,7 +1271,7 @@ static void initSDIOPeripheral()
SDIO->CLKCR=0;
SDIO->CMD=0;
SDIO->DCTRL=0;
SDIO->ICR=0xc007ff;
SDIO->ICR=ICR_FLAGS_CLR;
SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state
//This delay is particularly important: when setting the POWER register a
//glitch on the CMD pin happens. This glitch has a fast fall time and a slow
......
miosix/arch/common/drivers/stm32_sgm.cpp → miosix/arch/common/drivers/stm32_backup_domain.cpp
View file @ ca9c636f
......@@ -25,12 +25,25 @@
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
#include "board_settings.h"
#include "stm32_sgm.h"
#include "stm32_backup_domain.h"
#include <string.h>
#include "board_settings.h"
#include "miosix.h"
namespace miosix {
#if defined(_ARCH_CORTEXM3_STM32F2) || defined(_ARCH_CORTEXM4_STM32F4)
#define PWR_CR1 PWR->CR
#define PWR_CR1_DBP PWR_CR_DBP
#define PWR_CSR1 PWR->CSR
#define PWR_CSR1_BRE PWR_CSR_BRE
#define PWR_CSR1_BRR PWR_CSR_BRR
#define RCC_CSR_IWDGRSTF RCC_CSR_WDGRSTF
#define RCC_CSR_PINRSTF RCC_CSR_PADRSTF
#elif defined(_ARCH_CORTEXM7_STM32F7)
#define PWR_CSR1 PWR->CSR1
#define PWR_CR1 PWR->CR1
#endif
extern unsigned char _preserve_start asm("_preserve_start");
extern unsigned char _preserve_end asm("_preserve_end");
......@@ -38,92 +51,97 @@ extern unsigned char _preserve_end asm("_preserve_end");
static unsigned char *preserve_start = &_preserve_start;
static unsigned char *preserve_end = &_preserve_end;
SGM& SGM::instance()
namespace miosix
{
BackupDomain &BackupDomain::instance()
{
static SGM singleton;
static BackupDomain singleton;
return singleton;
}
SGM::SGM()
void BackupDomain::enable()
{
/* Enable PWR clock */
// Enable PWR clock
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
/* Enable backup SRAM Clock */
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
enableWrite();
/* Enable Backup regulator */
PWR->CSR |= PWR_CSR_BRE;
/* Enable the Backup SRAM low power Regulator */
PWR->CSR |= PWR_CSR_BRE;
// Enable access to the backup domain
PWR_CR1 |= PWR_CR1_DBP;
}
/* Wait for backup regulator */
while (!(PWR->CSR & (PWR_CSR_BRR)));
void BackupDomain::disable()
{
// Disable PWR clock
RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;
/* Retrive last reset reason and clear the pending flag */
readResetRegister();
// Disable access to the backup domain
PWR_CR1 &= ~PWR_CR1_DBP;
}
/*
* If the reset wasn't caused by software failure we cannot trust
* the content of the backup memory and we need to clear it.
*/
if(lastReset != RST_SW)
void BackupDomain::enableBackupSRAM()
{
memset(preserve_start, 0, preserve_end-preserve_start);
}
// Enable backup SRAM Clock
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
// Enable Backup regulator
PWR_CSR1 |= PWR_CSR1_BRE;
}
void SGM::disableWrite()
void BackupDomain::disableBackupSRAM()
{
/* Enable Backup Domain write protection */
PWR->CR &= ~PWR_CR_DBP;
// Disable backup SRAM Clock
RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN;
// Disable Backup regulator
PWR_CSR1 &= ~PWR_CSR1_BRE;
}
void SGM::enableWrite()
void clearBackupSRAM()
{
/* Disable Backup Domain write protection */
PWR->CR |= PWR_CR_DBP;
memset(preserve_start, 0, preserve_end - preserve_start);
}
void SGM::clearResetFlag()
BackupDomain::BackupDomain()
{
RCC->CSR |= RCC_CSR_RMVF;
// Retrieve last reset reason and clear the pending flag
readResetRegister();
}
void SGM::readResetRegister()
void BackupDomain::clearResetFlag() { RCC->CSR |= RCC_CSR_RMVF; }
void BackupDomain::readResetRegister()
{
uint32_t resetReg = RCC->CSR;
clearResetFlag();
if (resetReg & RCC_CSR_LPWRRSTF)
{
lastReset = RST_LOW_PWR;
lastReset = ResetReason::RST_LOW_PWR;
}
else if (resetReg & RCC_CSR_WWDGRSTF)
{
lastReset = RST_WINDOW_WDG;
lastReset = ResetReason::RST_WINDOW_WDG;
}
else if( resetReg & RCC_CSR_WDGRSTF)
else if (resetReg & RCC_CSR_IWDGRSTF)
{
lastReset = RST_INDEPENDENT_WDG;
lastReset = ResetReason::RST_INDEPENDENT_WDG;
}
else if (resetReg & RCC_CSR_SFTRSTF)
{
lastReset = RST_SW;
lastReset = ResetReason::RST_SW;
}
else if (resetReg & RCC_CSR_PORRSTF)
{
lastReset = RST_POWER_ON;
lastReset = ResetReason::RST_POWER_ON;
}
else if( resetReg & RCC_CSR_PADRSTF)
else if (resetReg & RCC_CSR_PINRSTF)
{
lastReset = RST_PIN;
lastReset = ResetReason::RST_PIN;
}
else
{
lastReset = RST_UNKNOWN;
lastReset = ResetReason::RST_UNKNOWN;
}
}
......
miosix/arch/common/drivers/stm32_sgm.h → miosix/arch/common/drivers/stm32_backup_domain.h
View file @ ca9c636f
......@@ -29,46 +29,60 @@
#define PRESERVE __attribute__((section(".preserve")))
namespace miosix {
namespace miosix
{
/**
* Possible causes for an STM32 reset
*/
enum ResetReason
enum class ResetReason
{
RST_LOW_PWR=0,
RST_WINDOW_WDG=1,
RST_INDEPENDENT_WDG=2,
RST_SW=3,
RST_POWER_ON=4,
RST_PIN=5,
RST_UNKNOWN=6,
RST_LOW_PWR = 0, // Low power
RST_WINDOW_WDG = 1, // Reset from the windows watchdog
RST_INDEPENDENT_WDG = 2, // Reset from the independent watchdog
RST_SW = 3, // Software reset
RST_POWER_ON = 4, // System power on
RST_PIN = 5, // Reset pin
RST_UNKNOWN = 6, // Unknown
};
/**
* Driver for the STM32F2 and STM32F4 backup SRAM, here used as
* SafeGuard Memory, that is, a memory whose value is preseved across resets.
* Driver for the backup SRAM.
*
* @warning Tested only on stm32f2, stm32f4 and stm32f7 microcontrollers.
*/
class SGM
class BackupDomain
{
public:
/**
* \return an instance of this class (singleton)
* @return An instance of this class (singleton).
*/
static BackupDomain& instance();
/**
* Enables the backup domain clock and write access.
*/
void enable();
/**
* Disable the backup domain clock and write access.
*/
void disable();
/**
* Enable the backup SRAM.
*/
static SGM& instance();
void enableBackupSRAM();
/**
* Temporarily disable writing to the safeguard memory.
* By deafult, from reset to when the contrsuctor of this class is called
* the safeguard memory is not writable. After the constructor is called,
* the safeguard memory is writable.
* Disable the backup SRAM.
*/
void disableWrite();
void disableBackupSRAM();
/**
* Make the safeguard memory writable again, after a call to disableWrite()
* Clear the backup SRAM.
*/
void enableWrite();
void clearBackupSRAM();
/**
* Return the cause of the last reset of the micro controller
......@@ -78,14 +92,12 @@ public:
private:
ResetReason lastReset;
SGM(const SGM&)=delete;
SGM& operator=(const SGM&)=delete;
BackupDomain(const BackupDomain&) = delete;
BackupDomain& operator=(const BackupDomain&) = delete;
SGM();
BackupDomain();
void readResetRegister();
void clearResetFlag();
};
}
\ No newline at end of file
} // namespace miosix
\ No newline at end of file
miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp
View file @ ca9c636f
......@@ -45,7 +45,6 @@
#include "filesystem/console/console_device.h"
#include "drivers/serial.h"
#include "drivers/sd_stm32f2_f4_f7.h"
#include "drivers/stm32_sgm.h"
#include "board_settings.h"
namespace miosix {
......@@ -188,10 +187,6 @@ void configureSdram()
void IRQbspInit()
{
/* force Safe Guard Memory constructor call */
SGM::instance();
/*If using SDRAM GPIOs are enabled by configureSdram(), else enable them here */
#ifndef __ENABLE_XRAM
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
......
miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_rig/interfaces-impl/bsp.cpp
View file @ ca9c636f
......@@ -263,13 +263,13 @@ namespace miosix
timers::tim11ch1::mode(Mode::ALTERNATE);
timers::tim3ch1::mode(Mode::ALTERNATE);
timers::tim10ch1::mode(Mode::ALTERNATE);
timers::tim2ch2::mode(Mode::ALTERNATE);
timers::tim8ch1::mode(Mode::ALTERNATE);
timers::tim4ch2::alternateFunction(2);
timers::tim11ch1::alternateFunction(3);
timers::tim3ch1::alternateFunction(2);
timers::tim10ch1::alternateFunction(3);
timers::tim2ch2::alternateFunction(1);
timers::tim8ch1::alternateFunction(3);
using namespace sensors;
ADS131_1::cs::mode(Mode::OUTPUT);
......@@ -282,15 +282,15 @@ namespace miosix
MAX31855::cs::high();
using namespace relays;
relay1::mode(Mode::OUTPUT);
relay2::mode(Mode::OUTPUT);
relay3::mode(Mode::OUTPUT);
relay4::mode(Mode::OUTPUT);
relay1::high();
relay2::high();
relay3::high();
relay4::high();
ignition::mode(Mode::OUTPUT);
ledLamp::mode(Mode::OUTPUT);
nitrogen::mode(Mode::OUTPUT);
generalPurpose::mode(Mode::OUTPUT);
ignition::high();
ledLamp::high();
nitrogen::high();
generalPurpose::high();
using namespace radio;
cs::mode(Mode::OUTPUT);
......
miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_rig/interfaces-impl/hwmapping.h
View file @ ca9c636f
......@@ -83,7 +83,7 @@ using tim4ch2 = Gpio<GPIOB_BASE, 7>; // Servo 1
using tim11ch1 = Gpio<GPIOB_BASE, 9>; // Servo 2
using tim3ch1 = Gpio<GPIOB_BASE, 4>; // Servo 3
using tim10ch1 = Gpio<GPIOB_BASE, 8>; // Servo 4
using tim2ch2 = Gpio<GPIOB_BASE, 3>; // Servo 5
using tim8ch1 = Gpio<GPIOC_BASE, 6>; // Servo 5
} // namespace timers
} // namespace interfaces
......@@ -137,15 +137,15 @@ using servo1 = interfaces::timers::tim4ch2;
using servo2 = interfaces::timers::tim11ch1;
using servo3 = interfaces::timers::tim3ch1;
using servo4 = interfaces::timers::tim10ch1;
using servo5 = interfaces::timers::tim2ch2;
using servo5 = interfaces::timers::tim8ch1;
} // namespace servos
namespace relays
{
using relay1 = Gpio<GPIOC_BASE, 14>; // Ignition
using relay2 = Gpio<GPIOE_BASE, 3>; // Faro LED
using relay3 = Gpio<GPIOC_BASE, 13>; // Nitrogen
using relay4 = Gpio<GPIOA_BASE, 15>;
using ignition = Gpio<GPIOC_BASE, 14>;
using ledLamp = Gpio<GPIOE_BASE, 3>;
using nitrogen = Gpio<GPIOC_BASE, 13>;
using generalPurpose = Gpio<GPIOA_BASE, 15>;
} // namespace relays
namespace radio
......
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/core/stage_1_boot.cpp 0 → 100644
View file @ ca9c636f
#include <string.h>
#include "core/cache_cortexMx.h"
#include "core/interrupts.h" //For the unexpected interrupt call
#include "core/interrupts_cortexMx.h"
#include "interfaces/arch_registers.h"
#include "interfaces/bsp.h"
#include "kernel/stage_2_boot.h"
/*
* startup.cpp
* STM32 C++ startup.
* NOTE: for stm32f767 devices ONLY.
* Supports interrupt handlers in C++ without extern "C"
* Developed by Terraneo Federico, based on ST startup code.
* Additionally modified to boot Miosix.
*/
/**
* Called by Reset_Handler, performs initialization and calls main.
* Never returns.
*/
void program_startup() __attribute__((noreturn));
void program_startup()
{
//Cortex M7 core appears to get out of reset with interrupts already enabled
__disable_irq();
miosix::IRQconfigureCache((const unsigned int*)0xd0000000, 8 * 1024 * 1024);
// These are defined in the linker script
extern unsigned char _etext asm("_etext");
extern unsigned char _data asm("_data");
extern unsigned char _edata asm("_edata");
extern unsigned char _bss_start asm("_bss_start");
extern unsigned char _bss_end asm("_bss_end");
// Initialize .data section, clear .bss section
unsigned char *etext=&_etext;
unsigned char *data=&_data;
unsigned char *edata=&_edata;
unsigned char *bss_start=&_bss_start;
unsigned char *bss_end=&_bss_end;
memcpy(data, etext, edata-data);
memset(bss_start, 0, bss_end-bss_start);
// Move on to stage 2
_init();
// If main returns, reboot
NVIC_SystemReset();
for(;;) ;
}
/**
* Reset handler, called by hardware immediately after reset
*/
void Reset_Handler() __attribute__((__interrupt__, noreturn));
void Reset_Handler()
{
/**
* SystemInit() is called *before* initializing .data and zeroing .bss
* Despite all startup files provided by ST do the opposite, there are three
* good reasons to do so:
* 1. First, the CMSIS specifications say that SystemInit() must not access
* global variables, so it is actually possible to call it before
* 2. Second, when running Miosix with the xram linker scripts .data and
* .bss are placed in the external RAM, so we *must* call SystemInit(),
* which enables xram, before touching .data and .bss
* 3. Third, this is a performance improvement since the loops that
* initialize .data and zeros .bss now run with the CPU at full speed
* instead of 8MHz
*/
SystemInit();
/**
* ST does not provide code to initialize the SDRAM at boot.
* Put after SystemInit() as SDRAM is timing-sensitive and needs the full
* clock speed.
*/
#ifdef __ENABLE_XRAM
miosix::configureSdram();
#endif //__ENABLE_XRAM
/*
* Load into the program stack pointer the heap end address and switch from
* the msp to sps.
* This is required for booting Miosix, a small portion of the top of the
* heap area will be used as stack until the first thread starts. After,
* this stack will be abandoned and the process stack will point to the
* current thread's stack.
*/
asm volatile(
"ldr r0, =_heap_end \n\t"
"msr psp, r0 \n\t"
"movw r0, #2 \n\n" // Set the control register to use
"msr control, r0 \n\t" // the process stack
"isb \n\t":::"r0");
program_startup();
}
/**
* All unused interrupts call this function.
*/
extern "C" void Default_Handler() { unexpectedInterrupt(); }
// System handlers
void /*__attribute__((weak))*/ Reset_Handler(); // These interrupts are not
void /*__attribute__((weak))*/ NMI_Handler(); // weak because they are
void /*__attribute__((weak))*/ HardFault_Handler(); // surely defined by Miosix
void /*__attribute__((weak))*/ MemManage_Handler();
void /*__attribute__((weak))*/ BusFault_Handler();
void /*__attribute__((weak))*/ UsageFault_Handler();
void /*__attribute__((weak))*/ SVC_Handler();
void /*__attribute__((weak))*/ DebugMon_Handler();
void /*__attribute__((weak))*/ PendSV_Handler();
void /*__attribute__((weak))*/ SysTick_Handler();
// Interrupt handlers
void __attribute__((weak)) WWDG_IRQHandler();
void __attribute__((weak)) PVD_IRQHandler();
void __attribute__((weak)) TAMP_STAMP_IRQHandler();
void __attribute__((weak)) RTC_WKUP_IRQHandler();
void __attribute__((weak)) FLASH_IRQHandler();
void __attribute__((weak)) RCC_IRQHandler();
void __attribute__((weak)) EXTI0_IRQHandler();
void __attribute__((weak)) EXTI1_IRQHandler();
void __attribute__((weak)) EXTI2_IRQHandler();
void __attribute__((weak)) EXTI3_IRQHandler();
void __attribute__((weak)) EXTI4_IRQHandler();
void __attribute__((weak)) DMA1_Stream0_IRQHandler();
void __attribute__((weak)) DMA1_Stream1_IRQHandler();
void __attribute__((weak)) DMA1_Stream2_IRQHandler();
void __attribute__((weak)) DMA1_Stream3_IRQHandler();
void __attribute__((weak)) DMA1_Stream4_IRQHandler();
void __attribute__((weak)) DMA1_Stream5_IRQHandler();
void __attribute__((weak)) DMA1_Stream6_IRQHandler();
void __attribute__((weak)) ADC_IRQHandler();
void __attribute__((weak)) CAN1_TX_IRQHandler();
void __attribute__((weak)) CAN1_RX0_IRQHandler();
void __attribute__((weak)) CAN1_RX1_IRQHandler();
void __attribute__((weak)) CAN1_SCE_IRQHandler();
void __attribute__((weak)) EXTI9_5_IRQHandler();
void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler();
void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler();
void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler();
void __attribute__((weak)) TIM1_CC_IRQHandler();
void __attribute__((weak)) TIM2_IRQHandler();
void __attribute__((weak)) TIM3_IRQHandler();
void __attribute__((weak)) TIM4_IRQHandler();
void __attribute__((weak)) I2C1_EV_IRQHandler();
void __attribute__((weak)) I2C1_ER_IRQHandler();
void __attribute__((weak)) I2C2_EV_IRQHandler();
void __attribute__((weak)) I2C2_ER_IRQHandler();
void __attribute__((weak)) SPI1_IRQHandler();
void __attribute__((weak)) SPI2_IRQHandler();
void __attribute__((weak)) USART1_IRQHandler();
void __attribute__((weak)) USART2_IRQHandler();
void __attribute__((weak)) USART3_IRQHandler();
void __attribute__((weak)) EXTI15_10_IRQHandler();
void __attribute__((weak)) RTC_Alarm_IRQHandler();
void __attribute__((weak)) OTG_FS_WKUP_IRQHandler();
void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler();
void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler();
void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler();
void __attribute__((weak)) TIM8_CC_IRQHandler();
void __attribute__((weak)) DMA1_Stream7_IRQHandler();
void __attribute__((weak)) FMC_IRQHandler();
void __attribute__((weak)) SDMMC1_IRQHandler();
void __attribute__((weak)) TIM5_IRQHandler();
void __attribute__((weak)) SPI3_IRQHandler();
void __attribute__((weak)) UART4_IRQHandler();
void __attribute__((weak)) UART5_IRQHandler();
void __attribute__((weak)) TIM6_DAC_IRQHandler();
void __attribute__((weak)) TIM7_IRQHandler();
void __attribute__((weak)) DMA2_Stream0_IRQHandler();
void __attribute__((weak)) DMA2_Stream1_IRQHandler();
void __attribute__((weak)) DMA2_Stream2_IRQHandler();
void __attribute__((weak)) DMA2_Stream3_IRQHandler();
void __attribute__((weak)) DMA2_Stream4_IRQHandler();
void __attribute__((weak)) ETH_IRQHandler();
void __attribute__((weak)) ETH_WKUP_IRQHandler();
void __attribute__((weak)) CAN2_TX_IRQHandler();
void __attribute__((weak)) CAN2_RX0_IRQHandler();
void __attribute__((weak)) CAN2_RX1_IRQHandler();
void __attribute__((weak)) CAN2_SCE_IRQHandler();
void __attribute__((weak)) OTG_FS_IRQHandler();
void __attribute__((weak)) DMA2_Stream5_IRQHandler();
void __attribute__((weak)) DMA2_Stream6_IRQHandler();
void __attribute__((weak)) DMA2_Stream7_IRQHandler();
void __attribute__((weak)) USART6_IRQHandler();
void __attribute__((weak)) I2C3_EV_IRQHandler();
void __attribute__((weak)) I2C3_ER_IRQHandler();
void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler();
void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler();
void __attribute__((weak)) OTG_HS_WKUP_IRQHandler();
void __attribute__((weak)) OTG_HS_IRQHandler();
void __attribute__((weak)) DCMI_IRQHandler();
void __attribute__((weak)) CRYP_IRQHandler();
void __attribute__((weak)) RNG_IRQHandler();
void __attribute__((weak)) FPU_IRQHandler();
void __attribute__((weak)) UART7_IRQHandler();
void __attribute__((weak)) UART8_IRQHandler();
void __attribute__((weak)) SPI4_IRQHandler();
void __attribute__((weak)) SPI5_IRQHandler();
void __attribute__((weak)) SPI6_IRQHandler();
void __attribute__((weak)) SAI1_IRQHandler();
void __attribute__((weak)) LTDC_IRQHandler();
void __attribute__((weak)) LTDC_ER_IRQHandler();
void __attribute__((weak)) DMA2D_IRQHandler();
void __attribute__((weak)) SAI2_IRQHandler();
void __attribute__((weak)) QUADSPI_IRQHandler();
void __attribute__((weak)) LPTIM1_IRQHandler();
void __attribute__((weak)) CEC_IRQHandler();
void __attribute__((weak)) I2C4_EV_IRQHandler();
void __attribute__((weak)) I2C4_ER_IRQHandler();
void __attribute__((weak)) SPDIF_RX_IRQHandler();
void __attribute__((weak)) DSIHOST_IRQHandler();
void __attribute__((weak)) DFSDM1_FLT0_IRQHandler();
void __attribute__((weak)) DFSDM1_FLT1_IRQHandler();
void __attribute__((weak)) DFSDM1_FLT2_IRQHandler();
void __attribute__((weak)) DFSDM1_FLT3_IRQHandler();
void __attribute__((weak)) SDMMC2_IRQHandler();
void __attribute__((weak)) CAN3_TX_IRQHandler();
void __attribute__((weak)) CAN3_RX0_IRQHandler();
void __attribute__((weak)) CAN3_RX1_IRQHandler();
void __attribute__((weak)) CAN3_SCE_IRQHandler();
void __attribute__((weak)) JPEG_IRQHandler();
void __attribute__((weak)) MDIOS_IRQHandler();
// Stack top, defined in the linker script
extern char _main_stack_top asm("_main_stack_top");
// Interrupt vectors, must be placed @ address 0x00000000
// The extern declaration is required otherwise g++ optimizes it out
extern void (*const __Vectors[])();
void (*const __Vectors[])() __attribute__((section(".isr_vector"))) =
{
reinterpret_cast<void (*)()>(&_main_stack_top), /* Stack pointer*/
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
HardFault_Handler, /* Hard Fault Handler */
MemManage_Handler, /* MPU Fault Handler */
BusFault_Handler, /* Bus Fault Handler */
UsageFault_Handler, /* Usage Fault Handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
SVC_Handler, /* SVCall Handler */
DebugMon_Handler, /* Debug Monitor Handler */
0, /* Reserved */
PendSV_Handler, /* PendSV Handler */
SysTick_Handler, /* SysTick Handler */
/* External Interrupts */
WWDG_IRQHandler,
PVD_IRQHandler,
TAMP_STAMP_IRQHandler,
RTC_WKUP_IRQHandler,
FLASH_IRQHandler,
RCC_IRQHandler,
EXTI0_IRQHandler,
EXTI1_IRQHandler,
EXTI2_IRQHandler,
EXTI3_IRQHandler,
EXTI4_IRQHandler,
DMA1_Stream0_IRQHandler,
DMA1_Stream1_IRQHandler,
DMA1_Stream2_IRQHandler,
DMA1_Stream3_IRQHandler,
DMA1_Stream4_IRQHandler,
DMA1_Stream5_IRQHandler,
DMA1_Stream6_IRQHandler,
ADC_IRQHandler,
CAN1_TX_IRQHandler,
CAN1_RX0_IRQHandler,
CAN1_RX1_IRQHandler,
CAN1_SCE_IRQHandler,
EXTI9_5_IRQHandler,
TIM1_BRK_TIM9_IRQHandler,
TIM1_UP_TIM10_IRQHandler,
TIM1_TRG_COM_TIM11_IRQHandler,
TIM1_CC_IRQHandler,
TIM2_IRQHandler,
TIM3_IRQHandler,
TIM4_IRQHandler,
I2C1_EV_IRQHandler,
I2C1_ER_IRQHandler,
I2C2_EV_IRQHandler,
I2C2_ER_IRQHandler,
SPI1_IRQHandler,
SPI2_IRQHandler,
USART1_IRQHandler,
USART2_IRQHandler,
USART3_IRQHandler,
EXTI15_10_IRQHandler,
RTC_Alarm_IRQHandler,
OTG_FS_WKUP_IRQHandler,
TIM8_BRK_TIM12_IRQHandler,
TIM8_UP_TIM13_IRQHandler,
TIM8_TRG_COM_TIM14_IRQHandler,
TIM8_CC_IRQHandler,
DMA1_Stream7_IRQHandler,
FMC_IRQHandler,
SDMMC1_IRQHandler,
TIM5_IRQHandler,
SPI3_IRQHandler,
UART4_IRQHandler,
UART5_IRQHandler,
TIM6_DAC_IRQHandler,
TIM7_IRQHandler,
DMA2_Stream0_IRQHandler,
DMA2_Stream1_IRQHandler,
DMA2_Stream2_IRQHandler,
DMA2_Stream3_IRQHandler,
DMA2_Stream4_IRQHandler,
ETH_IRQHandler,
ETH_WKUP_IRQHandler,
CAN2_TX_IRQHandler,
CAN2_RX0_IRQHandler,
CAN2_RX1_IRQHandler,
CAN2_SCE_IRQHandler,
OTG_FS_IRQHandler,
DMA2_Stream5_IRQHandler,
DMA2_Stream6_IRQHandler,
DMA2_Stream7_IRQHandler,
USART6_IRQHandler,
I2C3_EV_IRQHandler,
I2C3_ER_IRQHandler,
OTG_HS_EP1_OUT_IRQHandler,
OTG_HS_EP1_IN_IRQHandler,
OTG_HS_WKUP_IRQHandler,
OTG_HS_IRQHandler,
DCMI_IRQHandler,
CRYP_IRQHandler,
RNG_IRQHandler,
FPU_IRQHandler,
UART7_IRQHandler,
UART8_IRQHandler,
SPI4_IRQHandler,
SPI5_IRQHandler,
SPI6_IRQHandler,
SAI1_IRQHandler,
LTDC_IRQHandler,
LTDC_ER_IRQHandler,
DMA2D_IRQHandler,
SAI2_IRQHandler,
QUADSPI_IRQHandler,
LPTIM1_IRQHandler,
CEC_IRQHandler,
I2C4_EV_IRQHandler,
I2C4_ER_IRQHandler,
SPDIF_RX_IRQHandler,
DSIHOST_IRQHandler,
DFSDM1_FLT0_IRQHandler,
DFSDM1_FLT1_IRQHandler,
DFSDM1_FLT2_IRQHandler,
DFSDM1_FLT3_IRQHandler,
SDMMC2_IRQHandler,
CAN3_TX_IRQHandler,
CAN3_RX0_IRQHandler,
CAN3_RX1_IRQHandler,
CAN3_SCE_IRQHandler,
JPEG_IRQHandler,
MDIOS_IRQHandler,
};
#pragma weak WWDG_IRQHandler = Default_Handler
#pragma weak PVD_IRQHandler = Default_Handler
#pragma weak TAMP_STAMP_IRQHandler = Default_Handler
#pragma weak RTC_WKUP_IRQHandler = Default_Handler
#pragma weak FLASH_IRQHandler = Default_Handler
#pragma weak RCC_IRQHandler = Default_Handler
#pragma weak EXTI0_IRQHandler = Default_Handler
#pragma weak EXTI1_IRQHandler = Default_Handler
#pragma weak EXTI2_IRQHandler = Default_Handler
#pragma weak EXTI3_IRQHandler = Default_Handler
#pragma weak EXTI4_IRQHandler = Default_Handler
#pragma weak DMA1_Stream0_IRQHandler = Default_Handler
#pragma weak DMA1_Stream1_IRQHandler = Default_Handler
#pragma weak DMA1_Stream2_IRQHandler = Default_Handler
#pragma weak DMA1_Stream3_IRQHandler = Default_Handler
#pragma weak DMA1_Stream4_IRQHandler = Default_Handler
#pragma weak DMA1_Stream5_IRQHandler = Default_Handler
#pragma weak DMA1_Stream6_IRQHandler = Default_Handler
#pragma weak ADC_IRQHandler = Default_Handler
#pragma weak CAN1_TX_IRQHandler = Default_Handler
#pragma weak CAN1_RX0_IRQHandler = Default_Handler
#pragma weak CAN1_RX1_IRQHandler = Default_Handler
#pragma weak CAN1_SCE_IRQHandler = Default_Handler
#pragma weak EXTI9_5_IRQHandler = Default_Handler
#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler
#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler
#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler
#pragma weak TIM1_CC_IRQHandler = Default_Handler
#pragma weak TIM2_IRQHandler = Default_Handler
#pragma weak TIM3_IRQHandler = Default_Handler
#pragma weak TIM4_IRQHandler = Default_Handler
#pragma weak I2C1_EV_IRQHandler = Default_Handler
#pragma weak I2C1_ER_IRQHandler = Default_Handler
#pragma weak I2C2_EV_IRQHandler = Default_Handler
#pragma weak I2C2_ER_IRQHandler = Default_Handler
#pragma weak SPI1_IRQHandler = Default_Handler
#pragma weak SPI2_IRQHandler = Default_Handler
// #pragma weak USART1_IRQHandler = Default_Handler
// #pragma weak USART2_IRQHandler = Default_Handler
// #pragma weak USART3_IRQHandler = Default_Handler
#pragma weak EXTI15_10_IRQHandler = Default_Handler
#pragma weak RTC_Alarm_IRQHandler = Default_Handler
#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler
#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler
#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler
#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler
#pragma weak TIM8_CC_IRQHandler = Default_Handler
#pragma weak DMA1_Stream7_IRQHandler = Default_Handler
#pragma weak FMC_IRQHandler = Default_Handler
#pragma weak SDMMC1_IRQHandler = Default_Handler
#pragma weak TIM5_IRQHandler = Default_Handler
#pragma weak SPI3_IRQHandler = Default_Handler
#pragma weak UART4_IRQHandler = Default_Handler
#pragma weak UART5_IRQHandler = Default_Handler
#pragma weak TIM6_DAC_IRQHandler = Default_Handler
#pragma weak TIM7_IRQHandler = Default_Handler
#pragma weak DMA2_Stream0_IRQHandler = Default_Handler
#pragma weak DMA2_Stream1_IRQHandler = Default_Handler
#pragma weak DMA2_Stream2_IRQHandler = Default_Handler
#pragma weak DMA2_Stream3_IRQHandler = Default_Handler
#pragma weak DMA2_Stream4_IRQHandler = Default_Handler
#pragma weak ETH_IRQHandler = Default_Handler
#pragma weak ETH_WKUP_IRQHandler = Default_Handler
#pragma weak CAN2_TX_IRQHandler = Default_Handler
#pragma weak CAN2_RX0_IRQHandler = Default_Handler
#pragma weak CAN2_RX1_IRQHandler = Default_Handler
#pragma weak CAN2_SCE_IRQHandler = Default_Handler
#pragma weak OTG_FS_IRQHandler = Default_Handler
#pragma weak DMA2_Stream5_IRQHandler = Default_Handler
#pragma weak DMA2_Stream6_IRQHandler = Default_Handler
#pragma weak DMA2_Stream7_IRQHandler = Default_Handler
#pragma weak USART6_IRQHandler = Default_Handler
#pragma weak I2C3_EV_IRQHandler = Default_Handler
#pragma weak I2C3_ER_IRQHandler = Default_Handler
#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler
#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler
#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler
#pragma weak OTG_HS_IRQHandler = Default_Handler
#pragma weak DCMI_IRQHandler = Default_Handler
#pragma weak CRYP_IRQHandler = Default_Handler
#pragma weak RNG_IRQHandler = Default_Handler
#pragma weak FPU_IRQHandler = Default_Handler
#pragma weak UART7_IRQHandler = Default_Handler
#pragma weak UART8_IRQHandler = Default_Handler
#pragma weak SPI4_IRQHandler = Default_Handler
#pragma weak SPI5_IRQHandler = Default_Handler
#pragma weak SPI6_IRQHandler = Default_Handler
#pragma weak SAI1_IRQHandler = Default_Handler
#pragma weak LTDC_IRQHandler = Default_Handler
#pragma weak LTDC_ER_IRQHandler = Default_Handler
#pragma weak DMA2D_IRQHandler = Default_Handler
#pragma weak SAI2_IRQHandler = Default_Handler
#pragma weak QUADSPI_IRQHandler = Default_Handler
#pragma weak LPTIM1_IRQHandler = Default_Handler
#pragma weak CEC_IRQHandler = Default_Handler
#pragma weak I2C4_EV_IRQHandler = Default_Handler
#pragma weak I2C4_ER_IRQHandler = Default_Handler
#pragma weak SPDIF_RX_IRQHandler = Default_Handler
#pragma weak DSIHOST_IRQHandler = Default_Handler
#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler
#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler
#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler
#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler
#pragma weak SDMMC2_IRQHandler = Default_Handler
#pragma weak CAN3_TX_IRQHandler = Default_Handler
#pragma weak CAN3_RX0_IRQHandler = Default_Handler
#pragma weak CAN3_RX1_IRQHandler = Default_Handler
#pragma weak CAN3_SCE_IRQHandler = Default_Handler
#pragma weak JPEG_IRQHandler = Default_Handler
#pragma weak MDIOS_IRQHandler = Default_Handler
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/arch_registers_impl.h 0 → 100644
View file @ ca9c636f
#ifndef ARCH_REGISTERS_IMPL_H
#define ARCH_REGISTERS_IMPL_H
// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and
// includes core_cm7.h. Do not include core_cm7.h before.
#define STM32F767xx
#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h"
#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1)
#error "Wrong include order"
#endif
#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h"
#define RCC_SYNC() __DSB() // TODO: can this dsb be removed?
#endif // ARCH_REGISTERS_IMPL_H
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp.cpp 0 → 100644
View file @ ca9c636f
/***************************************************************************
* Copyright (C) 2018 by Terraneo Federico *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or use *
* macros or inline functions from this file, or you compile this file *
* and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with the GNU General *
* Public License. This exception does not invalidate any other reasons *
* why a work based on this file might be covered by the GNU General *
* Public License. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
/***********************************************************************
* bsp.cpp Part of the Miosix Embedded OS.
* Board support package, this file initializes hardware.
************************************************************************/
#include "interfaces/bsp.h"
#include <inttypes.h>
#include <sys/ioctl.h>
#include <cstdlib>
#include "board_settings.h"
#include "config/miosix_settings.h"
#include "drivers/sd_stm32f2_f4_f7.h"
#include "drivers/serial.h"
#include "drivers/serial_stm32.h"
#include "drivers/stm32_backup_domain.h"
#include "filesystem/console/console_device.h"
#include "filesystem/file_access.h"
#include "interfaces/arch_registers.h"
#include "interfaces/delays.h"
#include "interfaces/portability.h"
#include "kernel/kernel.h"
#include "kernel/logging.h"
#include "kernel/sync.h"
namespace miosix {
//
// Initialization
//
static void sdramCommandWait()
{
for(int i=0;i<0xffff;i++)
if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0)
return;
}
void configureSdram() {
// Enable gpios used by the ram
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN |
RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN |
RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN;
RCC_SYNC();
// On the compute unit with F767ZI, the SDRAM pins are:
// - PG8: FMC_SDCLK (sdram clock)
// - PB5: FMC_SDCKE1 (sdram bank 2 clock enable)
// - PB6: FMC_SDNE1 (sdram bank 2 chip enable)
// - PF0: FMC_A0
// - PF1: FMC_A1
// - PF2: FMC_A2
// - PF3: FMC_A3
// - PF4: FMC_A4
// - PF5: FMC_A5
// - PF12: FMC_A6
// - PF13: FMC_A7
// - PF14: FMC_A8
// - PF15: FMC_A9
// - PG0: FMC_A10
// - PG1: FMC_A11
// - PG2: FMC_A12 (used only by the 32MB ram, not by the 8MB one)
// - PD14: FMC_D0
// - PD15: FMC_D1
// - PD0: FMC_D2
// - PD1: FMC_D3
// - PE7: FMC_D4
// - PE8: FMC_D5
// - PE9: FMC_D6
// - PE10: FMC_D7
// - PE11: FMC_D8
// - PE12: FMC_D9
// - PE13: FMC_D10
// - PE14: FMC_D11
// - PE15: FMC_D12
// - PD8: FMC_D13
// - PD9: FMC_D14
// - PD10: FMC_D15
// - PG4: FMC_BA0
// - PG5: FMC_BA1
// - PF11: FMC_SDNRAS
// - PG15: FMC_SDNCAS
// - PC0: FMC_SDNWE
// - PE0: FMC_NBL0
// - PE1: FMC_NBL1
// All SDRAM GPIOs needs to be configured with alternate function 12 and
// maximum speed
// WARNING: The current configuration is for the 8MB ram
// Alternate functions
GPIOB->AFR[0] = 0x0cc00000;
GPIOC->AFR[0] = 0x0000000c;
GPIOD->AFR[0] = 0x000000cc;
GPIOD->AFR[1] = 0xcc000ccc;
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xccccc000;
GPIOG->AFR[0] = 0x00cc00cc;
GPIOG->AFR[1] = 0xc000000c;
// Mode
GPIOB->MODER = 0x00002800;
GPIOC->MODER = 0x00000002;
GPIOD->MODER = 0xa02a000a;
GPIOE->MODER = 0xaaaa800a;
GPIOF->MODER = 0xaa800aaa;
GPIOG->MODER = 0x80020a0a;
// Speed (high speed for all, very high speed for SDRAM pins)
GPIOB->OSPEEDR = 0x00003c00;
GPIOC->OSPEEDR = 0x00000003;
GPIOD->OSPEEDR = 0xf03f000f;
GPIOE->OSPEEDR = 0xffffc00f;
GPIOF->OSPEEDR = 0xffc00fff;
GPIOG->OSPEEDR = 0xc0030f0f;
// Since we'we un-configured PB3 and PB4 (by default they are SWO and NJRST)
// finish the job and remove the default pull-up
GPIOB->PUPDR = 0;
// Enable the SDRAM controller clock
RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN;
RCC_SYNC();
// The SDRAM is a AS4C4M16SA-6TAN
// HCLK = 216MHz -> SDRAM clock = HCLK/2 = 133MHz
// 1. Memory device features
FMC_Bank5_6->SDCR[0] = 0 // 0 delay after CAS latency
| FMC_SDCR1_RBURST // Enable read bursts
| FMC_SDCR1_SDCLK_1; // SDCLK = HCLK / 2
FMC_Bank5_6->SDCR[1] = 0 // Write accesses allowed
| FMC_SDCR2_CAS_1 // 2 cycles CAS latency
| FMC_SDCR2_NB // 4 internal banks
| FMC_SDCR2_MWID_0 // 16 bit data bus
| FMC_SDCR2_NR_0 // 12 bit row address
| 0; // 8 bit column address
// 2. Memory device timings
#ifdef SYSCLK_FREQ_216MHz
// SDRAM timings. One clock cycle is 9.26ns
FMC_Bank5_6->SDTR[0] = (2 - 1) << FMC_SDTR1_TRP_Pos // 2 cycles TRP (18.52ns > 18ns)
| (7 - 1) << FMC_SDTR1_TRC_Pos; // 7 cycles TRC (64.82ns > 60ns)
FMC_Bank5_6->SDTR[1] = (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns)
| (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (min 2 clock cycles)
| (5 - 1) << FMC_SDTR1_TRAS_Pos // 5 cycles TRAS (46.3ns > 42ns)
| (7 - 1) << FMC_SDTR1_TXSR_Pos // 7 cycles TXSR (74.08ns > 61.5ns)
| (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (min 2 clock cycles)
#else
#error No SDRAM timings for this clock
#endif
// 3. Enable the bank 2 clock
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_0 // Clock Configuration Enable
| FMC_SDCMR_CTB2; // Bank 2
sdramCommandWait();
// 4. Wait during command execution
delayUs(100);
// 5. Issue a "Precharge All" command
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 // Precharge all
| FMC_SDCMR_CTB2; // Bank 2
sdramCommandWait();
// 6. Issue Auto-Refresh commands
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 | FMC_SDCMR_MODE_0 // Auto-Refresh
| FMC_SDCMR_CTB2 // Bank 2
| (8 - 1) << FMC_SDCMR_NRFS_Pos; // 2 Auto-Refresh
sdramCommandWait();
// 7. Issue a Load Mode Register command
FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_2 /// Load mode register
| FMC_SDCMR_CTB2 // Bank 2
| 0x220 << FMC_SDCMR_MRD_Pos; // CAS = 2, burst = 1
sdramCommandWait();
// 8. Program the refresh rate (4K / 32ms)
// 32ms / 4096 = 7.8125us
#ifdef SYSCLK_FREQ_216MHz
// 7.8125us * 108MHz = 843 - 20 = 823
FMC_Bank5_6->SDRTR = 823 << FMC_SDRTR_COUNT_Pos;
#else
#error No SDRAM refresh timings for this clock
#endif
}
void IRQbspInit() {
// Enable USART1 pins port
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
userLed1::mode(Mode::OUTPUT);
userLed2::mode(Mode::OUTPUT);
userLed3::mode(Mode::OUTPUT);
userLed4::mode(Mode::OUTPUT);
userSwitch::mode(Mode::INPUT);
DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>(new STM32Serial(
defaultSerial, defaultSerialSpeed, STM32Serial::NOFLOWCTRL)));
}
void bspInit2() {
#ifdef WITH_FILESYSTEM
basicFilesystemSetup(SDIODriver::instance());
#endif // WITH_FILESYSTEM
#ifdef WITH_BACKUP_SRAM
BackupDomain::instance().enable();
BackupDomain::instance().enableBackupSRAM();
#endif
// Print the reset reason
bootlog("Reset reson: ");
switch(BackupDomain::instance().lastResetReason()) {
case ResetReason::RST_LOW_PWR:
bootlog("low power\n");
break;
case ResetReason::RST_WINDOW_WDG:
bootlog("window watchdog\n");
break;
case ResetReason::RST_INDEPENDENT_WDG:
bootlog("indeendent watchdog\n");
break;
case ResetReason::RST_SW:
bootlog("software reset\n");
break;
case ResetReason::RST_POWER_ON:
bootlog("power on\n");
break;
case ResetReason::RST_PIN:
bootlog("reset pin\n");
break;
case ResetReason::RST_UNKNOWN:
bootlog("unknown\n");
break;
}
}
//
// Shutdown and reboot
//
void shutdown()
{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
#ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
#endif // WITH_FILESYSTEM
disableInterrupts();
for(;;) ;
}
void reboot()
{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
#ifdef WITH_FILESYSTEM
FilesystemManager::instance().umountAll();
#endif // WITH_FILESYSTEM
disableInterrupts();
miosix_private::IRQsystemReboot();
}
} // namespace miosix
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/interfaces-impl/bsp_impl.h 0 → 100644
View file @ ca9c636f
/***************************************************************************
* Copyright (C) 2018 by Terraneo Federico *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* As a special exception, if other files instantiate templates or use *
* macros or inline functions from this file, or you compile this file *
* and link it with other works to produce a work based on this file, *
* this file does not by itself cause the resulting work to be covered *
* by the GNU General Public License. However the source code for this *
* file must still be made available in accordance with the GNU General *
* Public License. This exception does not invalidate any other reasons *
* why a work based on this file might be covered by the GNU General *
* Public License. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, see <http://www.gnu.org/licenses/> *
***************************************************************************/
/***************************************************************************
* bsp_impl.h Part of the Miosix Embedded OS.
* Board support package, this file initializes hardware.
***************************************************************************/
#ifndef BSP_IMPL_H
#define BSP_IMPL_H
#include "config/miosix_settings.h"
#include "interfaces/gpio.h"
namespace miosix
{
/**
\addtogroup Hardware
\{
*/
/**
* \internal
* Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss
* Requires the CPU clock to be already configured (running from the PLL)
*/
void configureSdram();
/**
* \internal
* Board pin definition
*/
typedef Gpio<GPIOB_BASE, 7> userLed1;
typedef Gpio<GPIOE_BASE, 3> userLed2;
typedef Gpio<GPIOC_BASE, 13> userLed3;
typedef Gpio<GPIOC_BASE, 2> userLed4;
typedef Gpio<GPIOB_BASE, 2> userSwitch;
inline void ledOn()
{
userLed1::high();
userLed2::high();
userLed3::high();
userLed4::high();
}
inline void ledOff()
{
userLed1::low();
userLed2::low();
userLed3::low();
userLed4::low();
}
inline void led1On() { userLed1::high(); }
inline void led1Off() { userLed1::low(); }
inline void led2On() { userLed2::high(); }
inline void led2Off() { userLed2::low(); }
inline void led3On() { userLed3::high(); }
inline void led3Off() { userLed3::low(); }
/**
* Polls the SD card sense GPIO.
*
* This board has no SD card whatsoever, but a card can be connected to the
* following GPIOs:
* TODO: never tested
*
* \return true. As there's no SD card sense switch, let's pretend that
* the card is present.
*/
inline bool sdCardSense() { return true; }
/**
\}
*/
} // namespace miosix
#endif // BSP_IMPL_H
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+384k_ram.ld 0 → 100644
View file @ ca9c636f
/*
* C++ enabled linker script for stm32f767zi (2M FLASH, 512K RAM)
* Developed by TFT: Terraneo Federico Technologies
* Optimized for use with the Miosix kernel
*/
/*
* This linker script puts:
* - read only data and code (.text, .rodata, .eh_*) in FLASH
* - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM
* - .data, .bss, stacks and heap in the internal RAM.
*/
/*
* The main stack is used for interrupt handling by the kernel.
*
* *** Readme ***
* This linker script places the main stack (used by the kernel for interrupts)
* at the bottom of the ram, instead of the top. This is done for two reasons:
*
* - as an optimization for microcontrollers with little ram memory. In fact
* the implementation of malloc from newlib requests memory to the OS in 4KB
* block (except the first block that can be smaller). This is probably done
* for compatibility with OSes with an MMU and paged memory. To see why this
* is bad, consider a microcontroller with 8KB of ram: when malloc finishes
* up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
* fail because the top part of the ram is used by the main stack. As a
* result, the top part of the memory will not be used by malloc, even if
* available (and it is nearly *half* the ram on an 8KB mcu). By placing the
* main stack at the bottom of the ram, the upper 4KB block will be entirely
* free and available as heap space.
*
* - In case of main stack overflow the cpu will fault because access to memory
* before the beginning of the ram faults. Instead with the default stack
* placement the main stack will silently collide with the heap.
* Note: if increasing the main stack size also increase the ORIGIN value in
* the MEMORY definitions below accordingly.
*/
_main_stack_size = 512; /* main stack = 512Bytes */
_main_stack_top = 0x20000000 + _main_stack_size;
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
/* Mapping the heap to the end of SRAM2 */
_heap_end = 0x20000000 + 512K; /* end of available ram */
/* Identify the Entry Point */
ENTRY(_Z13Reset_Handlerv)
/*
* Specify the memory areas
*
* NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled
* Memory). Technically, we could use this as normal RAM as there's a way for
* the DMA to access it, but the datasheet is unclear about performance
* penalties for doing so. To avoid nonuniform DMA memory access latencies,
* we leave this 128KB DTCM unused except for the first 512Bytes which are for
* the interrupt stack. This leaves us with 384KB of RAM
*/
MEMORY
{
sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K
dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */
bram(rw) : ORIGIN = 0x40024000, LENGTH = 4K /* Bakup SRAM */
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M
}
/* now define the output sections */
SECTIONS
{
. = 0;
/* .text section: code goes to flash */
.text :
{
/* Startup code must go at address 0 */
KEEP(*(.isr_vector))
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
/* these sections for thumb interwork? */
*(.glue_7)
*(.glue_7t)
/* these sections for C++? */
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.ARM.extab*)
*(.gnu.linkonce.armextab.*)
. = ALIGN(4);
/* .rodata: constant data */
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
/* C++ Static constructors/destructors (eabi) */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__miosix_init_array_start = .;
KEEP (*(SORT(.miosix_init_array.*)))
KEEP (*(.miosix_init_array))
__miosix_init_array_end = .;
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
/* C++ Static constructors/destructors (elf) */
. = ALIGN(4);
_ctor_start = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
_ctor_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > flash
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/*
* .data section: global variables go to sram, but also store a copy to
* flash to initialize them
*/
.data : ALIGN(8)
{
_data = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_edata = .;
} > sram AT > flash
_etext = LOADADDR(.data);
/* .bss section: uninitialized global variables go to sram */
_bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
. = ALIGN(8);
} > sram
_bss_end = .;
_end = .;
PROVIDE(end = .);
.preserve(NOLOAD) : ALIGN(4)
{
_preserve_start = .;
. = ALIGN(4);
*(.preserve);
*(.preserve*);
. = ALIGN(4);
_preserve_end = .;
} > bram
}
miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit/stm32_2m+8m_xram.ld 0 → 100644
View file @ ca9c636f
/*
* C++ enabled linker script for stm32f769ni (2M FLASH, 512K RAM, 8MB XRAM)
* Developed by TFT: Terraneo Federico Technologies
* Optimized for use with the Miosix kernel
*/
/*
* This linker script puts:
* - read only data and code (.text, .rodata, .eh_*) in FLASH
* - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM
* - .data, .bss, stacks and heap in the external 8MB SDRAM.
*/
/*
* The main stack is used for interrupt handling by the kernel.
*
* *** Readme ***
* This linker script places the main stack (used by the kernel for interrupts)
* at the bottom of the ram, instead of the top. This is done for two reasons:
*
* - as an optimization for microcontrollers with little ram memory. In fact
* the implementation of malloc from newlib requests memory to the OS in 4KB
* block (except the first block that can be smaller). This is probably done
* for compatibility with OSes with an MMU and paged memory. To see why this
* is bad, consider a microcontroller with 8KB of ram: when malloc finishes
* up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will
* fail because the top part of the ram is used by the main stack. As a
* result, the top part of the memory will not be used by malloc, even if
* available (and it is nearly *half* the ram on an 8KB mcu). By placing the
* main stack at the bottom of the ram, the upper 4KB block will be entirely
* free and available as heap space.
*
* - In case of main stack overflow the cpu will fault because access to memory
* before the beginning of the ram faults. Instead with the default stack
* placement the main stack will silently collide with the heap.
* Note: if increasing the main stack size also increase the ORIGIN value in
* the MEMORY definitions below accordingly.
*/
_main_stack_size = 512; /* main stack = 512Bytes */
_main_stack_top = 0x20000000 + _main_stack_size;
ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error");
/* Mapping the heap into XRAM */
_heap_end = 0xd0000000 + 8M; /* end of available ram */
/* Identify the Entry Point */
ENTRY(_Z13Reset_Handlerv)
/*
* Specify the memory areas
*
* NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled
* Memory). Technically, we could use this as normal RAM as there's a way for
* the DMA to access it, but the datasheet is unclear about performance
* penalties for doing so. To avoid nonuniform DMA memory access latencies,
* we leave this 128KB DTCM unused except for the first 512Bytes which are for
* the interrupt stack. This leaves us with 384KB of RAM
*/
MEMORY
{
xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M
sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K
dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */
bram(rw) : ORIGIN = 0x40024000, LENGTH = 4K /* Bakup SRAM */
flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M
}
/* now define the output sections */
SECTIONS
{
. = 0;
/* .text section: code goes to flash */
.text :
{
/* Startup code must go at address 0 */
KEEP(*(.isr_vector))
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
/* these sections for thumb interwork? */
*(.glue_7)
*(.glue_7t)
/* these sections for C++? */
*(.gcc_except_table)
*(.gcc_except_table.*)
*(.ARM.extab*)
*(.gnu.linkonce.armextab.*)
. = ALIGN(4);
/* .rodata: constant data */
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
/* C++ Static constructors/destructors (eabi) */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__miosix_init_array_start = .;
KEEP (*(SORT(.miosix_init_array.*)))
KEEP (*(.miosix_init_array))
__miosix_init_array_end = .;
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
/* C++ Static constructors/destructors (elf) */
. = ALIGN(4);
_ctor_start = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
_ctor_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
} > flash
/* .ARM.exidx is sorted, so has to go in its own output section. */
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > flash
__exidx_end = .;
/*
* .data section: global variables go to xram, but also store a copy to
* flash to initialize them
*/
.data : ALIGN(8)
{
_data = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
_edata = .;
} > xram AT > flash
_etext = LOADADDR(.data);
/* .bss section: uninitialized global variables go to xram */
_bss_start = .;
.bss :
{
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
. = ALIGN(8);
} > xram
_bss_end = .;
_end = .;
PROVIDE(end = .);
.preserve(NOLOAD) : ALIGN(4)
{
_preserve_start = .;
. = ALIGN(4);
*(.preserve);
*(.preserve*);
. = ALIGN(4);
_preserve_end = .;
} > bram
}
miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp
View file @ ca9c636f
......@@ -21,11 +21,26 @@
* Never returns.
*/
void program_startup() __attribute__((noreturn));
void program_startup() {
// Cortex M7 core appears to get out of reset with interrupts already
// enabled
void program_startup()
{
//Cortex M7 core appears to get out of reset with interrupts already enabled
__disable_irq();
/**
* SystemInit() is called *before* initializing .data and zeroing .bss
* Despite all startup files provided by ST do the opposite, there are three
* good reasons to do so:
* 1. First, the CMSIS specifications say that SystemInit() must not access
* global variables, so it is actually possible to call it before
* 2. Second, when running Miosix with the xram linker scripts .data and
* .bss are placed in the external RAM, so we *must* call SystemInit(),
* which enables xram, before touching .data and .bss
* 3. Third, this is a performance improvement since the loops that
* initialize .data and zeros .bss now run with the CPU at full speed
* instead of 8MHz
*/
SystemInit();
miosix::IRQconfigureCache();
// These are defined in the linker script
......@@ -49,30 +64,15 @@ void program_startup() {
// If main returns, reboot
NVIC_SystemReset();
for (;;)
;
for(;;) ;
}
/**
* Reset handler, called by hardware immediately after reset
*/
void Reset_Handler() __attribute__((__interrupt__, noreturn));
void Reset_Handler() {
/**
* SystemInit() is called *before* initializing .data and zeroing .bss
* Despite all startup files provided by ST do the opposite, there are three
* good reasons to do so:
* 1. First, the CMSIS specifications say that SystemInit() must not access
* global variables, so it is actually possible to call it before
* 2. Second, when running Miosix with the xram linker scripts .data and
* .bss are placed in the external RAM, so we *must* call SystemInit(),
* which enables xram, before touching .data and .bss
* 3. Third, this is a performance improvement since the loops that
* initialize .data and zeros .bss now run with the CPU at full speed
* instead of 8MHz
*/
SystemInit();
void Reset_Handler()
{
/*
* Load into the program stack pointer the heap end address and switch from
* the msp to sps.
......@@ -86,8 +86,7 @@ void Reset_Handler() {
"msr psp, r0 \n\t"
"movw r0, #2 \n\n" // Set the control register to use
"msr control, r0 \n\t" // the process stack
"isb \n\t" ::
: "r0");
"isb \n\t":::"r0");
program_startup();
}
......@@ -227,7 +226,8 @@ extern char _main_stack_top asm("_main_stack_top");
// Interrupt vectors, must be placed @ address 0x00000000
// The extern declaration is required otherwise g++ optimizes it out
extern void (*const __Vectors[])();
void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = {
void (*const __Vectors[])() __attribute__((section(".isr_vector"))) =
{
reinterpret_cast<void (*)()>(&_main_stack_top), /* Stack pointer*/
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
......
miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp
View file @ ca9c636f
......@@ -57,7 +57,8 @@ namespace miosix {
// Initialization
//
void IRQbspInit() {
void IRQbspInit()
{
// Enable all gpios
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN |
......@@ -82,15 +83,14 @@ void IRQbspInit() {
ledOn();
delayMs(100);
ledOff();
auto tx = Gpio<GPIOD_BASE, 8>::getPin();
tx.alternateFunction(7);
auto rx = Gpio<GPIOD_BASE, 9>::getPin();
rx.alternateFunction(7);
auto tx=Gpio<GPIOD_BASE,8>::getPin(); tx.alternateFunction(7);
auto rx=Gpio<GPIOD_BASE,9>::getPin(); rx.alternateFunction(7);
DefaultConsole::instance().IRQset(intrusive_ref_ptr<Device>(
new STM32Serial(3, defaultSerialSpeed, tx, rx)));
}
void bspInit2() {
void bspInit2()
{
#ifdef WITH_FILESYSTEM
basicFilesystemSetup(SDIODriver::instance());
#endif //WITH_FILESYSTEM
......@@ -100,7 +100,8 @@ void bspInit2() {
// Shutdown and reboot
//
void shutdown() {
void shutdown()
{
ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
#ifdef WITH_FILESYSTEM
......@@ -108,11 +109,11 @@ void shutdown() {
#endif //WITH_FILESYSTEM
disableInterrupts();
for (;;)
;
for(;;) ;
}
void reboot() {
void reboot()
{
ioctl(STDOUT_FILENO,IOCTL_SYNC,0);
#ifdef WITH_FILESYSTEM
......
miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h
View file @ ca9c636f
......@@ -52,13 +52,15 @@ typedef Gpio<GPIOB_BASE, 7> userLed2;
typedef Gpio<GPIOB_BASE,14> userLed3;
typedef Gpio<GPIOC_BASE,13> userBtn;
inline void ledOn() {
inline void ledOn()
{
userLed1::high();
userLed2::high();
userLed3::high();
}
inline void ledOff() {
inline void ledOff()
{
userLed1::low();
userLed2::low();
userLed3::low();
......
miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp
View file @ ca9c636f
......@@ -21,7 +21,8 @@
* Never returns.
*/
void program_startup() __attribute__((noreturn));
void program_startup() {
void program_startup()
{
// Cortex M7 core appears to get out of reset with interrupts already
// enabled
__disable_irq();
......@@ -49,15 +50,15 @@ void program_startup() {
// If main returns, reboot
NVIC_SystemReset();
for (;;)
;
for(;;) ;
}
/**
* Reset handler, called by hardware immediately after reset
*/
void Reset_Handler() __attribute__((__interrupt__, noreturn));
void Reset_Handler() {
void Reset_Handler()
{
/**
* SystemInit() is called *before* initializing .data and zeroing .bss
* Despite all startup files provided by ST do the opposite, there are three
......@@ -95,8 +96,7 @@ void Reset_Handler() {
"msr psp, r0 \n\t"
"movw r0, #2 \n\n" // Set the control register to use
"msr control, r0 \n\t" // the process stack
"isb \n\t" ::
: "r0");
"isb \n\t":::"r0");
program_startup();
}
......@@ -236,7 +236,8 @@ extern char _main_stack_top asm("_main_stack_top");
// Interrupt vectors, must be placed @ address 0x00000000
// The extern declaration is required otherwise g++ optimizes it out
extern void (*const __Vectors[])();
void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = {
void (*const __Vectors[])() __attribute__((section(".isr_vector"))) =
{
reinterpret_cast<void (*)()>(&_main_stack_top), /* Stack pointer*/
Reset_Handler, /* Reset Handler */
NMI_Handler, /* NMI Handler */
......
miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp
View file @ ca9c636f
......@@ -57,13 +57,15 @@ namespace miosix {
// Initialization
//
static void sdramCommandWait() {
static void sdramCommandWait()
{
for(int i=0;i<0xffff;i++)
if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0)
return;
}
void configureSdram() {
void configureSdram()
{
// Enable all gpios, passing clock
RCC->AHB1ENR |=
RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN |
......@@ -237,7 +239,8 @@ void configureSdram() {
#endif
}
void IRQbspInit() {
void IRQbspInit()
{
//If using SDRAM GPIOs are enabled by configureSdram(), else enable them here
#ifndef __ENABLE_XRAM
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN |
......@@ -262,7 +265,8 @@ void IRQbspInit() {
defaultSerial, defaultSerialSpeed, STM32Serial::NOFLOWCTRL)));
}
void bspInit2() {
void bspInit2()
{
#ifdef WITH_FILESYSTEM
basicFilesystemSetup(SDIODriver::instance());
#endif // WITH_FILESYSTEM
......@@ -272,7 +276,8 @@ void bspInit2() {
// Shutdown and reboot
//
void shutdown() {
void shutdown()
{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
#ifdef WITH_FILESYSTEM
......@@ -280,11 +285,11 @@ void shutdown() {
#endif // WITH_FILESYSTEM
disableInterrupts();
for (;;)
;
for(;;) ;
}
void reboot() {
void reboot()
{
ioctl(STDOUT_FILENO, IOCTL_SYNC, 0);
#ifdef WITH_FILESYSTEM
......
miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h
View file @ ca9c636f
......@@ -60,13 +60,15 @@ typedef Gpio<GPIOA_BASE, 12> userLed3;
typedef Gpio<GPIOA_BASE,0> userBtn;
typedef Gpio<GPIOI_BASE,15> sdCardDetect;
inline void ledOn() {
inline void ledOn()
{
userLed1::high();
userLed2::high();
userLed3::high();
}
inline void ledOff() {
inline void ledOff()
{
userLed1::low();
userLed2::low();
userLed3::low();
......
miosix/config/Makefile.inc
View file @ ca9c636f
......@@ -2954,10 +2954,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
CFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO
CXXFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO
## Select the SDMMC peripheral to use for the filesystem
SD := -D__SDMMC1
# SD := -D__SDMMC2
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
......@@ -2993,10 +2989,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
CFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO
CXXFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO
## Select the SDMMC peripheral to use for the filesystem
SD := -D__SDMMC1
# SD := -D__SDMMC2
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000
......@@ -3036,10 +3028,6 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
## Enables the initialization of the external 16MB SDRAM memory
XRAM := -D__ENABLE_XRAM
## Select the SDMMC peripheral to use for the filesystem
# SD := -D__SDMMC1
SD := -D__SDMMC2
## Select clock frequency (HSE_VALUE is the xtal on board, fixed)
CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_216MHz=216000000
......@@ -3071,9 +3059,9 @@ else ifeq ($(ARCH),cortexM7_stm32f7)
AFLAGS_BASE := $(ARCHOPTS)
CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
$(SD) $(ARCHOPTS) $(OPT_OPTIMIZATION) -c
$(ARCHOPTS) $(OPT_OPTIMIZATION) -c
CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) $(SRAM_BOOT)\
$(SD) $(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
$(ARCHOPTS) $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -c
LFLAGS_BASE := $(ARCHOPTS) -Wl,--gc-sections,-Map,main.map \
-Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \
$(OPT_OPTIMIZATION) -nostdlib
......