[I2C] Created new low-level (for stm32f4) and high-level I2C drivers

Low-level driver features (specific for the stm32f4 family):
- 7-bit (tested) and 10-bit (not tested yet) addressing;
- Speed modes: Standard (100kHz clock) and Fast (400kHz clock);
- Compatibility with all I2C peripherals till I2C4 (easy to extend to additional ones);
- Internal configuration of the pins in order to avoid forgetting to set them to ALTERNATE_OD mode (so, avoiding possibility of short-circuits between master and slave);
- The configurations of the slave (slave address, addressing mode and speed mode) we want to communicate with are setted before each read/write on the bus;
- Support for the reStart condition when wanting to write and then read from the same slave;
- Usage of interrupts when possible; In two cases we need polling anyway (limited to a parameter to avoid infinite polling): 
    . I2C_SR2_BUSY doesn't generate an interrupt and we can't communicate with the bus in BUSY state. 
    . I2C_SR1_SB do generate an interrupt, but its handling is a bit tricky since other interrupts are generated in the case of a reStart condition; also, using the interrupt for this, there would be the risk of a deadlock.
- Resilience to bus deadlocks;

High-level driver features:
- Resilience to bus deadlocks embedded before any operation on the bus;
- Implementation of higher level methods for using the bus;
- Possibility to have a synchronized version of the driver;