Skip to content
Snippets Groups Projects
Commit fde561c1 authored by Niccolò Betto's avatar Niccolò Betto Committed by Davide Mor
Browse files

[SPI] Workaround for non-empty FIFO after re-configure

parent c4ce666d
No related branches found
No related tags found
1 merge request!235[SPI] Workaround for non-empty FIFO after re-configure
Pipeline #8326 canceled
...@@ -132,6 +132,8 @@ public: ...@@ -132,6 +132,8 @@ public:
void waitPeripheral(); void waitPeripheral();
void flushRxBuffer();
/** /**
* @brief Configures and enables the bus with the provided configuration. * @brief Configures and enables the bus with the provided configuration.
* *
...@@ -402,6 +404,12 @@ inline void SPIBus::waitPeripheral() ...@@ -402,6 +404,12 @@ inline void SPIBus::waitPeripheral()
; ;
} }
inline void SPIBus::flushRxBuffer()
{
while ((spi->SR & SPI_SR_RXNE) != 0)
spi->DR;
}
inline void SPIBus::configure(SPIBusConfig newConfig) inline void SPIBus::configure(SPIBusConfig newConfig)
{ {
// Do not reconfigure if already in the correct configuration. // Do not reconfigure if already in the correct configuration.
...@@ -520,8 +528,18 @@ inline void SPIBus::write16(const uint16_t* data, size_t nBytes) ...@@ -520,8 +528,18 @@ inline void SPIBus::write16(const uint16_t* data, size_t nBytes)
inline uint8_t SPIBus::transfer(uint8_t data) inline uint8_t SPIBus::transfer(uint8_t data)
{ {
// At the start of the transfer we assume that the RX FIFO is empty /*
assert((spi->SR & SPI_SR_RXNE) == 0); * On STM32F7xx and STM32F4xx series chips, on SPI3 only, the RXNE flag
* may be erroneously set at the beginning of the transaction with the
* RX buffer containing garbage data.
* On F7xx chips the issue can be reproduced by re-configuring the SPI from
* Mode 0 (CPOL=0, CPHA=0) to Mode 3 (CPOL=1, CPHA=1), after performing at
* least one transaction in Mode 0.
*
* We work around this issue by flushing the RX buffer at the beginning of
* the transaction.
*/
flushRxBuffer();
// Wait until the peripheral is ready to transmit // Wait until the peripheral is ready to transmit
while ((spi->SR & SPI_SR_TXE) == 0) while ((spi->SR & SPI_SR_TXE) == 0)
......
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment