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    • Update Direct Memory Access authored by Alberto Nidasio's avatar Alberto Nidasio
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    Direct-Memory-Access.md
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    ...@@ -21,7 +21,7 @@ A DMA transfer is characterized by the following properties: ...@@ -21,7 +21,7 @@ A DMA transfer is characterized by the following properties:
    - Peripheral to memory - Peripheral to memory
    - Memory to memory (only DMA2) - Memory to memory (only DMA2)
    - **Transfer size**: number of data items defined by the DMA_SxNDTR register value - **Transfer size**: number of data items defined by the DMA_SxNDTR register value
    - **Address incrementation**: tt is possible to configure the DMA to automatically increment the source and/or destination address after each data item transfer. - **Address incrementation**: it is possible to configure the DMA stream to automatically increment the source and/or destination addresses after each data item transfer.
    - **Data width**: - **Data width**:
    - Byte (8 bits) - Byte (8 bits)
    - Half-word (16 bits) - Half-word (16 bits)
    ...@@ -48,7 +48,7 @@ Each DMA stream implements also a 4 word (16 byte) FIFO which can be used to buf ...@@ -48,7 +48,7 @@ Each DMA stream implements also a 4 word (16 byte) FIFO which can be used to buf
    ## Memory to peripheral mode ## Memory to peripheral mode
    When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream **immediately fills the FIFO** to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. This require that the data are already available in the source address. When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream **immediately fills the FIFO** to ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral. This requires that the data are already available in the source address.
    Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined thresholdd level, the FIFO is fully reloaded with data from memory. As said, in direct mode the memory is access for each data item. Each time a peripheral request occurs, the contents of the FIFO are drained and stored into the destination. When the level of the FIFO is lower than or equal to the predefined thresholdd level, the FIFO is fully reloaded with data from memory. As said, in direct mode the memory is access for each data item.
    ...@@ -84,9 +84,9 @@ The BSY flag can be monitored to ensure that the SPI communication is complete. ...@@ -84,9 +84,9 @@ The BSY flag can be monitored to ensure that the SPI communication is complete.
    The following code is part of a complete example that can be found [here](https://git.skywarder.eu/alberto.nidasio/skyward-dma-examples/-/blob/master/src/entrypoints/spi-ads1118.cpp). The following code is part of a complete example that can be found [here](https://git.skywarder.eu/alberto.nidasio/skyward-dma-examples/-/blob/master/src/entrypoints/spi-ads1118.cpp).
    The use of SPI with DMA requires 3 main steps: The use of SPI with DMA requires 3 main steps:
    - Configuring the SPI controller 1. Configuring the SPI controller
    - Configuring the DMA streams for transmission and reception 2. Configuring the DMA streams for transmission and reception
    - Start the data transfer 3. Start the data transfer
    Configuring the SPI controller has nothing special except enabling the use of DMA. Configuring the SPI controller has nothing special except enabling the use of DMA.
    ......