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# STM32 Backup SRAM
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## Overview
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The STM32F2/F4 microcontrollers provide a backup domain that includes 4 Kbytes of backup SRAM. This region can be considered as an internal EEPROM when VBAT is present: its content is preserved upon reset if VBAT is connected. This means that it can be used as a safe-guard memory (SGM).
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:information_source: INFO :information_source: *Of course you can connect VBAT to the board's power supply, but it would not provide the same reliability level as having a backup battery or a different power supply.*
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The backup region also includes twenty 32-bit registers that can be used store a total of 80 bytes (word-aligned). Backup registers are not reset by a system, a power reset, or when the device wakes up from the standby mode.
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The Miosix safe-guard memory driver provides an interface to enable the backup SRAM, to enable/disable write protection and to retrieve the last reset reason of the board.
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You can find the driver in `miosix-kernel/miosix/arch/common/drivers`.
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## Usage
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First of all you have to enable the backup SRAM: the backup domain is not readable until the backup SRAM clock is enabled.
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Moreover, after a reset, the backup domain is protected against possible unwanted write accesses, so you have to disable write protection before being able to write again to the backup region.
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The Miosix SGM driver constructor prepares the backup domain for you: it enables the backup clock and disables the write protection. It also retrieves the last board reset reason.
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Please remember that the backup domain content is wiped by the driver if, after the reset, the `RCC_CSR_SFTRSTF` (i.e. software reset) flag is not set in the `RCC->CSR` register.
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⚠️ WARNING ⚠️ *Notice that more than one flag could be set at the same time in the `RCC->CSR` register!*
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After enabling it, in order to read/write from/to the backup domain, you can simply use pointers or standard C/C++ functions, such as `memcpy` (better performance), starting from the backup region base address, which is `BKPSRAM_BASE`.
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#### Example
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This basic example shows how you can write to the backup SRAM using the Miosix SGM driver.
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In a very similar way you can also read the data you stored.
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```cpp
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#include <miosix.h>
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#include <arch/common/drivers/stm32_sgm.h>
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uint8_t* backup_sram_base_address = (uint8_t*) BKPSRAM_BASE;
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int main() {
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uint8_t data[5] = {1, 2, 3, 4, 5};
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uint16_t bytes_num = 5;
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uint16_t offset = 3;
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// enables the backup clock, disables write protection
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// and retrieves the last reset reason
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SGM &sgm = SGM::instance(); // singleton object
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for (uint16_t i = 0; i < bytes_num; i++) {
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*(backup_sram_base_address + offset + i) = *(data + i);
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}
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return 0;
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}
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```
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## Linker Script
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In the board's linker script, a backup memory region has to be defined:
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```
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MEMORY
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{
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...
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backupram(rw) : ORIGIN = 0x40024000, LENGTH = 4K
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}
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```
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Where in this case `0x40024000` is the backup SRAM base address and `4K` (4 Kbytes) is its size.
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A section in which `_preserve_start` and `_preserve_end` are defined is also needed, since these two addresses are used by the Miosix SGM driver.
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```
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.preserve(NOLOAD) : ALIGN(4)
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{
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_preserve_start = .;
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. = ALIGN(4);
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*(.preserve);
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*(.preserve*);
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. = ALIGN(4);
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_preserve_end = .;
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} > backupram
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```
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The `(NOLOAD)` directive will mark a section to not be loaded at run time. The linker will process the section normally, but will mark it so that a program loader will not load it into memory.
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⚠️ WARNING ⚠️ *Remember to comment out the assignement to `_end` before adding the `preserve` section.*
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```
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_end = .;
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PROVIDE(end = .);
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```
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Refer to the [Skyward STM32F429ZI Anakin board](https://git.skywarder.eu/scs/miosix-kernel/-/blob/master/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+256k_rom.ld) linker script as an example.
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## Pros and Cons
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Pros:
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* Useful to store relevant information that has to be persisted after a reset
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* Included in STM32F2/F4 microcontrollers
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* Simple to use
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Cons:
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* Limited storage region
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* Not actually a persistent storage
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* VBAT requires an additional power supply or backup battery for better reliability
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## References
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* [Miosix OS safe-guard memory driver](https://github.com/fedetft/miosix-kernel/blob/master/miosix/arch/common/drivers/stm32_sgm.h)
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* [StackOverflow - How to use backup SRAM as EEPROM in STM32F4](https://stackoverflow.com/questions/20667754/how-to-use-backup-sram-as-eeprom-in-stm32f4)
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* [Skyward's STM32F429ZI Anakin board](https://git.skywarder.eu/scs/miosix-kernel/-/tree/master/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin)
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* [RM0090, Reference Manual - STM32F405/415, STM32F407/417, STM32F427/437 and STM32F429/439 advanced Arm-based 32-bit MCUs (mainly sections 2.3.1, 5.1.2, 6.3.20/7.3.20)](https://www.st.com/resource/en/reference_manual/dm00031020-stm32f405-415-stm32f407-417-stm32f427-437-and-stm32f429-439-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf) |