zero-init ram on boot; fix timing reg value

miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/core/stage_1_boot.cpp

@@ -82,6 +82,12 @@ void Reset_Handler()
     miosix::configureSdram();
     #endif  //__ENABLE_XRAM
 
+
+    for(uint32_t address = 0xd0000000; address < 0xd1000000; address += 4) {
+        *((volatile uint32_t*) address) = (uint32_t) 0;
+    }
+
+
     /*
      * Load into the program stack pointer the heap end address and switch from
      * the msp to sps.

miosix/arch/cortexM7_stm32f7/stm32f767zi_compute_unit_v2/interfaces-impl/bsp.cpp

@@ -211,8 +211,8 @@ void configureSdram() {
 // 8. Program the refresh rate (4K / 32ms)
 // 64ms / 8192 = 7.8125us
 #ifdef SYSCLK_FREQ_216MHz
-    // 7.8125us * 133MHz = 1039 - 20 = 1019
-    FMC_Bank5_6->SDRTR = 1019 << FMC_SDRTR_COUNT_Pos;
+    // 7.8125us * 108MHz = 844 - 20 = 824
+    FMC_Bank5_6->SDRTR = 824 << FMC_SDRTR_COUNT_Pos;
 #else
 #error No SDRAM refresh timings for this clock
 #endif